projects / apple / xnu.git / blame
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|---|---|---|
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1 | /* |
| 2 | * Copyright (c) 2003 Apple Computer, Inc. All rights reserved. | |
| 3 | * | |
| 4 | * @APPLE_LICENSE_HEADER_START@ | |
| 5 | * | |
| e5568f75 A |
6 | * The contents of this file constitute Original Code as defined in and |
| 7 | * are subject to the Apple Public Source License Version 1.1 (the | |
| 8 | * "License"). You may not use this file except in compliance with the | |
| 9 | * License. Please obtain a copy of the License at | |
| 10 | * http://www.apple.com/publicsource and read it before using this file. | |
| 55e303ae | 11 | * |
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12 | * This Original Code and all software distributed under the License are |
| 13 | * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER | |
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14 | * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, |
| 15 | * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, | |
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16 | * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the |
| 17 | * License for the specific language governing rights and limitations | |
| 18 | * under the License. | |
| 55e303ae A |
19 | * |
| 20 | * @APPLE_LICENSE_HEADER_END@ | |
| 21 | */ | |
| 22 | ||
| 23 | #define ASSEMBLER | |
| 24 | #include <sys/appleapiopts.h> | |
| 25 | #include <ppc/asm.h> // EXT, LEXT | |
| 26 | #include <machine/cpu_capabilities.h> | |
| 27 | #include <machine/commpage.h> | |
| 28 | ||
| 29 | .text | |
| 30 | .align 2 | |
| 31 | .globl EXT(commpage_flush_dcache) | |
| 32 | .globl EXT(commpage_flush_icache) | |
| 33 | ||
| 34 | ||
| 35 | // ********************************************* | |
| 36 | // * C O M M P A G E _ F L U S H _ D C A C H E * | |
| 37 | // ********************************************* | |
| 38 | // | |
| 39 | // r3 = ptr to 1st byte to flush | |
| 40 | // r4 = length to flush (may be 0) | |
| 41 | ||
| 42 | commpage_flush_dcache: | |
| 43 | cmpwi r4,0 // length 0? | |
| 44 | lhz r5,_COMM_PAGE_CACHE_LINESIZE(0) | |
| 45 | subi r9,r5,1 // get (linesize-1) | |
| 46 | and r0,r3,r9 // get offset within line of 1st byte | |
| 47 | add r4,r4,r0 // adjust length so we flush them all | |
| 48 | add r4,r4,r9 // round length up... | |
| 49 | andc r4,r4,r9 // ...to multiple of cache lines | |
| 50 | beqlr-- // length was 0, so exit | |
| 51 | 1: | |
| 52 | sub. r4,r4,r5 // more to go? | |
| 53 | dcbf 0,r3 // flush another line | |
| 54 | add r3,r3,r5 | |
| 55 | bne 1b | |
| 56 | sync // make sure lines are flushed before we return | |
| 57 | blr | |
| 58 | ||
| 59 | COMMPAGE_DESCRIPTOR(commpage_flush_dcache,_COMM_PAGE_FLUSH_DCACHE,0,0,0) // matches all CPUs | |
| 60 | ||
| 61 | ||
| 62 | // ********************************************* | |
| 63 | // * C O M M P A G E _ F L U S H _ I C A C H E * | |
| 64 | // ********************************************* | |
| 65 | // | |
| 66 | // r3 = ptr to 1st byte to flush | |
| 67 | // r4 = length to flush (may be 0) | |
| 68 | ||
| 69 | commpage_flush_icache: | |
| 70 | cmpwi r4,0 // length 0? | |
| 71 | lhz r5,_COMM_PAGE_CACHE_LINESIZE(0) | |
| 72 | subi r9,r5,1 // get (linesize-1) | |
| 73 | and r0,r3,r9 // get offset within line of 1st byte | |
| 74 | add r4,r4,r0 // adjust length so we flush them all | |
| 75 | mr r7,r3 // copy ptr | |
| 76 | add r4,r4,r9 // round length up... | |
| 77 | andc r4,r4,r9 // ...to multiple of cache lines | |
| 78 | mr r6,r4 // copy length | |
| 79 | beqlr-- // length was 0, so exit | |
| 80 | 1: | |
| 81 | sub. r4,r4,r5 // more to go? | |
| 82 | dcbf 0,r3 // flush another line | |
| 83 | add r3,r3,r5 | |
| 84 | bne 1b | |
| 85 | sync // make sure lines are flushed | |
| 86 | 2: | |
| 87 | sub. r6,r6,r5 // more to go? | |
| 88 | icbi 0,r7 | |
| 89 | add r7,r7,r5 | |
| 90 | bne 2b | |
| 91 | isync // make sure we haven't prefetched old instructions | |
| 92 | ||
| 93 | blr | |
| 94 | ||
| 95 | COMMPAGE_DESCRIPTOR(commpage_flush_icache,_COMM_PAGE_FLUSH_ICACHE,0,0,0) // matches all CPUs | |
| 96 | ||
| 97 |