[apple/xnu.git] / osfmk / mach / ppc / processor_info.h

/*
 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_LICENSE_HEADER_START@
 * 
 * The contents of this file constitute Original Code as defined in and
 * are subject to the Apple Public Source License Version 1.1 (the
 * "License").  You may not use this file except in compliance with the
 * License.  Please obtain a copy of the License at
 * http://www.apple.com/publicsource and read it before using this file.
 * 
 * This Original Code and all software distributed under the License are
 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
 * License for the specific language governing rights and limitations
 * under the License.
 * 
 * @APPLE_LICENSE_HEADER_END@
 */
/*
 *	File:	mach/ppc/processor_info.h
 *
 *	Data structure definitions for ppc specific processor control
 */


#ifndef	_MACH_PPC_PROCESSOR_INFO_H_
#define _MACH_PPC_PROCESSOR_INFO_H_

#include <mach/machine.h>

/* processor_control command operations */
#define PROCESSOR_PM_SET_REGS     1     /* Set Performance Monitor Registers  */
#define PROCESSOR_PM_SET_MMCR     2     /* Set Monitor Mode Controls Registers  */
#define PROCESSOR_PM_CLR_PMC      3     /* Clear Performance Monitor Counter Registers */

/* 
 * Performance Monitor Register structures
 */

typedef union {
	unsigned int word;
	struct {
	        unsigned int dis	: 1;
		unsigned int dp 	: 1;
		unsigned int du 	: 1;
	        unsigned int dms	: 1;
	        unsigned int dmr	: 1;
	        unsigned int reserved3	: 1;        /* enint         */
	        unsigned int reserved4	: 1;        /* discount      */
	        unsigned int reserved5	: 2;        /* rtcselect     */
	        unsigned int reserved6	: 1;        /* intonbittrans */
	        unsigned int threshold	: 6;
	        unsigned int reserved7	: 1;        /* pmc1intcontrol */
	        unsigned int reserved8	: 1;        /* pmcintcontrol  */
	        unsigned int reserved9	: 1;        /* pmctrigger     */
	        unsigned int pmc1select	: 7;
	        unsigned int pmc2select	: 6;
	}bits;
}mmcr0_t;

typedef union {
	unsigned int word;
	struct {
	        unsigned int pmc3select	: 5;
	        unsigned int pmc4select	: 5;
	        unsigned int reserved	: 22;
	}bits;
}mmcr1_t;

typedef union {
	unsigned int word;
	struct {
	        unsigned int threshmult	 : 1;
	        unsigned int reserved	 : 31;
	}bits;
}mmcr2_t;

typedef union {
	unsigned int word;
	struct {
	        unsigned int ov : 1;        /* overflow value */
	        unsigned int cv : 31;       /* countervalue */
	}bits;
}pmcn_t;


/* Processor Performance Monitor Registers definitions */

struct processor_pm_regs {
      union {
	mmcr0_t mmcr0;
        mmcr1_t mmcr1;
        mmcr2_t mmcr2;
      }u;
      pmcn_t pmc[2];
};

typedef struct processor_pm_regs processor_pm_regs_data_t;
typedef struct processor_pm_regs *processor_pm_regs_t;
#define PROCESSOR_PM_REGS_COUNT \
        (sizeof(processor_pm_regs_data_t) / sizeof (unsigned int))

#define PROCESSOR_PM_REGS_COUNT_POWERPC_604 \
            (PROCESSOR_PM_REGS_COUNT * 1 )

#define PROCESSOR_PM_REGS_COUNT_POWERPC_604e \
            (PROCESSOR_PM_REGS_COUNT * 2 )

#define PROCESSOR_PM_REGS_COUNT_POWERPC_750 \
            (PROCESSOR_PM_REGS_COUNT * 2 )

#define PROCESSOR_PM_REGS_COUNT_POWERPC_7400 \
            (PROCESSOR_PM_REGS_COUNT * 3 )

typedef unsigned int processor_temperature_data_t;
typedef unsigned int *processor_temperature_t;

#define PROCESSOR_TEMPERATURE_COUNT 1

union processor_control_data {
        processor_pm_regs_data_t cmd_pm_regs[3];
};

struct processor_control_cmd {
    integer_t      cmd_op;
    cpu_type_t     cmd_cpu_type;
    cpu_subtype_t  cmd_cpu_subtype;
    union processor_control_data u;
};

typedef struct processor_control_cmd   processor_control_cmd_data_t;
typedef struct processor_control_cmd   *processor_control_cmd_t;
#define cmd_pm_regs u.cmd_pm_regs;
#define cmd_pm_ctls u.cmd_pm_ctls;

#define PROCESSOR_CONTROL_CMD_COUNT \
    (((sizeof(processor_control_cmd_data_t)) - \
      (sizeof(union processor_control_data))) / sizeof (integer_t))

     /* x should be a processor_pm_regs_t */
#define PERFMON_MMCR0(x)    ((x)[0].u.mmcr0.word)
#define PERFMON_PMC1(x)     ((x)[0].pmc[0].word)
#define PERFMON_PMC2(x)     ((x)[0].pmc[1].word)
#define PERFMON_MMCR1(x)    ((x)[1].u.mmcr1.word)
#define PERFMON_PMC3(x)     ((x)[1].pmc[0].word)
#define PERFMON_PMC4(x)     ((x)[1].pmc[1].word)
#define PERFMON_MMCR2(x)    ((x)[2].u.mmcr2.word)

#define PERFMON_DIS(x)           ((x)[0].u.mmcr0.bits.dis)
#define PERFMON_DP(x)            ((x)[0].u.mmcr0.bits.dp)
#define PERFMON_DU(x)            ((x)[0].u.mmcr0.bits.du)
#define PERFMON_DMS(x)           ((x)[0].u.mmcr0.bits.dms)
#define PERFMON_DMR(x)           ((x)[0].u.mmcr0.bits.dmr)
#define PERFMON_THRESHOLD(x)     ((x)[0].u.mmcr0.bits.threshold)
#define PERFMON_PMC1SELECT(x)    ((x)[0].u.mmcr0.bits.pmc1select)
#define PERFMON_PMC2SELECT(x)    ((x)[0].u.mmcr0.bits.pmc2select)
#define PERFMON_PMC3SELECT(x)    ((x)[1].u.mmcr1.bits.pmc3select)
#define PERFMON_PMC4SELECT(x)    ((x)[1].u.mmcr1.bits.pmc4select)
#define PERFMON_THRESHMULT(x)    ((x)[2].u.mmcr2.bits.threshmult)
#define PERFMON_PMC1_CV(x)       ((x)[0].u.pmc[0].bits.cv)
#define PERFMON_PMC2_CV(x)       ((x)[0].u.pmc[1].bits.cv)
#define PERFMON_PMC3_CV(x)       ((x)[1].u.pmc[0].bits.cv)
#define PERFMON_PMC4_CV(x)       ((x)[1].u.pmc[1].bits.cv)

#endif	/* _MACH_PPC_PROCESSOR_INFO_H_ */
Commit	Line	Data
1c79356b A	1	/*
	2	* Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
	3	*
	4	* @APPLE_LICENSE_HEADER_START@
	5	*
	6	* The contents of this file constitute Original Code as defined in and
	7	* are subject to the Apple Public Source License Version 1.1 (the
	8	* "License"). You may not use this file except in compliance with the
	9	* License. Please obtain a copy of the License at
	10	* http://www.apple.com/publicsource and read it before using this file.
	11	*
	12	* This Original Code and all software distributed under the License are
	13	* distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
	14	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
	15	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
	17	* License for the specific language governing rights and limitations
	18	* under the License.
	19	*
	20	* @APPLE_LICENSE_HEADER_END@
	21	*/
	22	/*
	23	* File: mach/ppc/processor_info.h
	24	*
	25	* Data structure definitions for ppc specific processor control
	26	*/
	27
	28
	29	#ifndef _MACH_PPC_PROCESSOR_INFO_H_
	30	#define _MACH_PPC_PROCESSOR_INFO_H_
	31
	32	#include <mach/machine.h>
	33
	34	/* processor_control command operations */
	35	#define PROCESSOR_PM_SET_REGS 1 /* Set Performance Monitor Registers */
	36	#define PROCESSOR_PM_SET_MMCR 2 /* Set Monitor Mode Controls Registers */
	37	#define PROCESSOR_PM_CLR_PMC 3 /* Clear Performance Monitor Counter Registers */
	38
	39	/*
	40	* Performance Monitor Register structures
	41	*/
	42
	43	typedef union {
	44	unsigned int word;
	45	struct {
	46	unsigned int dis : 1;
	47	unsigned int dp : 1;
	48	unsigned int du : 1;
	49	unsigned int dms : 1;
	50	unsigned int dmr : 1;
	51	unsigned int reserved3 : 1; /* enint */
	52	unsigned int reserved4 : 1; /* discount */
	53	unsigned int reserved5 : 2; /* rtcselect */
	54	unsigned int reserved6 : 1; /* intonbittrans */
	55	unsigned int threshold : 6;
	56	unsigned int reserved7 : 1; /* pmc1intcontrol */
	57	unsigned int reserved8 : 1; /* pmcintcontrol */
	58	unsigned int reserved9 : 1; /* pmctrigger */
	59	unsigned int pmc1select : 7;
	60	unsigned int pmc2select : 6;
	61	}bits;
	62	}mmcr0_t;
	63
	64	typedef union {
65	unsigned int word;
66	struct {
67	unsigned int pmc3select : 5;
68	unsigned int pmc4select : 5;
69	unsigned int reserved : 22;
70	}bits;
71	}mmcr1_t;
72
73	typedef union {
74	unsigned int word;
75	struct {
76	unsigned int threshmult : 1;
77	unsigned int reserved : 31;
78	}bits;
79	}mmcr2_t;
80
81	typedef union {
82	unsigned int word;
83	struct {
84	unsigned int ov : 1; /* overflow value */
85	unsigned int cv : 31; /* countervalue */
86	}bits;
87	}pmcn_t;
88
89
90
91	/* Processor Performance Monitor Registers definitions */
92
93	struct processor_pm_regs {
94	union {
95	mmcr0_t mmcr0;
96	mmcr1_t mmcr1;
97	mmcr2_t mmcr2;
98	}u;
99	pmcn_t pmc[2];
100	};
101
102	typedef struct processor_pm_regs processor_pm_regs_data_t;
103	typedef struct processor_pm_regs *processor_pm_regs_t;
104	#define PROCESSOR_PM_REGS_COUNT \
105	(sizeof(processor_pm_regs_data_t) / sizeof (unsigned int))
106
107	#define PROCESSOR_PM_REGS_COUNT_POWERPC_604 \
108	(PROCESSOR_PM_REGS_COUNT * 1 )
109
110	#define PROCESSOR_PM_REGS_COUNT_POWERPC_604e \
111	(PROCESSOR_PM_REGS_COUNT * 2 )
112
113	#define PROCESSOR_PM_REGS_COUNT_POWERPC_750 \
114	(PROCESSOR_PM_REGS_COUNT * 2 )
115
116	#define PROCESSOR_PM_REGS_COUNT_POWERPC_7400 \
117	(PROCESSOR_PM_REGS_COUNT * 3 )
118
119	typedef unsigned int processor_temperature_data_t;
120	typedef unsigned int *processor_temperature_t;
121
122	#define PROCESSOR_TEMPERATURE_COUNT 1
123
124	union processor_control_data {
125	processor_pm_regs_data_t cmd_pm_regs[3];
126	};
127
128	struct processor_control_cmd {
129	integer_t cmd_op;
130	cpu_type_t cmd_cpu_type;
131	cpu_subtype_t cmd_cpu_subtype;
132	union processor_control_data u;
133	};
134
135	typedef struct processor_control_cmd processor_control_cmd_data_t;
136	typedef struct processor_control_cmd *processor_control_cmd_t;
137	#define cmd_pm_regs u.cmd_pm_regs;
138	#define cmd_pm_ctls u.cmd_pm_ctls;
139
140	#define PROCESSOR_CONTROL_CMD_COUNT \
141	(((sizeof(processor_control_cmd_data_t)) - \
142	(sizeof(union processor_control_data))) / sizeof (integer_t))
143
144	/* x should be a processor_pm_regs_t */
145	#define PERFMON_MMCR0(x) ((x)[0].u.mmcr0.word)
146	#define PERFMON_PMC1(x) ((x)[0].pmc[0].word)
147	#define PERFMON_PMC2(x) ((x)[0].pmc[1].word)
148	#define PERFMON_MMCR1(x) ((x)[1].u.mmcr1.word)
149	#define PERFMON_PMC3(x) ((x)[1].pmc[0].word)
150	#define PERFMON_PMC4(x) ((x)[1].pmc[1].word)
151	#define PERFMON_MMCR2(x) ((x)[2].u.mmcr2.word)
152
153	#define PERFMON_DIS(x) ((x)[0].u.mmcr0.bits.dis)
154	#define PERFMON_DP(x) ((x)[0].u.mmcr0.bits.dp)
155	#define PERFMON_DU(x) ((x)[0].u.mmcr0.bits.du)
156	#define PERFMON_DMS(x) ((x)[0].u.mmcr0.bits.dms)
157	#define PERFMON_DMR(x) ((x)[0].u.mmcr0.bits.dmr)
158	#define PERFMON_THRESHOLD(x) ((x)[0].u.mmcr0.bits.threshold)
159	#define PERFMON_PMC1SELECT(x) ((x)[0].u.mmcr0.bits.pmc1select)
160	#define PERFMON_PMC2SELECT(x) ((x)[0].u.mmcr0.bits.pmc2select)
161	#define PERFMON_PMC3SELECT(x) ((x)[1].u.mmcr1.bits.pmc3select)
162	#define PERFMON_PMC4SELECT(x) ((x)[1].u.mmcr1.bits.pmc4select)
163	#define PERFMON_THRESHMULT(x) ((x)[2].u.mmcr2.bits.threshmult)
164	#define PERFMON_PMC1_CV(x) ((x)[0].u.pmc[0].bits.cv)
165	#define PERFMON_PMC2_CV(x) ((x)[0].u.pmc[1].bits.cv)
166	#define PERFMON_PMC3_CV(x) ((x)[1].u.pmc[0].bits.cv)
167	#define PERFMON_PMC4_CV(x) ((x)[1].u.pmc[1].bits.cv)
168
169	#endif /* _MACH_PPC_PROCESSOR_INFO_H_ */
170