projects / apple / xnu.git / blame
| Commit | Line | Data |
|---|---|---|
| 0c530ab8 A |
1 | /* |
| 2 | * Copyright (c) 2006 Apple Computer, Inc. All rights reserved. | |
| 3 | * | |
| 2d21ac55 | 4 | * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ |
| 0c530ab8 | 5 | * |
| 2d21ac55 A |
6 | * This file contains Original Code and/or Modifications of Original Code |
| 7 | * as defined in and that are subject to the Apple Public Source License | |
| 8 | * Version 2.0 (the 'License'). You may not use this file except in | |
| 9 | * compliance with the License. The rights granted to you under the License | |
| 10 | * may not be used to create, or enable the creation or redistribution of, | |
| 11 | * unlawful or unlicensed copies of an Apple operating system, or to | |
| 12 | * circumvent, violate, or enable the circumvention or violation of, any | |
| 13 | * terms of an Apple operating system software license agreement. | |
| 0c530ab8 | 14 | * |
| 2d21ac55 A |
15 | * Please obtain a copy of the License at |
| 16 | * http://www.opensource.apple.com/apsl/ and read it before using this file. | |
| 17 | * | |
| 18 | * The Original Code and all software distributed under the License are | |
| 19 | * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER | |
| 0c530ab8 A |
20 | * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, |
| 21 | * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, | |
| 2d21ac55 A |
22 | * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. |
| 23 | * Please see the License for the specific language governing rights and | |
| 24 | * limitations under the License. | |
| 0c530ab8 | 25 | * |
| 2d21ac55 | 26 | * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ |
| 0c530ab8 A |
27 | */ |
| 28 | ||
| 29 | #include <platforms.h> | |
| 30 | #include <mach_kdb.h> | |
| 31 | ||
| 32 | #include <i386/asm.h> | |
| 33 | #include <i386/asm64.h> | |
| 34 | #include <i386/proc_reg.h> | |
| 35 | #include <i386/postcode.h> | |
| 36 | #include <assym.s> | |
| 37 | ||
| 38 | .data | |
| 39 | .align 3 | |
| 40 | .globl EXT(gdtptr64) | |
| 41 | /* align below right */ | |
| 42 | .word 0 | |
| 43 | LEXT(gdtptr64) | |
| 44 | .word Times(8,GDTSZ)-1 | |
| 45 | /* XXX really want .quad here */ | |
| 46 | .long EXT(master_gdt) | |
| 47 | .long KERNEL_UBER_BASE_HI32 /* must be in uber-space */ | |
| 48 | ||
| 49 | .align 3 | |
| 50 | .globl EXT(idtptr64) | |
| 51 | /* align below right */ | |
| 52 | .word 0 | |
| 53 | LEXT(idtptr64) | |
| 54 | .word Times(16,IDTSZ)-1 | |
| 55 | /* XXX really want .quad here */ | |
| 56 | .long EXT(master_idt64) | |
| 57 | .long KERNEL_UBER_BASE_HI32 /* must be in uber-space */ | |
| 58 | ||
| 59 | .text | |
| 60 | ||
| 61 | Entry(ml_load_desc64) | |
| 62 | ||
| 63 | ENTER_64BIT_MODE() | |
| 64 | ||
| 65 | POSTCODE(ML_LOAD_DESC64_ENTRY) | |
| 66 | ||
| 67 | lgdt EXT(gdtptr64) /* load GDT */ | |
| 68 | ||
| 69 | POSTCODE(ML_LOAD_DESC64_GDT) | |
| 70 | ||
| 71 | lidt EXT(idtptr64) /* load IDT */ | |
| 72 | ||
| 73 | POSTCODE(ML_LOAD_DESC64_IDT) | |
| 74 | ||
| 75 | movw $(KERNEL_LDT),%ax /* get LDT segment */ | |
| 76 | lldt %ax /* load LDT */ | |
| 77 | ||
| 78 | POSTCODE(ML_LOAD_DESC64_LDT) | |
| 79 | ||
| 80 | movw $(KERNEL_TSS),%ax | |
| 81 | ltr %ax /* set up KTSS */ | |
| 82 | ||
| 83 | POSTCODE(ML_LOAD_DESC64_EXIT) | |
| 84 | ||
| 85 | ENTER_COMPAT_MODE() | |
| 86 | ||
| 87 | ret | |
| 88 | ||
| 89 | ||
| 0c530ab8 A |
90 | Entry(ml_64bit_lldt) |
| 91 | /* (int32_t selector) */ | |
| 92 | ||
| 93 | FRAME | |
| 94 | ||
| 95 | ENTER_64BIT_MODE() | |
| 96 | ||
| 97 | movl B_ARG0, %eax | |
| 98 | lldt %ax | |
| 99 | ||
| 100 | ENTER_COMPAT_MODE() | |
| 101 | ||
| 102 | EMARF | |
| 103 | ret | |
| 104 | ||
| 105 | Entry(set_64bit_debug_regs) | |
| 106 | /* x86_debug_state64_t *ds */ | |
| 107 | ||
| 108 | FRAME | |
| 109 | ||
| 110 | ENTER_64BIT_MODE() | |
| 111 | ||
| 112 | mov B_ARG0, %edx | |
| 113 | mov DS64_DR0(%edx), %rax | |
| 114 | mov %rax, %dr0 | |
| 115 | mov DS64_DR1(%edx), %rax | |
| 116 | mov %rax, %dr1 | |
| 117 | mov DS64_DR2(%edx), %rax | |
| 118 | mov %rax, %dr2 | |
| 119 | mov DS64_DR3(%edx), %rax | |
| 120 | mov %rax, %dr3 | |
| 121 | ||
| 122 | ENTER_COMPAT_MODE() | |
| 123 | ||
| 124 | EMARF | |
| 125 | ret | |
| 126 | ||
| 127 | Entry(flush_tlb64) | |
| 128 | ||
| 129 | FRAME | |
| 130 | ||
| 131 | ENTER_64BIT_MODE() | |
| 132 | ||
| 133 | mov %cr3, %rax | |
| 134 | mov %rax, %cr3 | |
| 135 | ||
| 136 | ENTER_COMPAT_MODE() | |
| 137 | ||
| 138 | EMARF | |
| 139 | ret | |
| 140 | ||
| 2d21ac55 A |
141 | Entry(set64_cr3) |
| 142 | ||
| 143 | FRAME | |
| 144 | ||
| 145 | movl B_ARG0, %eax | |
| 146 | movl B_ARG1, %edx | |
| 147 | ||
| 148 | ENTER_64BIT_MODE() | |
| 149 | ||
| 150 | /* %rax = %edx:%eax */ | |
| 151 | shl $32, %rax | |
| 152 | shrd $32, %rdx, %rax | |
| 153 | ||
| 154 | mov %rax, %cr3 | |
| 155 | ||
| 156 | ENTER_COMPAT_MODE() | |
| 157 | ||
| 158 | EMARF | |
| 159 | ret | |
| 160 | ||
| 161 | Entry(get64_cr3) | |
| 162 | ||
| 163 | FRAME | |
| 164 | ||
| 165 | ENTER_64BIT_MODE() | |
| 166 | ||
| 167 | mov %cr3, %rax | |
| 168 | mov %rax, %rdx | |
| 169 | shr $32, %rdx // %edx:%eax = %cr3 | |
| 170 | ||
| 171 | ENTER_COMPAT_MODE() | |
| 172 | ||
| 173 | EMARF | |
| 174 | ret | |
| 175 | ||
| 0c530ab8 | 176 | /* FXSAVE and FXRSTOR operate in a mode dependent fashion, hence these variants. |
| 2d21ac55 | 177 | * Must be called with interrupts disabled. |
| 2d21ac55 | 178 | */ |
| 0c530ab8 A |
179 | |
| 180 | Entry(fxsave64) | |
| 181 | movl S_ARG0,%eax | |
| 182 | ENTER_64BIT_MODE() | |
| 0c530ab8 A |
183 | fxsave 0(%eax) |
| 184 | ENTER_COMPAT_MODE() | |
| 185 | ret | |
| 186 | ||
| 187 | Entry(fxrstor64) | |
| 188 | movl S_ARG0,%eax | |
| 189 | ENTER_64BIT_MODE() | |
| 0c530ab8 A |
190 | fxrstor 0(%rax) |
| 191 | ENTER_COMPAT_MODE() | |
| 192 | ret | |
| b0d623f7 A |
193 | |
| 194 | Entry(cpuid64) | |
| 195 | ENTER_64BIT_MODE() | |
| 196 | cpuid | |
| 197 | ENTER_COMPAT_MODE() | |
| 198 | ret | |
| 199 |