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1c79356b | 1 | /* |
2d21ac55 | 2 | * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved. |
1c79356b | 3 | * |
2d21ac55 | 4 | * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ |
1c79356b | 5 | * |
2d21ac55 A |
6 | * This file contains Original Code and/or Modifications of Original Code |
7 | * as defined in and that are subject to the Apple Public Source License | |
8 | * Version 2.0 (the 'License'). You may not use this file except in | |
9 | * compliance with the License. The rights granted to you under the License | |
10 | * may not be used to create, or enable the creation or redistribution of, | |
11 | * unlawful or unlicensed copies of an Apple operating system, or to | |
12 | * circumvent, violate, or enable the circumvention or violation of, any | |
13 | * terms of an Apple operating system software license agreement. | |
8f6c56a5 | 14 | * |
2d21ac55 A |
15 | * Please obtain a copy of the License at |
16 | * http://www.opensource.apple.com/apsl/ and read it before using this file. | |
17 | * | |
18 | * The Original Code and all software distributed under the License are | |
19 | * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER | |
8f6c56a5 A |
20 | * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, |
21 | * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, | |
2d21ac55 A |
22 | * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. |
23 | * Please see the License for the specific language governing rights and | |
24 | * limitations under the License. | |
8f6c56a5 | 25 | * |
2d21ac55 | 26 | * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ |
1c79356b A |
27 | */ |
28 | /* | |
29 | * @OSF_COPYRIGHT@ | |
30 | */ | |
31 | /* | |
32 | * Mach Operating System | |
33 | * Copyright (c) 1991 Carnegie Mellon University | |
34 | * All Rights Reserved. | |
35 | * | |
36 | * Permission to use, copy, modify and distribute this software and its | |
37 | * documentation is hereby granted, provided that both the copyright | |
38 | * notice and this permission notice appear in all copies of the | |
39 | * software, derivative works or modified versions, and any portions | |
40 | * thereof, and that both notices appear in supporting documentation. | |
41 | * | |
42 | * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" | |
43 | * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR | |
44 | * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. | |
45 | * | |
46 | * Carnegie Mellon requests users of this software to return to | |
47 | * | |
48 | * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU | |
49 | * School of Computer Science | |
50 | * Carnegie Mellon University | |
51 | * Pittsburgh PA 15213-3890 | |
52 | * | |
53 | * any improvements or extensions that they make and grant Carnegie Mellon | |
54 | * the rights to redistribute these changes. | |
55 | */ | |
56 | ||
1c79356b A |
57 | #ifndef _I386_FPU_H_ |
58 | #define _I386_FPU_H_ | |
59 | ||
60 | /* | |
61 | * Macro definitions for routines to manipulate the | |
62 | * floating-point processor. | |
63 | */ | |
0c530ab8 | 64 | #include <kern/thread.h> |
1c79356b A |
65 | #include <kern/kern_types.h> |
66 | #include <mach/i386/kern_return.h> | |
67 | #include <mach/i386/thread_status.h> | |
0c530ab8 | 68 | #include <i386/proc_reg.h> |
b0d623f7 | 69 | #include <i386/thread.h> |
0c530ab8 A |
70 | |
71 | extern int fp_kind; | |
72 | ||
73 | extern void init_fpu(void); | |
74 | extern void fpu_module_init(void); | |
75 | extern void fpu_free( | |
76 | struct x86_fpsave_state * fps); | |
77 | extern kern_return_t fpu_set_fxstate( | |
78 | thread_t thr_act, | |
79 | thread_state_t state); | |
80 | extern kern_return_t fpu_get_fxstate( | |
81 | thread_t thr_act, | |
82 | thread_state_t state); | |
83 | extern void fpu_dup_fxstate( | |
84 | thread_t parent, | |
85 | thread_t child); | |
86 | extern void fpnoextflt(void); | |
87 | extern void fpextovrflt(void); | |
88 | extern void fpexterrflt(void); | |
89 | extern void fpSSEexterrflt(void); | |
90 | extern void fpflush(thread_t); | |
91 | extern void fp_setvalid(boolean_t); | |
b0d623f7 | 92 | #ifdef __i386__ |
0c530ab8 A |
93 | extern void fxsave64(struct x86_fx_save *); |
94 | extern void fxrstor64(struct x86_fx_save *); | |
b0d623f7 | 95 | #endif |
1c79356b A |
96 | |
97 | /* | |
98 | * FPU instructions. | |
99 | */ | |
100 | #define fninit() \ | |
101 | __asm__ volatile("fninit") | |
102 | ||
103 | #define fnstcw(control) \ | |
104 | __asm__("fnstcw %0" : "=m" (*(unsigned short *)(control))) | |
105 | ||
106 | #define fldcw(control) \ | |
107 | __asm__ volatile("fldcw %0" : : "m" (*(unsigned short *) &(control)) ) | |
108 | ||
2d21ac55 A |
109 | static inline unsigned short |
110 | fnstsw(void) | |
1c79356b A |
111 | { |
112 | unsigned short status; | |
113 | __asm__ volatile("fnstsw %0" : "=ma" (status)); | |
114 | return(status); | |
115 | } | |
116 | ||
117 | #define fnclex() \ | |
118 | __asm__ volatile("fnclex") | |
119 | ||
55e303ae | 120 | #define fnsave(state) \ |
1c79356b A |
121 | __asm__ volatile("fnsave %0" : "=m" (*state)) |
122 | ||
123 | #define frstor(state) \ | |
124 | __asm__ volatile("frstor %0" : : "m" (state)) | |
125 | ||
126 | #define fwait() \ | |
127 | __asm__("fwait"); | |
128 | ||
55e303ae A |
129 | #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) |
130 | #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) | |
131 | ||
132 | #define FXSAFE() (fp_kind == FP_FXSR) | |
1c79356b | 133 | |
0c530ab8 A |
134 | |
135 | static inline void clear_fpu(void) | |
136 | { | |
137 | set_ts(); | |
138 | } | |
1c79356b | 139 | |
b0d623f7 | 140 | |
1c79356b A |
141 | /* |
142 | * Save thread`s FPU context. | |
1c79356b | 143 | */ |
1c79356b | 144 | |
0c530ab8 A |
145 | static inline void fpu_save_context(thread_t thread) |
146 | { | |
147 | struct x86_fpsave_state *ifps; | |
148 | ||
149 | assert(ml_get_interrupts_enabled() == FALSE); | |
150 | ifps = (thread)->machine.pcb->ifps; | |
151 | if (ifps != 0 && !ifps->fp_valid) { | |
152 | /* Clear CR0.TS in preparation for the FP context save. In | |
153 | * theory, this shouldn't be necessary since a live FPU should | |
154 | * indicate that TS is clear. However, various routines | |
155 | * (such as sendsig & sigreturn) manipulate TS directly. | |
156 | */ | |
157 | clear_ts(); | |
158 | /* registers are in FPU - save to memory */ | |
159 | ifps->fp_valid = TRUE; | |
2d21ac55 | 160 | |
b0d623f7 | 161 | #if defined(__i386__) |
0c530ab8 A |
162 | if (!thread_is_64bit(thread) || is_saved_state32(thread->machine.pcb->iss)) { |
163 | /* save the compatibility/legacy mode XMM+x87 state */ | |
164 | fxsave(&ifps->fx_save_state); | |
165 | ifps->fp_save_layout = FXSAVE32; | |
166 | } | |
167 | else { | |
168 | /* Execute a brief jump to 64-bit mode to save the 64 | |
169 | * bit state | |
170 | */ | |
171 | fxsave64(&ifps->fx_save_state); | |
172 | ifps->fp_save_layout = FXSAVE64; | |
173 | } | |
b0d623f7 A |
174 | #elif defined(__x86_64__) |
175 | /* for a 64-bit long mode kernel, we can always use plain fxsave */ | |
176 | fxsave(&ifps->fx_save_state); | |
177 | ifps->fp_save_layout = thread_is_64bit(thread) ? FXSAVE64 | |
178 | : FXSAVE32; | |
179 | ||
180 | #endif | |
0c530ab8 A |
181 | } |
182 | set_ts(); | |
183 | } | |
1c79356b A |
184 | |
185 | #endif /* _I386_FPU_H_ */ |