[apple/xnu.git] / osfmk / arm / cpuid.h

/*
 * Copyright (c) 2007-2016 Apple Inc. All rights reserved.
 *
 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
 *
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. The rights granted to you under the License
 * may not be used to create, or enable the creation or redistribution of,
 * unlawful or unlicensed copies of an Apple operating system, or to
 * circumvent, violate, or enable the circumvention or violation of, any
 * terms of an Apple operating system software license agreement.
 *
 * Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this file.
 *
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 *
 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
 */
/*
 * @OSF_COPYRIGHT@
 */

/*
 * ARM CPU identification
 */

#ifndef _MACHINE_CPUID_H_
#define _MACHINE_CPUID_H_

#include <stdint.h>
#include <mach/boolean.h>
#include <machine/machine_cpuid.h>

typedef struct {
	uint32_t arm_rev : 4,  /* 00:03 revision number */
	    arm_part         : 12,/* 04:15 primary part number */
	    arm_arch         : 4,/* 16:19 architecture */
	    arm_variant      : 4,/* 20:23 variant  */
	    arm_implementor  : 8;/* 24:31 implementor (0x41) */
} arm_cpuid_bits_t;

typedef union {
	arm_cpuid_bits_t arm_info; /* ARM9xx,  ARM11xx, and later processors */
	uint32_t         value;
} arm_cpu_info_t;

/* Implementor codes */
#define CPU_VID_ARM      0x41 // ARM Limited
#define CPU_VID_DEC      0x44 // Digital Equipment Corporation
#define CPU_VID_MOTOROLA 0x4D // Motorola - Freescale Semiconductor Inc.
#define CPU_VID_MARVELL  0x56 // Marvell Semiconductor Inc.
#define CPU_VID_INTEL    0x69 // Intel ARM parts.
#define CPU_VID_APPLE    0x61 // Apple Inc.


/* ARM Architecture Codes */

#define CPU_ARCH_ARMv4    0x1 /* ARMv4 */
#define CPU_ARCH_ARMv4T   0x2 /* ARMv4 + Thumb */
#define CPU_ARCH_ARMv5    0x3 /* ARMv5 */
#define CPU_ARCH_ARMv5T   0x4 /* ARMv5 + Thumb */
#define CPU_ARCH_ARMv5TE  0x5 /* ARMv5 + Thumb + Extensions(?) */
#define CPU_ARCH_ARMv5TEJ 0x6 /* ARMv5 + Thumb + Extensions(?) + //Jazelle(?) XXX */
#define CPU_ARCH_ARMv6    0x7 /* ARMv6 */
#define CPU_ARCH_ARMv7    0x8 /* ARMv7 */
#define CPU_ARCH_ARMv7f   0x9 /* ARMv7 for Cortex A9 */
#define CPU_ARCH_ARMv7s   0xa /* ARMv7 for Swift */
#define CPU_ARCH_ARMv7k   0xb /* ARMv7 for Cortex A7 */

#define CPU_ARCH_ARMv8    0xc /* Subtype for CPU_TYPE_ARM64 */

#define CPU_ARCH_ARMv8E   0xd /* ARMv8.3a + Apple Private ISA Subtype for CPU_TYPE_ARM64 */

/* special code indicating we need to look somewhere else for the architecture version */
#define CPU_ARCH_EXTENDED 0xF

/* ARM Part Numbers */
/*
 * XXX: ARM Todo
 * Fill out these part numbers more completely
 */

/* ARM9 (ARMv4T architecture) */
#define CPU_PART_920T               0x920
#define CPU_PART_926EJS             0x926 /* ARM926EJ-S */

/* ARM11  (ARMv6 architecture) */
#define CPU_PART_1136JFS            0xB36 /* ARM1136JF-S or ARM1136J-S */
#define CPU_PART_1176JZFS           0xB76 /* ARM1176JZF-S */

/* G1 (ARMv7 architecture) */
#define CPU_PART_CORTEXA5           0xC05

/* M7 (ARMv7 architecture) */
#define CPU_PART_CORTEXA7           0xC07

/* H2 H3 (ARMv7 architecture) */
#define CPU_PART_CORTEXA8           0xC08

/* H4 (ARMv7 architecture) */
#define CPU_PART_CORTEXA9           0xC09

/* H7 (ARMv8 architecture) */
#define CPU_PART_TYPHOON            0x2

/* H7G (ARMv8 architecture) */
#define CPU_PART_TYPHOON_CAPRI      0x3

/* H8 (ARMv8 architecture) */
#define CPU_PART_TWISTER            0x4

/* H8G H8M (ARMv8 architecture) */
#define CPU_PART_TWISTER_ELBA_MALTA 0x5

/* H9 (ARMv8 architecture) */
#define CPU_PART_HURRICANE          0x6

/* H9G (ARMv8 architecture) */
#define CPU_PART_HURRICANE_MYST     0x7

/* H10 p-Core (ARMv8 architecture) */
#define CPU_PART_MONSOON            0x8

/* H10 e-Core (ARMv8 architecture) */
#define CPU_PART_MISTRAL            0x9

/* H11 p-Core (ARMv8 architecture) */
#define CPU_PART_VORTEX             0xB

/* H11 e-Core (ARMv8 architecture) */
#define CPU_PART_TEMPEST            0xC

/* M9 e-Core (ARMv8 architecture) */
#define CPU_PART_TEMPEST_M9         0xF

/* H11G p-Core (ARMv8 architecture) */
#define CPU_PART_VORTEX_ARUBA       0x10

/* H11G e-Core (ARMv8 architecture) */
#define CPU_PART_TEMPEST_ARUBA      0x11

/* H12 p-Core (ARMv8 architecture) */
#define CPU_PART_LIGHTNING          0x12

/* H12 e-Core (ARMv8 architecture) */
#define CPU_PART_THUNDER            0x13

#ifndef RC_HIDE_XNU_FIRESTORM
/*
 * Whilst this is a Thunder-based SoC, it
 * hasn't been released and should remain
 * hidden in 2020 seeds.
 */
/* M10 e-Core (ARMv8 architecture) */
#define CPU_PART_THUNDER_M10        0x26
#endif

#ifndef RC_HIDE_XNU_FIRESTORM

/* H13 e-Core */
#define CPU_PART_ICESTORM           0x20

/* H13 p-Core */
#define CPU_PART_FIRESTORM          0x21

/* H13G e-Core */
#define CPU_PART_ICESTORM_TONGA     0x22

/* H13G p-Core */
#define CPU_PART_FIRESTORM_TONGA    0x23

#endif /* !RC_HIDE_XNU_FIRESTORM */


/* Cache type identification */

/* Supported Cache Types */
typedef enum {
	CACHE_WRITE_THROUGH,
	CACHE_WRITE_BACK,
	CACHE_READ_ALLOCATION,
	CACHE_WRITE_ALLOCATION,
	CACHE_UNKNOWN
} cache_type_t;

typedef struct {
	boolean_t    c_unified;          /* unified I & D cache? */
	uint32_t     c_isize;            /* in Bytes (ARM caches can be 0.5 KB) */
	boolean_t    c_i_ppage;          /* protected page restriction for I cache
	                                  * (see B6-11 in ARM DDI 0100I document). */
	uint32_t     c_dsize;            /* in Bytes (ARM caches can be 0.5 KB) */
	boolean_t    c_d_ppage;          /* protected page restriction for I cache
	                                  * (see B6-11 in ARM DDI 0100I document). */
	cache_type_t c_type;             /* WB or WT */
	uint32_t     c_linesz;           /* number of bytes */
	uint32_t     c_assoc;            /* n-way associativity */
	uint32_t     c_l2size;           /* L2 size, if present */
	uint32_t     c_bulksize_op;      /* bulk operation size limit. 0 if disabled */
	uint32_t     c_inner_cache_size; /* inner dache size */
} cache_info_t;

typedef struct {
	uint32_t
	    RB:4, /* 3:0 - 32x64-bit media register bank supported: 0x2 */
	    SP:4, /* 7:4 - Single precision supported in VFPv3: 0x2 */
	    DP:4, /* 8:11 - Double precision supported in VFPv3: 0x2 */
	    TE:4, /* 12-15 - Only untrapped exception handling can be selected: 0x0 */
	    D:4, /* 19:16 - VFP hardware divide supported: 0x1 */
	    SR:4, /* 23:20 - VFP hardware square root supported: 0x1 */
	    SV:4, /* 27:24 - VFP short vector supported: 0x1 */
	    RM:4; /* 31:28 - All VFP rounding modes supported: 0x1 */
} arm_mvfr0_t;

typedef union {
	arm_mvfr0_t bits;
	uint32_t    value;
} arm_mvfr0_info_t;

typedef struct {
	uint32_t
	    FZ:4, /* 3:0 - Full denormal arithmetic supported for VFP: 0x1 */
	    DN:4, /* 7:4 - Propagation of NaN values supported for VFP: 0x1 */
	    LS:4, /* 11:8 - Load/store instructions supported for NEON: 0x1 */
	    I:4, /* 15:12 - Integer instructions supported for NEON: 0x1 */
	    SP:4, /* 19:16 - Single precision floating-point instructions supported for NEON: 0x1 */
	    HPFP:4, /* 23:20 - Half precision floating-point instructions supported */
	    RSVP:8; /* 31:24 - Reserved */
} arm_mvfr1_t;

typedef union {
	arm_mvfr1_t bits;
	uint32_t    value;
} arm_mvfr1_info_t;

typedef struct {
	uint32_t neon;
	uint32_t neon_hpfp;
	uint32_t neon_fp16;
} arm_mvfp_info_t;

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */

extern void do_cpuid(void);
extern arm_cpu_info_t *cpuid_info(void);
extern int cpuid_get_cpufamily(void);
extern int cpuid_get_cpusubfamily(void);

extern void do_debugid(void);
extern arm_debug_info_t *arm_debug_info(void);

extern void do_cacheid(void);
extern cache_info_t *cache_info(void);

extern void do_mvfpid(void);
extern arm_mvfp_info_t *arm_mvfp_info(void);

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif // _MACHINE_CPUID_H_
Commit	Line	Data
5ba3f43e A	1	/*
	2	* Copyright (c) 2007-2016 Apple Inc. All rights reserved.
	3	*
	4	* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
	5	*
	6	* This file contains Original Code and/or Modifications of Original Code
	7	* as defined in and that are subject to the Apple Public Source License
	8	* Version 2.0 (the 'License'). You may not use this file except in
	9	* compliance with the License. The rights granted to you under the License
	10	* may not be used to create, or enable the creation or redistribution of,
	11	* unlawful or unlicensed copies of an Apple operating system, or to
	12	* circumvent, violate, or enable the circumvention or violation of, any
	13	* terms of an Apple operating system software license agreement.
	14	*
	15	* Please obtain a copy of the License at
	16	* http://www.opensource.apple.com/apsl/ and read it before using this file.
	17	*
	18	* The Original Code and all software distributed under the License are
	19	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
	20	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
	21	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
	22	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	23	* Please see the License for the specific language governing rights and
	24	* limitations under the License.
	25	*
	26	* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
	27	*/
	28	/*
	29	* @OSF_COPYRIGHT@
	30	*/
	31
	32	/*
	33	* ARM CPU identification
	34	*/
	35
	36	#ifndef _MACHINE_CPUID_H_
	37	#define _MACHINE_CPUID_H_
	38
	39	#include <stdint.h>
	40	#include <mach/boolean.h>
	41	#include <machine/machine_cpuid.h>
	42
	43	typedef struct {
cb323159 A	44	uint32_t arm_rev : 4, /* 00:03 revision number */
	45	arm_part : 12,/* 04:15 primary part number */
	46	arm_arch : 4,/* 16:19 architecture */
	47	arm_variant : 4,/* 20:23 variant */
	48	arm_implementor : 8;/* 24:31 implementor (0x41) */
5ba3f43e A	49	} arm_cpuid_bits_t;
	50
	51	typedef union {
cb323159 A	52	arm_cpuid_bits_t arm_info; /* ARM9xx, ARM11xx, and later processors */
cb323159 A	53	uint32_t value;
5ba3f43e A	54	} arm_cpu_info_t;
	55
	56	/* Implementor codes */
cb323159 A	57	#define CPU_VID_ARM 0x41 // ARM Limited
	58	#define CPU_VID_DEC 0x44 // Digital Equipment Corporation
	59	#define CPU_VID_MOTOROLA 0x4D // Motorola - Freescale Semiconductor Inc.
	60	#define CPU_VID_MARVELL 0x56 // Marvell Semiconductor Inc.
	61	#define CPU_VID_INTEL 0x69 // Intel ARM parts.
	62	#define CPU_VID_APPLE 0x61 // Apple Inc.
5ba3f43e A	63
	64
	65	/* ARM Architecture Codes */
	66
cb323159 A	67	#define CPU_ARCH_ARMv4 0x1 /* ARMv4 */
	68	#define CPU_ARCH_ARMv4T 0x2 /* ARMv4 + Thumb */
	69	#define CPU_ARCH_ARMv5 0x3 /* ARMv5 */
	70	#define CPU_ARCH_ARMv5T 0x4 /* ARMv5 + Thumb */
	71	#define CPU_ARCH_ARMv5TE 0x5 /* ARMv5 + Thumb + Extensions(?) */
	72	#define CPU_ARCH_ARMv5TEJ 0x6 /* ARMv5 + Thumb + Extensions(?) + //Jazelle(?) XXX */
	73	#define CPU_ARCH_ARMv6 0x7 /* ARMv6 */
	74	#define CPU_ARCH_ARMv7 0x8 /* ARMv7 */
	75	#define CPU_ARCH_ARMv7f 0x9 /* ARMv7 for Cortex A9 */
	76	#define CPU_ARCH_ARMv7s 0xa /* ARMv7 for Swift */
	77	#define CPU_ARCH_ARMv7k 0xb /* ARMv7 for Cortex A7 */
5ba3f43e	78
cb323159	79	#define CPU_ARCH_ARMv8 0xc /* Subtype for CPU_TYPE_ARM64 */
5ba3f43e	80
cb323159	81	#define CPU_ARCH_ARMv8E 0xd /* ARMv8.3a + Apple Private ISA Subtype for CPU_TYPE_ARM64 */
5ba3f43e A	82
5ba3f43e A	83	/* special code indicating we need to look somewhere else for the architecture version */
cb323159	84	#define CPU_ARCH_EXTENDED 0xF
5ba3f43e A	85
	86	/* ARM Part Numbers */
	87	/*
	88	* XXX: ARM Todo
	89	* Fill out these part numbers more completely
	90	*/
	91
	92	/* ARM9 (ARMv4T architecture) */
cb323159 A	93	#define CPU_PART_920T 0x920
cb323159 A	94	#define CPU_PART_926EJS 0x926 /* ARM926EJ-S */
5ba3f43e A	95
5ba3f43e A	96	/* ARM11 (ARMv6 architecture) */
cb323159 A	97	#define CPU_PART_1136JFS 0xB36 /* ARM1136JF-S or ARM1136J-S */
cb323159 A	98	#define CPU_PART_1176JZFS 0xB76 /* ARM1176JZF-S */
5ba3f43e A	99
5ba3f43e A	100	/* G1 (ARMv7 architecture) */
cb323159	101	#define CPU_PART_CORTEXA5 0xC05
5ba3f43e A	102
5ba3f43e A	103	/* M7 (ARMv7 architecture) */
cb323159	104	#define CPU_PART_CORTEXA7 0xC07
5ba3f43e A	105
5ba3f43e A	106	/* H2 H3 (ARMv7 architecture) */
cb323159	107	#define CPU_PART_CORTEXA8 0xC08
5ba3f43e A	108
5ba3f43e A	109	/* H4 (ARMv7 architecture) */
cb323159	110	#define CPU_PART_CORTEXA9 0xC09
5ba3f43e	111
5ba3f43e	112	/* H7 (ARMv8 architecture) */
cb323159	113	#define CPU_PART_TYPHOON 0x2
5ba3f43e A	114
5ba3f43e A	115	/* H7G (ARMv8 architecture) */
cb323159	116	#define CPU_PART_TYPHOON_CAPRI 0x3
5ba3f43e A	117
5ba3f43e A	118	/* H8 (ARMv8 architecture) */
cb323159	119	#define CPU_PART_TWISTER 0x4
5ba3f43e A	120
5ba3f43e A	121	/* H8G H8M (ARMv8 architecture) */
cb323159	122	#define CPU_PART_TWISTER_ELBA_MALTA 0x5
5ba3f43e A	123
5ba3f43e A	124	/* H9 (ARMv8 architecture) */
cb323159	125	#define CPU_PART_HURRICANE 0x6
5ba3f43e A	126
5ba3f43e A	127	/* H9G (ARMv8 architecture) */
cb323159	128	#define CPU_PART_HURRICANE_MYST 0x7
5ba3f43e	129
d9a64523	130	/* H10 p-Core (ARMv8 architecture) */
cb323159	131	#define CPU_PART_MONSOON 0x8
d9a64523 A	132
d9a64523 A	133	/* H10 e-Core (ARMv8 architecture) */
cb323159 A	134	#define CPU_PART_MISTRAL 0x9
	135
	136	/* H11 p-Core (ARMv8 architecture) */
	137	#define CPU_PART_VORTEX 0xB
	138
	139	/* H11 e-Core (ARMv8 architecture) */
	140	#define CPU_PART_TEMPEST 0xC
	141
	142	/* M9 e-Core (ARMv8 architecture) */
	143	#define CPU_PART_TEMPEST_M9 0xF
	144
	145	/* H11G p-Core (ARMv8 architecture) */
	146	#define CPU_PART_VORTEX_ARUBA 0x10
	147
	148	/* H11G e-Core (ARMv8 architecture) */
	149	#define CPU_PART_TEMPEST_ARUBA 0x11
d9a64523	150
c6bf4f31 A	151	/* H12 p-Core (ARMv8 architecture) */
	152	#define CPU_PART_LIGHTNING 0x12
	153
	154	/* H12 e-Core (ARMv8 architecture) */
	155	#define CPU_PART_THUNDER 0x13
	156
2a1bd2d3 A	157	#ifndef RC_HIDE_XNU_FIRESTORM
	158	/*
	159	* Whilst this is a Thunder-based SoC, it
	160	* hasn't been released and should remain
	161	* hidden in 2020 seeds.
	162	*/
	163	/* M10 e-Core (ARMv8 architecture) */
	164	#define CPU_PART_THUNDER_M10 0x26
	165	#endif
	166
	167	#ifndef RC_HIDE_XNU_FIRESTORM
	168
	169	/* H13 e-Core */
	170	#define CPU_PART_ICESTORM 0x20
	171
	172	/* H13 p-Core */
	173	#define CPU_PART_FIRESTORM 0x21
	174
	175	/* H13G e-Core */
	176	#define CPU_PART_ICESTORM_TONGA 0x22
	177
	178	/* H13G p-Core */
	179	#define CPU_PART_FIRESTORM_TONGA 0x23
f427ee49	180
2a1bd2d3	181	#endif /* !RC_HIDE_XNU_FIRESTORM */
f427ee49 A	182
f427ee49 A	183
5ba3f43e A	184
	185	/* Cache type identification */
	186
	187	/* Supported Cache Types */
	188	typedef enum {
	189	CACHE_WRITE_THROUGH,
	190	CACHE_WRITE_BACK,
	191	CACHE_READ_ALLOCATION,
	192	CACHE_WRITE_ALLOCATION,
	193	CACHE_UNKNOWN
	194	} cache_type_t;
	195
	196	typedef struct {
cb323159 A	197	boolean_t c_unified; /* unified I & D cache? */
	198	uint32_t c_isize; /* in Bytes (ARM caches can be 0.5 KB) */
	199	boolean_t c_i_ppage; /* protected page restriction for I cache
	200	* (see B6-11 in ARM DDI 0100I document). */
	201	uint32_t c_dsize; /* in Bytes (ARM caches can be 0.5 KB) */
	202	boolean_t c_d_ppage; /* protected page restriction for I cache
	203	* (see B6-11 in ARM DDI 0100I document). */
	204	cache_type_t c_type; /* WB or WT */
	205	uint32_t c_linesz; /* number of bytes */
	206	uint32_t c_assoc; /* n-way associativity */
	207	uint32_t c_l2size; /* L2 size, if present */
	208	uint32_t c_bulksize_op; /* bulk operation size limit. 0 if disabled */
	209	uint32_t c_inner_cache_size; /* inner dache size */
5ba3f43e A	210	} cache_info_t;
	211
	212	typedef struct {
	213	uint32_t
0a7de745 A	214	RB:4, /* 3:0 - 32x64-bit media register bank supported: 0x2 */
	215	SP:4, /* 7:4 - Single precision supported in VFPv3: 0x2 */
	216	DP:4, /* 8:11 - Double precision supported in VFPv3: 0x2 */
	217	TE:4, /* 12-15 - Only untrapped exception handling can be selected: 0x0 */
	218	D:4, /* 19:16 - VFP hardware divide supported: 0x1 */
	219	SR:4, /* 23:20 - VFP hardware square root supported: 0x1 */
	220	SV:4, /* 27:24 - VFP short vector supported: 0x1 */
	221	RM:4; /* 31:28 - All VFP rounding modes supported: 0x1 */
5ba3f43e A	222	} arm_mvfr0_t;
	223
	224	typedef union {
	225	arm_mvfr0_t bits;
	226	uint32_t value;
	227	} arm_mvfr0_info_t;
	228
	229	typedef struct {
	230	uint32_t
0a7de745 A	231	FZ:4, /* 3:0 - Full denormal arithmetic supported for VFP: 0x1 */
	232	DN:4, /* 7:4 - Propagation of NaN values supported for VFP: 0x1 */
	233	LS:4, /* 11:8 - Load/store instructions supported for NEON: 0x1 */
	234	I:4, /* 15:12 - Integer instructions supported for NEON: 0x1 */
	235	SP:4, /* 19:16 - Single precision floating-point instructions supported for NEON: 0x1 */
	236	HPFP:4, /* 23:20 - Half precision floating-point instructions supported */
	237	RSVP:8; /* 31:24 - Reserved */
5ba3f43e A	238	} arm_mvfr1_t;
	239
	240	typedef union {
	241	arm_mvfr1_t bits;
	242	uint32_t value;
	243	} arm_mvfr1_info_t;
	244
	245	typedef struct {
cb323159 A	246	uint32_t neon;
	247	uint32_t neon_hpfp;
	248	uint32_t neon_fp16;
5ba3f43e A	249	} arm_mvfp_info_t;
	250
	251	#ifdef __cplusplus
	252	extern "C" {
cb323159	253	#endif /* __cplusplus */
5ba3f43e A	254
	255	extern void do_cpuid(void);
	256	extern arm_cpu_info_t *cpuid_info(void);
	257	extern int cpuid_get_cpufamily(void);
f427ee49	258	extern int cpuid_get_cpusubfamily(void);
5ba3f43e A	259
	260	extern void do_debugid(void);
	261	extern arm_debug_info_t *arm_debug_info(void);
	262
	263	extern void do_cacheid(void);
	264	extern cache_info_t *cache_info(void);
	265
	266	extern void do_mvfpid(void);
	267	extern arm_mvfp_info_t *arm_mvfp_info(void);
	268
	269	#ifdef __cplusplus
	270	}
cb323159	271	#endif /* __cplusplus */
5ba3f43e A	272
5ba3f43e A	273	#endif // _MACHINE_CPUID_H_