[apple/xnu.git] / osfmk / arm / cpu_x86_64_capabilities.h

/*
 * Copyright (c) 2017 Apple Inc. All rights reserved.
 */

#ifdef  PRIVATE

#ifndef _ARM_CPU_X86_64_CAPABILITIES_H
#define _ARM_CPU_X86_64_CAPABILITIES_H

#ifndef __ASSEMBLER__
#include <stdint.h>
#include <sys/commpage.h>
#ifdef KERNEL_PRIVATE
#include <mach/vm_types.h>
#endif
#endif

/*
 * This is the authoritative way to determine from x86_64 user mode what
 * implementation-specific processor features are available.
 *
 * This API only supported for Apple internal use.
 */

/* Bit definitions for emulated _cpu_capabilities: */

#define x86_64_kHasMMX                  0x00000001
#define x86_64_kHasSSE                  0x00000002
#define x86_64_kHasSSE2                 0x00000004
#define x86_64_kHasSSE3                 0x00000008
#define x86_64_kCache32                 0x00000010      /* cache line size is 32 bytes */
#define x86_64_kCache64                 0x00000020
#define x86_64_kCache128                0x00000040
#define x86_64_kFastThreadLocalStorage  0x00000080      /* TLS ptr is kept in a user-mode-readable register */
#define x86_64_kHasSupplementalSSE3             0x00000100
#define x86_64_k64Bit                   0x00000200      /* processor supports EM64T (not what mode you're running in) */
#define x86_64_kHasSSE4_1               0x00000400
#define x86_64_kHasSSE4_2               0x00000800
#define x86_64_kHasAES                  0x00001000
#define x86_64_kInOrderPipeline 0x00002000
#define x86_64_kSlow                    0x00004000      /* tsc < nanosecond */
#define x86_64_kUP                              0x00008000      /* set if (kNumCPUs == 1) */
#define x86_64_kNumCPUs                 0x00FF0000      /* number of CPUs (see _NumCPUs() below) */
#define x86_64_kNumCPUsShift    16
#define x86_64_kHasAVX1_0               0x01000000
#define x86_64_kHasRDRAND               0x02000000
#define x86_64_kHasF16C                 0x04000000
#define x86_64_kHasENFSTRG              0x08000000
#define x86_64_kHasFMA                  0x10000000
#define x86_64_kHasAVX2_0               0x20000000
#define x86_64_kHasBMI1                 0x40000000
#define x86_64_kHasBMI2                 0x80000000
/* Extending into 64-bits from here: */
#define x86_64_kHasRTM                  0x0000000100000000ULL
#define x86_64_kHasHLE                  0x0000000200000000ULL
#define x86_64_kHasRDSEED               0x0000000800000000ULL
#define x86_64_kHasADX                  0x0000000400000000ULL
#define x86_64_kHasMPX                  0x0000001000000000ULL
#define x86_64_kHasSGX                  0x0000002000000000ULL
#if !defined(RC_HIDE_XNU_J137)
#define x86_64_kHasAVX512F              0x0000004000000000ULL
#define x86_64_kHasAVX512CD             0x0000008000000000ULL
#define x86_64_kHasAVX512DQ             0x0000010000000000ULL
#define x86_64_kHasAVX512BW             0x0000020000000000ULL
#define x86_64_kHasAVX512IFMA   0x0000040000000000ULL
#define x86_64_kHasAVX512VBMI   0x0000080000000000ULL
#define x86_64_kHasAVX512VL             0x0000100000000000ULL
#endif /* not RC_HIDE_XNU_J137 */

#define x86_64_kIsTranslated    0x4000000000000000ULL   // isTranslated
/* Cambria specific. The address space page shift. */
#define x86_64_kVmPageShift     0xFFB

/*
 * The effectively cast-in-stone x86_64 comm page address that we
 * simulate for compatibility purposes.
 */

#define X86_64_COMM_PAGE_BASE_ADDRESS           (0x7fffffe00000ULL)
#define X86_64_COMM_PAGE_AREA_LENGTH            4096
#define X86_64_COMM_PAGE_VERSION                        14
#define X86_64_MP_SPIN_TRIES                    1000

#ifdef KERNEL_PRIVATE
extern vm_address_t x86_64_sharedpage_rw_addr;
extern uint64_t _get_x86_64_cpu_capabilities(void);
#endif

typedef struct {
/*  0 */ uint8_t signature[16];
/* 10 */ uint64_t cpu_capabilities64;
/* 18 */ uint8_t _unused[6];
/* 1e */ uint16_t version;
/* 20 */ uint32_t cpu_capabilities;
/* 24 */ uint8_t _unused0[2];
/* 26 */ uint16_t cache_linesize;
/* 28 */ volatile uint32_t sched_gen;
/* 2c */ volatile uint32_t memory_pressure;
/* 30 */ volatile uint32_t spin_count;
/* 34 */ volatile uint8_t active_cpus;
/* 35 */ uint8_t physical_cpus;
/* 36 */ uint8_t logical_cpus;
/* 37 */ uint8_t _unused1[1];
/* 38 */ uint64_t memory_size;
/* 40 */ uint32_t cpufamily;
/* 44 */ volatile uint32_t kdebug_enable;
/* 48 */ volatile uint32_t atm_diagnostic_config;
/* 4C */ uint8_t cp_dtrace_dof_enabled;
/* 4D */ uint8_t cp_kernel_page_shift; /* _COMM_PAGE_VERSION >= 14 */
/* 4E */ uint8_t cp_user_page_shift; /* _COMM_PAGE_VERSION >= 14 */
/* 4F */ uint8_t _unused2;
	volatile struct {
/* 50 */ uint64_t nt_tsc_base;
/* 58 */ uint32_t nt_scale;
/* 5c */ uint32_t nt_shift;
/* 60 */ uint64_t nt_ns_base;
/* 68 */ uint32_t nt_generation;
/* 6c */ uint32_t gtod_generation;
/* 70 */ uint64_t gtod_ns_base;
/* 78 */ uint64_t gtod_sec_base;
	} time_data;
	volatile union {
		struct {
/* 80 */ uint64_t time;
/* 88 */ uint64_t time_supported;
		} _;
		uint8_t _fill[64];
	} approx;
/* c0 */ volatile uint64_t cont_timebase;
/* c8 */ volatile uint64_t boottime_usec;
	new_commpage_timeofday_data_t new_time_data;
/*			{								*/
/* d0			uint64_t TimeStamp_tick;	*/
/* d8			uint64_t TimeStamp_sec;		*/
/* e0			uint64_t TimeStamp_frac;	*/
/* e8			uint64_t Ticks_scale;		*/
/* f0			uint64_t Ticks_per_sec;		*/
/*			}								*/

/* f8 */ uint64_t unused;
/* 100 */ uint64_t dyld_system_flags;

/* 108 */ uint8_t unused2[3800];
/* 0xFE0 */ uint8_t cp_aprr_shadow_supported;
/* 0xFE1 */ uint8_t unused3[7];
/* 0xFE8 */ uint64_t cp_aprr_shadow_jit_rw;
/* 0xFF0*/ uint64_t cp_aprr_shadow_jit_rx;
/* 0xFF8 */ uint32_t unused4;
/* ffc */ uint32_t arm_cpufamily;
} x86_64_commpage_t;

#endif /* _ARM_CPU_X86_64_CAPABILITIES_H */
#endif /* PRIVATE */
Commit	Line	Data
f427ee49 A	1	/*
	2	* Copyright (c) 2017 Apple Inc. All rights reserved.
	3	*/
	4
	5	#ifdef PRIVATE
	6
	7	#ifndef _ARM_CPU_X86_64_CAPABILITIES_H
	8	#define _ARM_CPU_X86_64_CAPABILITIES_H
	9
	10	#ifndef __ASSEMBLER__
	11	#include <stdint.h>
	12	#include <sys/commpage.h>
	13	#ifdef KERNEL_PRIVATE
	14	#include <mach/vm_types.h>
	15	#endif
	16	#endif
	17
	18	/*
	19	* This is the authoritative way to determine from x86_64 user mode what
	20	* implementation-specific processor features are available.
	21	*
	22	* This API only supported for Apple internal use.
	23	*/
	24
	25	/* Bit definitions for emulated _cpu_capabilities: */
	26
	27	#define x86_64_kHasMMX 0x00000001
	28	#define x86_64_kHasSSE 0x00000002
	29	#define x86_64_kHasSSE2 0x00000004
	30	#define x86_64_kHasSSE3 0x00000008
	31	#define x86_64_kCache32 0x00000010 /* cache line size is 32 bytes */
	32	#define x86_64_kCache64 0x00000020
	33	#define x86_64_kCache128 0x00000040
	34	#define x86_64_kFastThreadLocalStorage 0x00000080 /* TLS ptr is kept in a user-mode-readable register */
	35	#define x86_64_kHasSupplementalSSE3 0x00000100
	36	#define x86_64_k64Bit 0x00000200 /* processor supports EM64T (not what mode you're running in) */
	37	#define x86_64_kHasSSE4_1 0x00000400
	38	#define x86_64_kHasSSE4_2 0x00000800
	39	#define x86_64_kHasAES 0x00001000
	40	#define x86_64_kInOrderPipeline 0x00002000
	41	#define x86_64_kSlow 0x00004000 /* tsc < nanosecond */
	42	#define x86_64_kUP 0x00008000 /* set if (kNumCPUs == 1) */
	43	#define x86_64_kNumCPUs 0x00FF0000 /* number of CPUs (see _NumCPUs() below) */
	44	#define x86_64_kNumCPUsShift 16
	45	#define x86_64_kHasAVX1_0 0x01000000
	46	#define x86_64_kHasRDRAND 0x02000000
	47	#define x86_64_kHasF16C 0x04000000
	48	#define x86_64_kHasENFSTRG 0x08000000
	49	#define x86_64_kHasFMA 0x10000000
	50	#define x86_64_kHasAVX2_0 0x20000000
	51	#define x86_64_kHasBMI1 0x40000000
	52	#define x86_64_kHasBMI2 0x80000000
	53	/* Extending into 64-bits from here: */
	54	#define x86_64_kHasRTM 0x0000000100000000ULL
	55	#define x86_64_kHasHLE 0x0000000200000000ULL
	56	#define x86_64_kHasRDSEED 0x0000000800000000ULL
	57	#define x86_64_kHasADX 0x0000000400000000ULL
	58	#define x86_64_kHasMPX 0x0000001000000000ULL
	59	#define x86_64_kHasSGX 0x0000002000000000ULL
	60	#if !defined(RC_HIDE_XNU_J137)
	61	#define x86_64_kHasAVX512F 0x0000004000000000ULL
	62	#define x86_64_kHasAVX512CD 0x0000008000000000ULL
	63	#define x86_64_kHasAVX512DQ 0x0000010000000000ULL
	64	#define x86_64_kHasAVX512BW 0x0000020000000000ULL
65	#define x86_64_kHasAVX512IFMA 0x0000040000000000ULL
66	#define x86_64_kHasAVX512VBMI 0x0000080000000000ULL
67	#define x86_64_kHasAVX512VL 0x0000100000000000ULL
68	#endif /* not RC_HIDE_XNU_J137 */
69
70	#define x86_64_kIsTranslated 0x4000000000000000ULL // isTranslated
71	/* Cambria specific. The address space page shift. */
72	#define x86_64_kVmPageShift 0xFFB
73
74	/*
75	* The effectively cast-in-stone x86_64 comm page address that we
76	* simulate for compatibility purposes.
77	*/
78
79	#define X86_64_COMM_PAGE_BASE_ADDRESS (0x7fffffe00000ULL)
80	#define X86_64_COMM_PAGE_AREA_LENGTH 4096
81	#define X86_64_COMM_PAGE_VERSION 14
82	#define X86_64_MP_SPIN_TRIES 1000
83
84	#ifdef KERNEL_PRIVATE
85	extern vm_address_t x86_64_sharedpage_rw_addr;
86	extern uint64_t _get_x86_64_cpu_capabilities(void);
87	#endif
88
89	typedef struct {
90	/* 0 */ uint8_t signature[16];
91	/* 10 */ uint64_t cpu_capabilities64;
92	/* 18 */ uint8_t _unused[6];
93	/* 1e */ uint16_t version;
94	/* 20 */ uint32_t cpu_capabilities;
95	/* 24 */ uint8_t _unused0[2];
96	/* 26 */ uint16_t cache_linesize;
97	/* 28 */ volatile uint32_t sched_gen;
98	/* 2c */ volatile uint32_t memory_pressure;
99	/* 30 */ volatile uint32_t spin_count;
100	/* 34 */ volatile uint8_t active_cpus;
101	/* 35 */ uint8_t physical_cpus;
102	/* 36 */ uint8_t logical_cpus;
103	/* 37 */ uint8_t _unused1[1];
104	/* 38 */ uint64_t memory_size;
105	/* 40 */ uint32_t cpufamily;
106	/* 44 */ volatile uint32_t kdebug_enable;
107	/* 48 */ volatile uint32_t atm_diagnostic_config;
108	/* 4C */ uint8_t cp_dtrace_dof_enabled;
109	/* 4D / uint8_t cp_kernel_page_shift; / _COMM_PAGE_VERSION >= 14 */
110	/* 4E / uint8_t cp_user_page_shift; / _COMM_PAGE_VERSION >= 14 */
111	/* 4F */ uint8_t _unused2;
112	volatile struct {
113	/* 50 */ uint64_t nt_tsc_base;
114	/* 58 */ uint32_t nt_scale;
115	/* 5c */ uint32_t nt_shift;
116	/* 60 */ uint64_t nt_ns_base;
117	/* 68 */ uint32_t nt_generation;
118	/* 6c */ uint32_t gtod_generation;
119	/* 70 */ uint64_t gtod_ns_base;
120	/* 78 */ uint64_t gtod_sec_base;
121	} time_data;
122	volatile union {
123	struct {
124	/* 80 */ uint64_t time;
125	/* 88 */ uint64_t time_supported;
126	} _;
127	uint8_t _fill[64];
128	} approx;
129	/* c0 */ volatile uint64_t cont_timebase;
130	/* c8 */ volatile uint64_t boottime_usec;
131	new_commpage_timeofday_data_t new_time_data;
132	/* { */
133	/* d0 uint64_t TimeStamp_tick; */
134	/* d8 uint64_t TimeStamp_sec; */
135	/* e0 uint64_t TimeStamp_frac; */
136	/* e8 uint64_t Ticks_scale; */
137	/* f0 uint64_t Ticks_per_sec; */
138	/* } */
139
140	/* f8 */ uint64_t unused;
141	/* 100 */ uint64_t dyld_system_flags;
142
143	/* 108 */ uint8_t unused2[3800];
144	/* 0xFE0 */ uint8_t cp_aprr_shadow_supported;
145	/* 0xFE1 */ uint8_t unused3[7];
146	/* 0xFE8 */ uint64_t cp_aprr_shadow_jit_rw;
147	/* 0xFF0*/ uint64_t cp_aprr_shadow_jit_rx;
148	/* 0xFF8 */ uint32_t unused4;
149	/* ffc */ uint32_t arm_cpufamily;
150	} x86_64_commpage_t;
151
152	#endif /* _ARM_CPU_X86_64_CAPABILITIES_H */
153	#endif /* PRIVATE */