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1/*
2 * Copyright (c) 2015 Apple Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
0a7de745 5 *
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6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. Please obtain a copy of the License at
10 * http://www.opensource.apple.com/apsl/ and read it before using this
11 * file.
0a7de745 12 *
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13 * The Original Code and all software distributed under the License are
14 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
15 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
16 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
18 * Please see the License for the specific language governing rights and
19 * limitations under the License.
0a7de745 20 *
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21 * @APPLE_LICENSE_HEADER_END@
22 */
23#include <stddef.h>
24#include <stdbool.h>
25#include <sys/types.h>
26#include <machine/cpu_capabilities.h>
27#include <mach/mach_time.h>
28
29__attribute__((visibility("hidden")))
30uint64_t
31_mach_continuous_time_base(void)
32{
33#if !defined(__x86_64__) && !defined(__arm64__)
34 // Deal with the lack of 64-bit loads on arm32 (see mach_approximate_time.s)
0a7de745 35 while (1) {
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36 volatile uint64_t *base_ptr = (volatile uint64_t*)_COMM_PAGE_CONT_TIMEBASE;
37 uint64_t read1, read2;
38 read1 = *base_ptr;
5ba3f43e 39#if defined(__arm__)
0a7de745 40 __asm__ volatile ("dsb sy" ::: "memory");
5ba3f43e 41#elif defined(__i386__)
0a7de745 42 __asm__ volatile ("lfence" ::: "memory");
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43#else
44#error "unsupported arch"
45#endif
46 read2 = *base_ptr;
47
0a7de745 48 if (__builtin_expect((read1 == read2), 1)) {
39037602 49 return read1;
0a7de745 50 }
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51 }
52#else // 64-bit
53 return *(volatile uint64_t*)_COMM_PAGE_CONT_TIMEBASE;
54#endif // 64-bit
55}
56
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57__attribute__((visibility("hidden")))
58kern_return_t
59_mach_continuous_hwclock(uint64_t *cont_time __unused)
60{
61#if defined(__arm64__)
cb323159 62#define ISB_SY 0xf
5ba3f43e 63 uint8_t cont_hwclock = *((uint8_t*)_COMM_PAGE_CONT_HWCLOCK);
5ba3f43e 64 if (cont_hwclock) {
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65 __builtin_arm_isb(ISB_SY);
66 *cont_time = __builtin_arm_rsr64("CNTPCT_EL0");
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67 return KERN_SUCCESS;
68 }
69#endif
70 return KERN_NOT_SUPPORTED;
71}
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72
73__attribute__((visibility("hidden")))
74kern_return_t
75_mach_continuous_time(uint64_t* absolute_time, uint64_t* cont_time)
76{
77 volatile uint64_t *base_ptr = (volatile uint64_t*)_COMM_PAGE_CONT_TIMEBASE;
78 volatile uint64_t read1, read2;
79 volatile uint64_t absolute;
80
81 do {
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82 read1 = *base_ptr;
83 absolute = mach_absolute_time();
84#if defined(__arm__) || defined(__arm64__)
85 /*
86 * mach_absolute_time() contains an instruction barrier which will
87 * prevent the speculation of read2 above this point, so we don't
88 * need another barrier here.
89 */
5ba3f43e 90#endif
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91 read2 = *base_ptr;
92 } while (__builtin_expect((read1 != read2), 0));
93
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94 if (absolute_time) {
95 *absolute_time = absolute;
96 }
97 if (cont_time) {
98 *cont_time = absolute + read1;
99 }
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100
101 return KERN_SUCCESS;
102}
103
104uint64_t
105mach_continuous_time(void)
106{
107 uint64_t cont_time;
0a7de745 108 if (_mach_continuous_hwclock(&cont_time) != KERN_SUCCESS) {
5ba3f43e 109 _mach_continuous_time(NULL, &cont_time);
0a7de745 110 }
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111 return cont_time;
112}
113
114uint64_t
115mach_continuous_approximate_time(void)
116{
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117 /*
118 * No retry loop here because if we use a slightly too old timebase that's
119 * okay, we are approximate time anyway.
0a7de745 120 */
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121 volatile register uint64_t time_base = _mach_continuous_time_base();
122 return time_base + mach_approximate_time();
39037602 123}