[apple/xnu.git] / pexpert / i386 / pe_serial.c

/*
 * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
 * 
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. The rights granted to you under the License
 * may not be used to create, or enable the creation or redistribution of,
 * unlawful or unlicensed copies of an Apple operating system, or to
 * circumvent, violate, or enable the circumvention or violation of, any
 * terms of an Apple operating system software license agreement.
 * 
 * Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this file.
 * 
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 * 
 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
 */

/*
 * file: pe_serial.c
 *       Polled-mode 16x50 UART driver.
 */

#include <machine/machine_routines.h>
#include <pexpert/protos.h>
#include <pexpert/pexpert.h>

struct pe_serial_functions {
    void            (*uart_init) (void);
    void            (*uart_set_baud_rate) (int unit, uint32_t baud_rate);
    int             (*tr0) (void);
    void            (*td0) (int c);
    int             (*rr0) (void);
    int             (*rd0) (void);
};

static struct pe_serial_functions *gPESF;

static int uart_initted = 0;   /* 1 if init'ed */

static unsigned int legacy_uart_enabled = 0; /* 1 Legacy IO based UART is supported on platform */

static boolean_t lpss_uart_supported = 0; /* 1 if LPSS UART is supported on platform */
static unsigned int lpss_uart_enabled = 0; /* 1 if it is LPSS UART is in D0 state */
static void lpss_uart_re_init (void);

static boolean_t pcie_uart_enabled = 0; /* 1 if PCIe UART is supported on platform */

#define DEFAULT_UART_BAUD_RATE 115200

static unsigned uart_baud_rate = DEFAULT_UART_BAUD_RATE;

// =============================================================================
// Legacy UART support using IO transactions to COM1 or COM2
// =============================================================================

#define LEGACY_UART_PORT_ADDR   COM1_PORT_ADDR
#define LEGACY_UART_CLOCK       1843200   /* 1.8432 MHz clock */

#define IO_WRITE(r, v)  outb(LEGACY_UART_PORT_ADDR + UART_##r, v)
#define IO_READ(r)      inb(LEGACY_UART_PORT_ADDR + UART_##r)

enum {
    COM1_PORT_ADDR = 0x3f8,
    COM2_PORT_ADDR = 0x2f8
};

enum {
    UART_RBR = 0,  /* receive buffer Register   (R) */
    UART_THR = 0,  /* transmit holding register (W) */
    UART_DLL = 0,  /* DLAB = 1, divisor latch (LSB) */
    UART_IER = 1,  /* interrupt enable register     */
    UART_DLM = 1,  /* DLAB = 1, divisor latch (MSB) */
    UART_IIR = 2,  /* interrupt ident register (R)  */
    UART_FCR = 2,  /* fifo control register (W)     */
    UART_LCR = 3,  /* line control register         */
    UART_MCR = 4,  /* modem control register        */
    UART_LSR = 5,  /* line status register          */
    UART_MSR = 6,  /* modem status register         */
    UART_SCR = 7   /* scratch register              */
};

enum {
    UART_LCR_8BITS = 0x03,
    UART_LCR_DLAB  = 0x80
};

enum {
    UART_MCR_DTR   = 0x01,
    UART_MCR_RTS   = 0x02,
    UART_MCR_OUT1  = 0x04,
    UART_MCR_OUT2  = 0x08,
    UART_MCR_LOOP  = 0x10
};

enum {
    UART_LSR_DR    = 0x01,
    UART_LSR_OE    = 0x02,
    UART_LSR_PE    = 0x04,
    UART_LSR_FE    = 0x08,
    UART_LSR_THRE  = 0x20
};

enum {
	UART_CLK_125M_1 = 0x60002,
	UART_CLK_125M_2 = 0x80060003,
};

static int
legacy_uart_probe( void )
{
    /* Verify that the Scratch Register is accessible */

    IO_WRITE( SCR, 0x5a );
    if (IO_READ(SCR) != 0x5a) return 0;
    IO_WRITE( SCR, 0xa5 );
    if (IO_READ(SCR) != 0xa5) return 0;
    return 1;
}

static void
legacy_uart_set_baud_rate( __unused int unit, uint32_t baud_rate )
{
    const unsigned char lcr = IO_READ( LCR );
    unsigned long       div;

    if (baud_rate == 0) baud_rate = 9600;
    div = LEGACY_UART_CLOCK / 16 / baud_rate;
    IO_WRITE( LCR, lcr | UART_LCR_DLAB );
    IO_WRITE( DLM, (unsigned char)(div >> 8) );
    IO_WRITE( DLL, (unsigned char) div );
    IO_WRITE( LCR, lcr & ~UART_LCR_DLAB);
}

static int
legacy_uart_tr0( void )
{
    return (IO_READ(LSR) & UART_LSR_THRE);
}

static void
legacy_uart_td0( int c )
{
    IO_WRITE( THR, c );
}

static void
legacy_uart_init( void )
{
    /* Disable hardware interrupts */

    IO_WRITE( MCR, 0 );
    IO_WRITE( IER, 0 );

    /* Disable FIFO's for 16550 devices */

    IO_WRITE( FCR, 0 );

    /* Set for 8-bit, no parity, DLAB bit cleared */

    IO_WRITE( LCR, UART_LCR_8BITS );

    /* Set baud rate */

    gPESF->uart_set_baud_rate ( 0, uart_baud_rate );

    /* Assert DTR# and RTS# lines (OUT2?) */

    IO_WRITE( MCR, UART_MCR_DTR | UART_MCR_RTS );

    /* Clear any garbage in the input buffer */

    IO_READ( RBR );

    uart_initted = 1;
}

static int
legacy_uart_rr0( void ) 
{
    unsigned char lsr;

    lsr = IO_READ( LSR );

    if ( lsr & (UART_LSR_FE | UART_LSR_PE | UART_LSR_OE) )
    {
        IO_READ( RBR ); /* discard */
        return 0;
    }

    return (lsr & UART_LSR_DR);
}

static int
legacy_uart_rd0( void ) 
{
    return IO_READ( RBR );
}

static struct pe_serial_functions legacy_uart_serial_functions = {
    .uart_init = legacy_uart_init,
    .uart_set_baud_rate = legacy_uart_set_baud_rate,
    .tr0 = legacy_uart_tr0,
    .td0 = legacy_uart_td0,
    .rr0 = legacy_uart_rr0,
    .rd0 = legacy_uart_rd0
};

// =============================================================================
// MMIO UART (using PCH LPSS UART2)
// =============================================================================

#define MMIO_UART2_BASE_LEGACY  0xFE034000 /* Legacy MMIO Config space */
#define MMIO_UART2_BASE         0xFE036000 /* MMIO Config space */
#define PCI_UART2               0xFE037000 /* PCI Config Space */

#define MMIO_WRITE(r, v)  ml_phys_write_word(mmio_uart_base + MMIO_UART_##r, v)
#define MMIO_READ(r)      ml_phys_read_word(mmio_uart_base + MMIO_UART_##r)

enum {
    MMIO_UART_RBR = 0x0,   /* receive buffer Register   (R) */
    MMIO_UART_THR = 0x0,   /* transmit holding register (W) */
    MMIO_UART_DLL = 0x0,   /* DLAB = 1, divisor latch (LSB) */
    MMIO_UART_IER = 0x4,   /* interrupt enable register     */
    MMIO_UART_DLM = 0x4,   /* DLAB = 1, divisor latch (MSB) */
    MMIO_UART_FCR = 0x8,   /* fifo control register (W)     */
    MMIO_UART_LCR = 0xc,   /* line control register         */
    MMIO_UART_MCR = 0x10,  /* modem control register        */
    MMIO_UART_LSR = 0x14,  /* line status register          */
    MMIO_UART_SCR = 0x1c,  /* scratch register              */
    MMIO_UART_CLK = 0x200, /* clocks register               */
    MMIO_UART_RST = 0x204  /* Reset register              */
};

static vm_offset_t mmio_uart_base = 0;
 
static int
mmio_uart_present( void )
{
    MMIO_WRITE( SCR, 0x5a );
    if (MMIO_READ(SCR) != 0x5a) return 0;
    MMIO_WRITE( SCR, 0xa5 );
    if (MMIO_READ(SCR) != 0xa5) return 0;
    return 1;
}

static int
mmio_uart_probe( void )
{
    unsigned new_mmio_uart_base = 0;

    // if specified, mmio_uart overrides all probing
    if (PE_parse_boot_argn("mmio_uart", &new_mmio_uart_base, sizeof (new_mmio_uart_base)))
    {
        // mmio_uart=0 will disable mmio_uart support
        if (new_mmio_uart_base == 0) {
            return 0;
        }

        mmio_uart_base = new_mmio_uart_base;
        return 1;
    }

    // probe the two possible MMIO_UART2 addresses
    mmio_uart_base = MMIO_UART2_BASE;
    if (mmio_uart_present()) {
      return 1;
    }

    mmio_uart_base = MMIO_UART2_BASE_LEGACY;
    if (mmio_uart_present()) {
      return 1;
    }

    // no mmio uart found
    return 0;
}

static void
mmio_uart_set_baud_rate( __unused int unit, __unused uint32_t baud_rate )
{
    const unsigned char lcr = MMIO_READ( LCR );
    unsigned long       div;

    if (baud_rate == 0) baud_rate = 9600;
    div = LEGACY_UART_CLOCK / 16 / baud_rate;

    MMIO_WRITE( LCR, lcr | UART_LCR_DLAB );
    MMIO_WRITE( DLM, (unsigned char)(div >> 8) );
    MMIO_WRITE( DLL, (unsigned char) div );
    MMIO_WRITE( LCR, lcr & ~UART_LCR_DLAB);
}

static int
mmio_uart_tr0( void )
{
    return (MMIO_READ(LSR) & UART_LSR_THRE);
}

static void
mmio_uart_td0( int c )
{
    MMIO_WRITE( THR, c );
}

static void
mmio_uart_init( void )
{
    /* Disable hardware interrupts */

    MMIO_WRITE( MCR, 0 );
    MMIO_WRITE( IER, 0 );

    /* Disable FIFO's for 16550 devices */

    MMIO_WRITE( FCR, 0 );

    /* Set for 8-bit, no parity, DLAB bit cleared */

    MMIO_WRITE( LCR, UART_LCR_8BITS );

    /* Leave baud rate as set by firmware unless serialbaud boot-arg overrides */

    if (uart_baud_rate != DEFAULT_UART_BAUD_RATE) 
    {
        gPESF->uart_set_baud_rate ( 0, uart_baud_rate );
    }

    /* Assert DTR# and RTS# lines (OUT2?) */

    MMIO_WRITE( MCR, UART_MCR_DTR | UART_MCR_RTS );

    /* Clear any garbage in the input buffer */

    MMIO_READ( RBR );

    uart_initted = 1;
}

static int
mmio_uart_rr0( void ) 
{
    unsigned char lsr;

    lsr = MMIO_READ( LSR );

    if ( lsr & (UART_LSR_FE | UART_LSR_PE | UART_LSR_OE) )
    {
        MMIO_READ( RBR ); /* discard */
        return 0;
    }
    
    return (lsr & UART_LSR_DR);
}

void lpss_uart_enable( boolean_t on_off )
{
	unsigned int pmcs_reg;

	if (!lpss_uart_supported) {
		return;
	}

	pmcs_reg = ml_phys_read_byte (PCI_UART2 + 0x84);
	if (on_off == FALSE) {
		pmcs_reg |= 0x03;
		lpss_uart_enabled = 0;
	} else {
		pmcs_reg &= ~(0x03);
	}

	ml_phys_write_byte (PCI_UART2 + 0x84, pmcs_reg);
	pmcs_reg = ml_phys_read_byte (PCI_UART2 + 0x84);
	
	if (on_off == TRUE) {
		lpss_uart_re_init();
		lpss_uart_enabled = 1;
	}
}

static void lpss_uart_re_init( void )
{
	uint32_t register_read;
	
	MMIO_WRITE (RST, 0x7);				/* LPSS UART2 controller out ot reset */
	register_read = MMIO_READ (RST);

	MMIO_WRITE (LCR, UART_LCR_DLAB);	/* Set DLAB bit to enable reading/writing of DLL, DLH */
	register_read = MMIO_READ (LCR);

	MMIO_WRITE (DLL, 1);				/* Divisor Latch Low Register */
	register_read = MMIO_READ (DLL);

	MMIO_WRITE (DLM, 0);				/* Divisor Latch High Register */
	register_read = MMIO_READ (DLM);

	MMIO_WRITE (FCR, 1);				/* Enable FIFO */
	register_read = MMIO_READ (FCR);

	MMIO_WRITE (LCR, UART_LCR_8BITS);	/* Set 8 bits, clear DLAB */
	register_read = MMIO_READ (LCR);

	MMIO_WRITE (MCR, UART_MCR_RTS);		/* Request to send */
	register_read = MMIO_READ (MCR);

	MMIO_WRITE (CLK, UART_CLK_125M_1);	/* 1.25M Clock speed */
	register_read = MMIO_READ (CLK);

	MMIO_WRITE (CLK, UART_CLK_125M_2);	/* 1.25M Clock speed */
	register_read = MMIO_READ (CLK);	
}

static int
mmio_uart_rd0( void ) 
{
    return MMIO_READ( RBR );
}

static struct pe_serial_functions mmio_uart_serial_functions = {
    .uart_init = mmio_uart_init,
    .uart_set_baud_rate = mmio_uart_set_baud_rate,
    .tr0 = mmio_uart_tr0,
    .td0 = mmio_uart_td0,
    .rr0 = mmio_uart_rr0,
    .rd0 = mmio_uart_rd0
};

// =============================================================================
// PCIE_MMIO UART 
// =============================================================================

#define PCIE_MMIO_UART_BASE         0xFE410000

#define PCIE_MMIO_WRITE(r, v)  ml_phys_write_byte(pcie_mmio_uart_base + PCIE_MMIO_UART_##r, v)
#define PCIE_MMIO_READ(r)      ml_phys_read_byte(pcie_mmio_uart_base + PCIE_MMIO_UART_##r)

enum {
    PCIE_MMIO_UART_RBR = 0x0,   /* receive buffer Register   (R) */
    PCIE_MMIO_UART_THR = 0x0,   /* transmit holding register (W) */
    PCIE_MMIO_UART_IER = 0x1,   /* interrupt enable register     */
    PCIE_MMIO_UART_FCR = 0x2,   /* fifo control register (W)     */
    PCIE_MMIO_UART_LCR = 0x4,   /* line control register         */
    PCIE_MMIO_UART_MCR = 0x4,  /* modem control register        */
    PCIE_MMIO_UART_LSR = 0x5,  /* line status register          */
    PCIE_MMIO_UART_DLL = 0x8,   /* DLAB = 1, divisor latch (LSB) */
    PCIE_MMIO_UART_DLM = 0x9,   /* DLAB = 1, divisor latch (MSB) */
    PCIE_MMIO_UART_SCR = 0x30,   /* scratch register              */
};

static vm_offset_t pcie_mmio_uart_base = 0;
 
static int
pcie_mmio_uart_present( void )
{

    PCIE_MMIO_WRITE( SCR, 0x5a );
    if (PCIE_MMIO_READ(SCR) != 0x5a) return 0;
    PCIE_MMIO_WRITE( SCR, 0xa5 );
    if (PCIE_MMIO_READ(SCR) != 0xa5) return 0;

    return 1;
}

static int
pcie_mmio_uart_probe( void )
{
    unsigned new_pcie_mmio_uart_base = 0;

    // if specified, pcie_mmio_uart overrides all probing
    if (PE_parse_boot_argn("pcie_mmio_uart", &new_pcie_mmio_uart_base, sizeof (new_pcie_mmio_uart_base)))
    {
        // pcie_mmio_uart=0 will disable pcie_mmio_uart support
        if (new_pcie_mmio_uart_base == 0) {
            return 0;
        }
        pcie_mmio_uart_base = new_pcie_mmio_uart_base;
        return 1;
    }

    pcie_mmio_uart_base = PCIE_MMIO_UART_BASE;
    if (pcie_mmio_uart_present()) {
      return 1;
    }

    // no pcie_mmio uart found
    return 0;
}

static void
pcie_mmio_uart_set_baud_rate( __unused int unit, __unused uint32_t baud_rate )
{
    const unsigned char lcr = PCIE_MMIO_READ( LCR );
    unsigned long       div;

    if (baud_rate == 0) baud_rate = 9600;
    div = LEGACY_UART_CLOCK / 16 / baud_rate;

    PCIE_MMIO_WRITE( LCR, lcr | UART_LCR_DLAB );
    PCIE_MMIO_WRITE( DLM, (unsigned char)(div >> 8) );
    PCIE_MMIO_WRITE( DLL, (unsigned char) div );
    PCIE_MMIO_WRITE( LCR, lcr & ~UART_LCR_DLAB);
}

static int
pcie_mmio_uart_tr0( void )
{
    return (PCIE_MMIO_READ(LSR) & UART_LSR_THRE);
}

static void
pcie_mmio_uart_td0( int c )
{
    PCIE_MMIO_WRITE( THR, c );
}

static void
pcie_mmio_uart_init( void )
{
    uart_initted = 1;
}

static int
pcie_mmio_uart_rr0( void ) 
{
    unsigned char lsr;

    lsr = PCIE_MMIO_READ( LSR );

    if ( lsr & (UART_LSR_FE | UART_LSR_PE | UART_LSR_OE) )
    {
        PCIE_MMIO_READ( RBR ); /* discard */
        return 0;
    }
    
    return (lsr & UART_LSR_DR);
}

static int
pcie_mmio_uart_rd0( void ) 
{
    return PCIE_MMIO_READ( RBR );
}

static struct pe_serial_functions pcie_mmio_uart_serial_functions = {
    .uart_init = pcie_mmio_uart_init,
    .uart_set_baud_rate = pcie_mmio_uart_set_baud_rate,
    .tr0 = pcie_mmio_uart_tr0,
    .td0 = pcie_mmio_uart_td0,
    .rr0 = pcie_mmio_uart_rr0,
    .rd0 = pcie_mmio_uart_rd0
};

// =============================================================================
// Generic serial support below
// =============================================================================

int
serial_init( void )
{
    unsigned new_uart_baud_rate = 0;

    if (PE_parse_boot_argn("serialbaud", &new_uart_baud_rate, sizeof (new_uart_baud_rate)))
    {
        /* Valid divisor? */
        if (!((LEGACY_UART_CLOCK / 16) % new_uart_baud_rate)) {
            uart_baud_rate = new_uart_baud_rate;
        }
    }

    if ( mmio_uart_probe() )
    {
        gPESF = &mmio_uart_serial_functions;
        gPESF->uart_init();
        lpss_uart_supported = 1;
        lpss_uart_enabled = 1;
        return 1;
    }
    else if ( legacy_uart_probe() )
    {
        gPESF = &legacy_uart_serial_functions;
        gPESF->uart_init();
        legacy_uart_enabled = 1;
        return 1;
    }
    else if ( pcie_mmio_uart_probe() )
    {
        gPESF = &pcie_mmio_uart_serial_functions;
        gPESF->uart_init();
        pcie_uart_enabled = 1;
        return 1;
    }
    else
    {
        return 0;
    }

}

static void
uart_putc(char c)
{
	if (uart_initted && (legacy_uart_enabled || lpss_uart_enabled || pcie_uart_enabled)) {
        while (!gPESF->tr0());  /* Wait until THR is empty. */
        gPESF->td0(c);
    }
}

static int
uart_getc(void)
{
    if (uart_initted && (legacy_uart_enabled || lpss_uart_enabled || pcie_uart_enabled)) {
        if (!gPESF->rr0())
            return -1;
        return gPESF->rd0();
    }
    return -1;
}

void
serial_putc( char c )
{
    uart_putc(c);
}

int
serial_getc( void )
{
    return uart_getc();
}
Commit	Line	Data
55e303ae	1	/*
2d21ac55	2	* Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
55e303ae	3	*
2d21ac55	4	* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
55e303ae	5	*
2d21ac55 A	6	* This file contains Original Code and/or Modifications of Original Code
	7	* as defined in and that are subject to the Apple Public Source License
	8	* Version 2.0 (the 'License'). You may not use this file except in
	9	* compliance with the License. The rights granted to you under the License
	10	* may not be used to create, or enable the creation or redistribution of,
	11	* unlawful or unlicensed copies of an Apple operating system, or to
	12	* circumvent, violate, or enable the circumvention or violation of, any
	13	* terms of an Apple operating system software license agreement.
8f6c56a5	14	*
2d21ac55 A	15	* Please obtain a copy of the License at
	16	* http://www.opensource.apple.com/apsl/ and read it before using this file.
	17	*
	18	* The Original Code and all software distributed under the License are
	19	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
8f6c56a5 A	20	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
8f6c56a5 A	21	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
2d21ac55 A	22	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	23	* Please see the License for the specific language governing rights and
	24	* limitations under the License.
8f6c56a5	25	*
2d21ac55	26	* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
55e303ae A	27	*/
	28
	29	/*
	30	* file: pe_serial.c
	31	* Polled-mode 16x50 UART driver.
	32	*/
	33
813fb2f6	34	#include <machine/machine_routines.h>
55e303ae A	35	#include <pexpert/protos.h>
	36	#include <pexpert/pexpert.h>
	37
813fb2f6 A	38	struct pe_serial_functions {
	39	void (*uart_init) (void);
	40	void (*uart_set_baud_rate) (int unit, uint32_t baud_rate);
	41	int (*tr0) (void);
	42	void (*td0) (int c);
	43	int (*rr0) (void);
	44	int (*rd0) (void);
	45	};
	46
	47	static struct pe_serial_functions *gPESF;
	48
	49	static int uart_initted = 0; /* 1 if init'ed */
	50
a39ff7e2 A	51	static unsigned int legacy_uart_enabled = 0; /* 1 Legacy IO based UART is supported on platform */
	52
	53	static boolean_t lpss_uart_supported = 0; /* 1 if LPSS UART is supported on platform */
	54	static unsigned int lpss_uart_enabled = 0; /* 1 if it is LPSS UART is in D0 state */
	55	static void lpss_uart_re_init (void);
	56
d9a64523 A	57	static boolean_t pcie_uart_enabled = 0; /* 1 if PCIe UART is supported on platform */
d9a64523 A	58
813fb2f6 A	59	#define DEFAULT_UART_BAUD_RATE 115200
	60
	61	static unsigned uart_baud_rate = DEFAULT_UART_BAUD_RATE;
	62
	63	// =============================================================================
	64	// Legacy UART support using IO transactions to COM1 or COM2
	65	// =============================================================================
	66
	67	#define LEGACY_UART_PORT_ADDR COM1_PORT_ADDR
	68	#define LEGACY_UART_CLOCK 1843200 /* 1.8432 MHz clock */
	69
	70	#define IO_WRITE(r, v) outb(LEGACY_UART_PORT_ADDR + UART_##r, v)
	71	#define IO_READ(r) inb(LEGACY_UART_PORT_ADDR + UART_##r)
	72
55e303ae A	73	enum {
	74	COM1_PORT_ADDR = 0x3f8,
	75	COM2_PORT_ADDR = 0x2f8
	76	};
	77
55e303ae A	78	enum {
	79	UART_RBR = 0, /* receive buffer Register (R) */
	80	UART_THR = 0, /* transmit holding register (W) */
	81	UART_DLL = 0, /* DLAB = 1, divisor latch (LSB) */
	82	UART_IER = 1, /* interrupt enable register */
	83	UART_DLM = 1, /* DLAB = 1, divisor latch (MSB) */
	84	UART_IIR = 2, /* interrupt ident register (R) */
	85	UART_FCR = 2, /* fifo control register (W) */
	86	UART_LCR = 3, /* line control register */
	87	UART_MCR = 4, /* modem control register */
	88	UART_LSR = 5, /* line status register */
593a1d5f A	89	UART_MSR = 6, /* modem status register */
593a1d5f A	90	UART_SCR = 7 /* scratch register */
55e303ae A	91	};
	92
	93	enum {
	94	UART_LCR_8BITS = 0x03,
	95	UART_LCR_DLAB = 0x80
	96	};
	97
	98	enum {
	99	UART_MCR_DTR = 0x01,
	100	UART_MCR_RTS = 0x02,
	101	UART_MCR_OUT1 = 0x04,
	102	UART_MCR_OUT2 = 0x08,
	103	UART_MCR_LOOP = 0x10
	104	};
	105
	106	enum {
0c530ab8 A	107	UART_LSR_DR = 0x01,
	108	UART_LSR_OE = 0x02,
	109	UART_LSR_PE = 0x04,
	110	UART_LSR_FE = 0x08,
55e303ae A	111	UART_LSR_THRE = 0x20
	112	};
	113
a39ff7e2 A	114	enum {
	115	UART_CLK_125M_1 = 0x60002,
	116	UART_CLK_125M_2 = 0x80060003,
	117	};
	118
55e303ae	119	static int
813fb2f6	120	legacy_uart_probe( void )
55e303ae	121	{
593a1d5f A	122	/* Verify that the Scratch Register is accessible */
593a1d5f A	123
813fb2f6 A	124	IO_WRITE( SCR, 0x5a );
	125	if (IO_READ(SCR) != 0x5a) return 0;
	126	IO_WRITE( SCR, 0xa5 );
	127	if (IO_READ(SCR) != 0xa5) return 0;
55e303ae A	128	return 1;
	129	}
	130
	131	static void
813fb2f6	132	legacy_uart_set_baud_rate( __unused int unit, uint32_t baud_rate )
55e303ae	133	{
813fb2f6	134	const unsigned char lcr = IO_READ( LCR );
55e303ae A	135	unsigned long div;
	136
	137	if (baud_rate == 0) baud_rate = 9600;
813fb2f6 A	138	div = LEGACY_UART_CLOCK / 16 / baud_rate;
	139	IO_WRITE( LCR, lcr \| UART_LCR_DLAB );
	140	IO_WRITE( DLM, (unsigned char)(div >> 8) );
	141	IO_WRITE( DLL, (unsigned char) div );
	142	IO_WRITE( LCR, lcr & ~UART_LCR_DLAB);
	143	}
	144
	145	static int
	146	legacy_uart_tr0( void )
	147	{
	148	return (IO_READ(LSR) & UART_LSR_THRE);
	149	}
	150
	151	static void
	152	legacy_uart_td0( int c )
	153	{
	154	IO_WRITE( THR, c );
55e303ae A	155	}
	156
	157	static void
813fb2f6	158	legacy_uart_init( void )
55e303ae	159	{
813fb2f6 A	160	/* Disable hardware interrupts */
	161
	162	IO_WRITE( MCR, 0 );
	163	IO_WRITE( IER, 0 );
	164
	165	/* Disable FIFO's for 16550 devices */
	166
	167	IO_WRITE( FCR, 0 );
	168
	169	/* Set for 8-bit, no parity, DLAB bit cleared */
	170
	171	IO_WRITE( LCR, UART_LCR_8BITS );
	172
	173	/* Set baud rate */
55e303ae	174
813fb2f6	175	gPESF->uart_set_baud_rate ( 0, uart_baud_rate );
55e303ae	176
813fb2f6 A	177	/* Assert DTR# and RTS# lines (OUT2?) */
	178
	179	IO_WRITE( MCR, UART_MCR_DTR \| UART_MCR_RTS );
	180
	181	/* Clear any garbage in the input buffer */
	182
	183	IO_READ( RBR );
	184
	185	uart_initted = 1;
55e303ae A	186	}
55e303ae A	187
0c530ab8	188	static int
813fb2f6	189	legacy_uart_rr0( void )
0c530ab8	190	{
0c530ab8 A	191	unsigned char lsr;
0c530ab8 A	192
813fb2f6	193	lsr = IO_READ( LSR );
0c530ab8 A	194
	195	if ( lsr & (UART_LSR_FE \| UART_LSR_PE \| UART_LSR_OE) )
	196	{
813fb2f6 A	197	IO_READ( RBR ); /* discard */
813fb2f6 A	198	return 0;
0c530ab8 A	199	}
0c530ab8 A	200
813fb2f6 A	201	return (lsr & UART_LSR_DR);
	202	}
	203
	204	static int
	205	legacy_uart_rd0( void )
	206	{
	207	return IO_READ( RBR );
	208	}
	209
	210	static struct pe_serial_functions legacy_uart_serial_functions = {
	211	.uart_init = legacy_uart_init,
	212	.uart_set_baud_rate = legacy_uart_set_baud_rate,
	213	.tr0 = legacy_uart_tr0,
	214	.td0 = legacy_uart_td0,
	215	.rr0 = legacy_uart_rr0,
	216	.rd0 = legacy_uart_rd0
	217	};
	218
	219	// =============================================================================
	220	// MMIO UART (using PCH LPSS UART2)
	221	// =============================================================================
	222
a39ff7e2 A	223	#define MMIO_UART2_BASE_LEGACY 0xFE034000 /* Legacy MMIO Config space */
	224	#define MMIO_UART2_BASE 0xFE036000 /* MMIO Config space */
	225	#define PCI_UART2 0xFE037000 /* PCI Config Space */
813fb2f6 A	226
	227	#define MMIO_WRITE(r, v) ml_phys_write_word(mmio_uart_base + MMIO_UART_##r, v)
	228	#define MMIO_READ(r) ml_phys_read_word(mmio_uart_base + MMIO_UART_##r)
	229
	230	enum {
	231	MMIO_UART_RBR = 0x0, /* receive buffer Register (R) */
	232	MMIO_UART_THR = 0x0, /* transmit holding register (W) */
	233	MMIO_UART_DLL = 0x0, /* DLAB = 1, divisor latch (LSB) */
	234	MMIO_UART_IER = 0x4, /* interrupt enable register */
	235	MMIO_UART_DLM = 0x4, /* DLAB = 1, divisor latch (MSB) */
	236	MMIO_UART_FCR = 0x8, /* fifo control register (W) */
	237	MMIO_UART_LCR = 0xc, /* line control register */
	238	MMIO_UART_MCR = 0x10, /* modem control register */
	239	MMIO_UART_LSR = 0x14, /* line status register */
a39ff7e2 A	240	MMIO_UART_SCR = 0x1c, /* scratch register */
	241	MMIO_UART_CLK = 0x200, /* clocks register */
	242	MMIO_UART_RST = 0x204 /* Reset register */
813fb2f6 A	243	};
	244
	245	static vm_offset_t mmio_uart_base = 0;
	246
	247	static int
	248	mmio_uart_present( void )
	249	{
	250	MMIO_WRITE( SCR, 0x5a );
	251	if (MMIO_READ(SCR) != 0x5a) return 0;
	252	MMIO_WRITE( SCR, 0xa5 );
	253	if (MMIO_READ(SCR) != 0xa5) return 0;
813fb2f6 A	254	return 1;
	255	}
	256
	257	static int
	258	mmio_uart_probe( void )
	259	{
	260	unsigned new_mmio_uart_base = 0;
	261
	262	// if specified, mmio_uart overrides all probing
	263	if (PE_parse_boot_argn("mmio_uart", &new_mmio_uart_base, sizeof (new_mmio_uart_base)))
0c530ab8	264	{
813fb2f6 A	265	// mmio_uart=0 will disable mmio_uart support
	266	if (new_mmio_uart_base == 0) {
	267	return 0;
	268	}
	269
	270	mmio_uart_base = new_mmio_uart_base;
	271	return 1;
0c530ab8 A	272	}
0c530ab8 A	273
813fb2f6 A	274	// probe the two possible MMIO_UART2 addresses
	275	mmio_uart_base = MMIO_UART2_BASE;
	276	if (mmio_uart_present()) {
	277	return 1;
	278	}
	279
	280	mmio_uart_base = MMIO_UART2_BASE_LEGACY;
	281	if (mmio_uart_present()) {
	282	return 1;
	283	}
	284
	285	// no mmio uart found
	286	return 0;
	287	}
	288
	289	static void
	290	mmio_uart_set_baud_rate( __unused int unit, __unused uint32_t baud_rate )
	291	{
	292	const unsigned char lcr = MMIO_READ( LCR );
	293	unsigned long div;
	294
	295	if (baud_rate == 0) baud_rate = 9600;
	296	div = LEGACY_UART_CLOCK / 16 / baud_rate;
	297
	298	MMIO_WRITE( LCR, lcr \| UART_LCR_DLAB );
	299	MMIO_WRITE( DLM, (unsigned char)(div >> 8) );
	300	MMIO_WRITE( DLL, (unsigned char) div );
	301	MMIO_WRITE( LCR, lcr & ~UART_LCR_DLAB);
	302	}
	303
	304	static int
	305	mmio_uart_tr0( void )
	306	{
	307	return (MMIO_READ(LSR) & UART_LSR_THRE);
0c530ab8 A	308	}
0c530ab8 A	309
813fb2f6 A	310	static void
813fb2f6 A	311	mmio_uart_td0( int c )
55e303ae	312	{
813fb2f6 A	313	MMIO_WRITE( THR, c );
813fb2f6 A	314	}
55e303ae	315
813fb2f6 A	316	static void
	317	mmio_uart_init( void )
	318	{
55e303ae A	319	/* Disable hardware interrupts */
55e303ae A	320
813fb2f6 A	321	MMIO_WRITE( MCR, 0 );
813fb2f6 A	322	MMIO_WRITE( IER, 0 );
55e303ae A	323
	324	/* Disable FIFO's for 16550 devices */
	325
813fb2f6	326	MMIO_WRITE( FCR, 0 );
55e303ae A	327
	328	/* Set for 8-bit, no parity, DLAB bit cleared */
	329
813fb2f6	330	MMIO_WRITE( LCR, UART_LCR_8BITS );
55e303ae	331
813fb2f6	332	/* Leave baud rate as set by firmware unless serialbaud boot-arg overrides */
55e303ae	333
813fb2f6	334	if (uart_baud_rate != DEFAULT_UART_BAUD_RATE)
0c530ab8	335	{
813fb2f6	336	gPESF->uart_set_baud_rate ( 0, uart_baud_rate );
0c530ab8	337	}
55e303ae A	338
	339	/* Assert DTR# and RTS# lines (OUT2?) */
	340
813fb2f6	341	MMIO_WRITE( MCR, UART_MCR_DTR \| UART_MCR_RTS );
55e303ae A	342
	343	/* Clear any garbage in the input buffer */
	344
813fb2f6	345	MMIO_READ( RBR );
55e303ae A	346
55e303ae A	347	uart_initted = 1;
813fb2f6	348	}
55e303ae	349
813fb2f6 A	350	static int
	351	mmio_uart_rr0( void )
	352	{
	353	unsigned char lsr;
	354
	355	lsr = MMIO_READ( LSR );
	356
	357	if ( lsr & (UART_LSR_FE \| UART_LSR_PE \| UART_LSR_OE) )
	358	{
	359	MMIO_READ( RBR ); /* discard */
	360	return 0;
	361	}
	362
	363	return (lsr & UART_LSR_DR);
	364	}
	365
a39ff7e2 A	366	void lpss_uart_enable( boolean_t on_off )
	367	{
	368	unsigned int pmcs_reg;
	369
	370	if (!lpss_uart_supported) {
	371	return;
	372	}
	373
	374	pmcs_reg = ml_phys_read_byte (PCI_UART2 + 0x84);
	375	if (on_off == FALSE) {
	376	pmcs_reg \|= 0x03;
	377	lpss_uart_enabled = 0;
	378	} else {
	379	pmcs_reg &= ~(0x03);
	380	}
	381
	382	ml_phys_write_byte (PCI_UART2 + 0x84, pmcs_reg);
	383	pmcs_reg = ml_phys_read_byte (PCI_UART2 + 0x84);
	384
	385	if (on_off == TRUE) {
	386	lpss_uart_re_init();
	387	lpss_uart_enabled = 1;
	388	}
	389	}
	390
	391	static void lpss_uart_re_init( void )
	392	{
	393	uint32_t register_read;
	394
	395	MMIO_WRITE (RST, 0x7); /* LPSS UART2 controller out ot reset */
	396	register_read = MMIO_READ (RST);
	397
	398	MMIO_WRITE (LCR, UART_LCR_DLAB); /* Set DLAB bit to enable reading/writing of DLL, DLH */
	399	register_read = MMIO_READ (LCR);
	400
	401	MMIO_WRITE (DLL, 1); /* Divisor Latch Low Register */
	402	register_read = MMIO_READ (DLL);
	403
	404	MMIO_WRITE (DLM, 0); /* Divisor Latch High Register */
	405	register_read = MMIO_READ (DLM);
	406
	407	MMIO_WRITE (FCR, 1); /* Enable FIFO */
	408	register_read = MMIO_READ (FCR);
	409
	410	MMIO_WRITE (LCR, UART_LCR_8BITS); /* Set 8 bits, clear DLAB */
	411	register_read = MMIO_READ (LCR);
	412
	413	MMIO_WRITE (MCR, UART_MCR_RTS); /* Request to send */
	414	register_read = MMIO_READ (MCR);
	415
	416	MMIO_WRITE (CLK, UART_CLK_125M_1); /* 1.25M Clock speed */
	417	register_read = MMIO_READ (CLK);
	418
	419	MMIO_WRITE (CLK, UART_CLK_125M_2); /* 1.25M Clock speed */
	420	register_read = MMIO_READ (CLK);
	421	}
	422
813fb2f6 A	423	static int
	424	mmio_uart_rd0( void )
	425	{
	426	return MMIO_READ( RBR );
	427	}
	428
	429	static struct pe_serial_functions mmio_uart_serial_functions = {
	430	.uart_init = mmio_uart_init,
	431	.uart_set_baud_rate = mmio_uart_set_baud_rate,
	432	.tr0 = mmio_uart_tr0,
	433	.td0 = mmio_uart_td0,
	434	.rr0 = mmio_uart_rr0,
	435	.rd0 = mmio_uart_rd0
	436	};
	437
d9a64523 A	438	// =============================================================================
	439	// PCIE_MMIO UART
	440	// =============================================================================
	441
	442	#define PCIE_MMIO_UART_BASE 0xFE410000
	443
	444	#define PCIE_MMIO_WRITE(r, v) ml_phys_write_byte(pcie_mmio_uart_base + PCIE_MMIO_UART_##r, v)
	445	#define PCIE_MMIO_READ(r) ml_phys_read_byte(pcie_mmio_uart_base + PCIE_MMIO_UART_##r)
	446
	447	enum {
	448	PCIE_MMIO_UART_RBR = 0x0, /* receive buffer Register (R) */
	449	PCIE_MMIO_UART_THR = 0x0, /* transmit holding register (W) */
	450	PCIE_MMIO_UART_IER = 0x1, /* interrupt enable register */
	451	PCIE_MMIO_UART_FCR = 0x2, /* fifo control register (W) */
	452	PCIE_MMIO_UART_LCR = 0x4, /* line control register */
	453	PCIE_MMIO_UART_MCR = 0x4, /* modem control register */
	454	PCIE_MMIO_UART_LSR = 0x5, /* line status register */
	455	PCIE_MMIO_UART_DLL = 0x8, /* DLAB = 1, divisor latch (LSB) */
	456	PCIE_MMIO_UART_DLM = 0x9, /* DLAB = 1, divisor latch (MSB) */
	457	PCIE_MMIO_UART_SCR = 0x30, /* scratch register */
	458	};
	459
	460	static vm_offset_t pcie_mmio_uart_base = 0;
	461
	462	static int
	463	pcie_mmio_uart_present( void )
	464	{
	465
	466	PCIE_MMIO_WRITE( SCR, 0x5a );
	467	if (PCIE_MMIO_READ(SCR) != 0x5a) return 0;
	468	PCIE_MMIO_WRITE( SCR, 0xa5 );
	469	if (PCIE_MMIO_READ(SCR) != 0xa5) return 0;
	470
	471	return 1;
	472	}
	473
	474	static int
	475	pcie_mmio_uart_probe( void )
	476	{
	477	unsigned new_pcie_mmio_uart_base = 0;
	478
	479	// if specified, pcie_mmio_uart overrides all probing
	480	if (PE_parse_boot_argn("pcie_mmio_uart", &new_pcie_mmio_uart_base, sizeof (new_pcie_mmio_uart_base)))
	481	{
	482	// pcie_mmio_uart=0 will disable pcie_mmio_uart support
	483	if (new_pcie_mmio_uart_base == 0) {
	484	return 0;
	485	}
	486	pcie_mmio_uart_base = new_pcie_mmio_uart_base;
	487	return 1;
	488	}
	489
	490	pcie_mmio_uart_base = PCIE_MMIO_UART_BASE;
	491	if (pcie_mmio_uart_present()) {
	492	return 1;
	493	}
	494
	495	// no pcie_mmio uart found
	496	return 0;
	497	}
	498
	499	static void
	500	pcie_mmio_uart_set_baud_rate( __unused int unit, __unused uint32_t baud_rate )
	501	{
502	const unsigned char lcr = PCIE_MMIO_READ( LCR );
503	unsigned long div;
504
505	if (baud_rate == 0) baud_rate = 9600;
506	div = LEGACY_UART_CLOCK / 16 / baud_rate;
507
508	PCIE_MMIO_WRITE( LCR, lcr \| UART_LCR_DLAB );
509	PCIE_MMIO_WRITE( DLM, (unsigned char)(div >> 8) );
510	PCIE_MMIO_WRITE( DLL, (unsigned char) div );
511	PCIE_MMIO_WRITE( LCR, lcr & ~UART_LCR_DLAB);
512	}
513
514	static int
515	pcie_mmio_uart_tr0( void )
516	{
517	return (PCIE_MMIO_READ(LSR) & UART_LSR_THRE);
518	}
519
520	static void
521	pcie_mmio_uart_td0( int c )
522	{
523	PCIE_MMIO_WRITE( THR, c );
524	}
525
526	static void
527	pcie_mmio_uart_init( void )
528	{
529	uart_initted = 1;
530	}
531
532	static int
533	pcie_mmio_uart_rr0( void )
534	{
535	unsigned char lsr;
536
537	lsr = PCIE_MMIO_READ( LSR );
538
539	if ( lsr & (UART_LSR_FE \| UART_LSR_PE \| UART_LSR_OE) )
540	{
541	PCIE_MMIO_READ( RBR ); /* discard */
542	return 0;
543	}
544
545	return (lsr & UART_LSR_DR);
546	}
547
548	static int
549	pcie_mmio_uart_rd0( void )
550	{
551	return PCIE_MMIO_READ( RBR );
552	}
553
554	static struct pe_serial_functions pcie_mmio_uart_serial_functions = {
555	.uart_init = pcie_mmio_uart_init,
556	.uart_set_baud_rate = pcie_mmio_uart_set_baud_rate,
557	.tr0 = pcie_mmio_uart_tr0,
558	.td0 = pcie_mmio_uart_td0,
559	.rr0 = pcie_mmio_uart_rr0,
560	.rd0 = pcie_mmio_uart_rd0
561	};
562
813fb2f6 A	563	// =============================================================================
	564	// Generic serial support below
	565	// =============================================================================
	566
	567	int
	568	serial_init( void )
	569	{
	570	unsigned new_uart_baud_rate = 0;
	571
	572	if (PE_parse_boot_argn("serialbaud", &new_uart_baud_rate, sizeof (new_uart_baud_rate)))
	573	{
	574	/* Valid divisor? */
	575	if (!((LEGACY_UART_CLOCK / 16) % new_uart_baud_rate)) {
	576	uart_baud_rate = new_uart_baud_rate;
	577	}
	578	}
	579
	580	if ( mmio_uart_probe() )
	581	{
	582	gPESF = &mmio_uart_serial_functions;
	583	gPESF->uart_init();
a39ff7e2 A	584	lpss_uart_supported = 1;
a39ff7e2 A	585	lpss_uart_enabled = 1;
813fb2f6 A	586	return 1;
	587	}
	588	else if ( legacy_uart_probe() )
	589	{
	590	gPESF = &legacy_uart_serial_functions;
	591	gPESF->uart_init();
a39ff7e2	592	legacy_uart_enabled = 1;
813fb2f6 A	593	return 1;
813fb2f6 A	594	}
d9a64523 A	595	else if ( pcie_mmio_uart_probe() )
	596	{
	597	gPESF = &pcie_mmio_uart_serial_functions;
	598	gPESF->uart_init();
	599	pcie_uart_enabled = 1;
	600	return 1;
	601	}
813fb2f6 A	602	else
	603	{
	604	return 0;
	605	}
	606
	607	}
	608
	609	static void
	610	uart_putc(char c)
	611	{
d9a64523	612	if (uart_initted && (legacy_uart_enabled \|\| lpss_uart_enabled \|\| pcie_uart_enabled)) {
813fb2f6 A	613	while (!gPESF->tr0()); /* Wait until THR is empty. */
	614	gPESF->td0(c);
	615	}
	616	}
	617
	618	static int
	619	uart_getc(void)
	620	{
d9a64523	621	if (uart_initted && (legacy_uart_enabled \|\| lpss_uart_enabled \|\| pcie_uart_enabled)) {
813fb2f6 A	622	if (!gPESF->rr0())
	623	return -1;
	624	return gPESF->rd0();
	625	}
	626	return -1;
55e303ae A	627	}
55e303ae A	628
813fb2f6 A	629	void
813fb2f6 A	630	serial_putc( char c )
55e303ae A	631	{
55e303ae A	632	uart_putc(c);
55e303ae A	633	}
55e303ae A	634
813fb2f6 A	635	int
813fb2f6 A	636	serial_getc( void )
55e303ae	637	{
0c530ab8	638	return uart_getc();
55e303ae	639	}