[apple/xnu.git] / osfmk / mach / i386 / fp_reg.h

/*
 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_LICENSE_HEADER_START@
 * 
 * The contents of this file constitute Original Code as defined in and
 * are subject to the Apple Public Source License Version 1.1 (the
 * "License").  You may not use this file except in compliance with the
 * License.  Please obtain a copy of the License at
 * http://www.apple.com/publicsource and read it before using this file.
 * 
 * This Original Code and all software distributed under the License are
 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
 * License for the specific language governing rights and limitations
 * under the License.
 * 
 * @APPLE_LICENSE_HEADER_END@
 */
/*
 * @OSF_COPYRIGHT@
 */
/*
 * HISTORY
 * 
 * Revision 1.1.1.1  1998/09/22 21:05:31  wsanchez
 * Import of Mac OS X kernel (~semeria)
 *
 * Revision 1.1.1.1  1998/03/07 02:25:47  wsanchez
 * Import of OSF Mach kernel (~mburg)
 *
 * Revision 1.2.6.1  1994/09/23  02:37:03  ezf
 * 	change marker to not FREE
 * 	[1994/09/22  21:39:57  ezf]
 *
 * Revision 1.2.2.2  1993/06/09  02:40:30  gm
 * 	Added to OSF/1 R1.3 from NMK15.0.
 * 	[1993/06/02  21:16:11  jeffc]
 * 
 * Revision 1.2  1993/04/19  16:33:51  devrcs
 * 	ansi C conformance changes
 * 	[1993/02/02  18:56:01  david]
 * 
 * Revision 1.1  1992/09/30  02:30:43  robert
 * 	Initial revision
 * 
 * $EndLog$
 */
/* CMU_HIST */
/*
 * Revision 2.1.1.1.2.1  92/03/03  16:21:23  jeffreyh
 * 	Merged up to Trunk
 * 	[92/02/26            jeffreyh]
 * 
 * Revision 2.4  92/02/26  13:10:29  elf
 * 	Added stupid alaises to make i386/fpu.c compile. RVB will fix.
 * 	 
 * 	[92/02/26            elf]
 * 
 * Revision 2.3  92/02/26  12:47:46  elf
 * 	Installed from i386 directory.
 * 	[92/02/26            danner]
 * 
 * 
 * Revision 2.2  92/01/03  20:19:47  dbg
 * 	Move this file to mach/i386.  Add FP_NO..FP_387 codes for
 * 	floating-point processor status.  Error bits in control
 * 	register are masks, not enables.
 * 	[91/10/19            dbg]
 * 
 */
/* CMU_ENDHIST */
/* 
 * Mach Operating System
 * Copyright (c) 1992-1989 Carnegie Mellon University
 * All Rights Reserved.
 * 
 * Permission to use, copy, modify and distribute this software and its
 * documentation is hereby granted, provided that both the copyright
 * notice and this permission notice appear in all copies of the
 * software, derivative works or modified versions, and any portions
 * thereof, and that both notices appear in supporting documentation.
 * 
 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
 * 
 * Carnegie Mellon requests users of this software to return to
 * 
 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
 *  School of Computer Science
 *  Carnegie Mellon University
 *  Pittsburgh PA 15213-3890
 * 
 * any improvements or extensions that they make and grant Carnegie Mellon
 * the rights to redistribute these changes.
 */
/*
 */

#ifndef	_I386_FP_SAVE_H_
#define	_I386_FP_SAVE_H_
/*
 *	Floating point registers and status, as saved
 *	and restored by FP save/restore instructions.
 */
struct i386_fp_save	{
	unsigned short	fp_control;	/* control */
	unsigned short	fp_unused_1;
	unsigned short	fp_status;	/* status */
	unsigned short	fp_unused_2;
	unsigned short	fp_tag;		/* register tags */
	unsigned short	fp_unused_3;
	unsigned int	fp_eip;		/* eip at failed instruction */
	unsigned short	fp_cs;		/* cs at failed instruction */
	unsigned short	fp_opcode;	/* opcode of failed instruction */
	unsigned int	fp_dp;		/* data address */
	unsigned short	fp_ds;		/* data segment */
	unsigned short	fp_unused_4;
};

struct i386_fp_regs {
	unsigned short	fp_reg_word[5][8];
					/* space for 8 80-bit FP registers */
};

/* note when allocating this data structure, it must be 16 byte aligned. */
struct i386_fx_save {
        unsigned short  fx_control;     /* control */
        unsigned short  fx_status;      /* status */
        unsigned char  	fx_tag;         /* register tags */
        unsigned char	fx_bbz1;	/* better be zero when calling fxrtstor */
        unsigned short  fx_opcode;
        unsigned int    fx_eip;         /* eip  instruction */
        unsigned short  fx_cs;          /* cs instruction */
        unsigned short  fx_bbz2;	/* better be zero when calling fxrtstor */ 
        unsigned int    fx_dp;          /* data address */
        unsigned short  fx_ds;          /* data segment */
        unsigned short  fx_bbz3;	/* better be zero when calling fxrtstor */
        unsigned int  	fx_MXCSR;
        unsigned int  	fx_MXCSR_MASK;
        unsigned short  fx_reg_word[8][8];      /* STx/MMx registers */
        unsigned short  fx_XMM_reg[8][8];       /* XMM0-XMM7 */
        unsigned char 	fx_reserved[16*14];     /* reserved by intel for future expansion */
};


/*
 * Control register
 */
#define	FPC_IE		0x0001		/* enable invalid operation
					   exception */
#define FPC_IM		FPC_IE
#define	FPC_DE		0x0002		/* enable denormalized operation
					   exception */
#define FPC_DM		FPC_DE
#define	FPC_ZE		0x0004		/* enable zero-divide exception */
#define FPC_ZM		FPC_ZE
#define	FPC_OE		0x0008		/* enable overflow exception */
#define FPC_OM		FPC_OE
#define	FPC_UE		0x0010		/* enable underflow exception */
#define	FPC_PE		0x0020		/* enable precision exception */
#define	FPC_PC		0x0300		/* precision control: */
#define	FPC_PC_24	0x0000			/* 24 bits */
#define	FPC_PC_53	0x0200			/* 53 bits */
#define	FPC_PC_64	0x0300			/* 64 bits */
#define	FPC_RC		0x0c00		/* rounding control: */
#define	FPC_RC_RN	0x0000			/* round to nearest or even */
#define	FPC_RC_RD	0x0400			/* round down */
#define	FPC_RC_RU	0x0800			/* round up */
#define	FPC_RC_CHOP	0x0c00			/* chop */
#define	FPC_IC		0x1000		/* infinity control (obsolete) */
#define	FPC_IC_PROJ	0x0000			/* projective infinity */
#define	FPC_IC_AFF	0x1000			/* affine infinity (std) */

/*
 * Status register
 */
#define	FPS_IE		0x0001		/* invalid operation */
#define	FPS_DE		0x0002		/* denormalized operand */
#define	FPS_ZE		0x0004		/* divide by zero */
#define	FPS_OE		0x0008		/* overflow */
#define	FPS_UE		0x0010		/* underflow */
#define	FPS_PE		0x0020		/* precision */
#define	FPS_SF		0x0040		/* stack flag */
#define	FPS_ES		0x0080		/* error summary */
#define	FPS_C0		0x0100		/* condition code bit 0 */
#define	FPS_C1		0x0200		/* condition code bit 1 */
#define	FPS_C2		0x0400		/* condition code bit 2 */
#define	FPS_TOS		0x3800		/* top-of-stack pointer */
#define	FPS_TOS_SHIFT	11
#define	FPS_C3		0x4000		/* condition code bit 3 */
#define	FPS_BUSY	0x8000		/* FPU busy */

/*
 * Kind of floating-point support provided by kernel.
 */
#define	FP_NO		0		/* no floating point */
#define	FP_SOFT		1		/* software FP emulator */
#define	FP_287		2		/* 80287 */
#define	FP_387		3		/* 80387 or 80486 */
#define FP_FXSR		4		/* Fast save/restore SIMD Extension */

#endif	/* _I386_FP_SAVE_H_ */
Commit	Line	Data
1c79356b A	1	/*
	2	* Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
	3	*
	4	* @APPLE_LICENSE_HEADER_START@
	5	*
e5568f75 A	6	* The contents of this file constitute Original Code as defined in and
	7	* are subject to the Apple Public Source License Version 1.1 (the
	8	* "License"). You may not use this file except in compliance with the
	9	* License. Please obtain a copy of the License at
	10	* http://www.apple.com/publicsource and read it before using this file.
1c79356b	11	*
e5568f75 A	12	* This Original Code and all software distributed under the License are
e5568f75 A	13	* distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
1c79356b A	14	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
1c79356b A	15	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
e5568f75 A	16	* FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
	17	* License for the specific language governing rights and limitations
	18	* under the License.
1c79356b A	19	*
	20	* @APPLE_LICENSE_HEADER_END@
	21	*/
	22	/*
	23	* @OSF_COPYRIGHT@
	24	*/
	25	/*
	26	* HISTORY
	27	*
	28	* Revision 1.1.1.1 1998/09/22 21:05:31 wsanchez
	29	* Import of Mac OS X kernel (~semeria)
	30	*
	31	* Revision 1.1.1.1 1998/03/07 02:25:47 wsanchez
	32	* Import of OSF Mach kernel (~mburg)
	33	*
	34	* Revision 1.2.6.1 1994/09/23 02:37:03 ezf
	35	* change marker to not FREE
	36	* [1994/09/22 21:39:57 ezf]
	37	*
	38	* Revision 1.2.2.2 1993/06/09 02:40:30 gm
	39	* Added to OSF/1 R1.3 from NMK15.0.
	40	* [1993/06/02 21:16:11 jeffc]
	41	*
	42	* Revision 1.2 1993/04/19 16:33:51 devrcs
	43	* ansi C conformance changes
	44	* [1993/02/02 18:56:01 david]
	45	*
	46	* Revision 1.1 1992/09/30 02:30:43 robert
	47	* Initial revision
	48	*
	49	* $EndLog$
	50	*/
	51	/* CMU_HIST */
	52	/*
	53	* Revision 2.1.1.1.2.1 92/03/03 16:21:23 jeffreyh
	54	* Merged up to Trunk
	55	* [92/02/26 jeffreyh]
	56	*
	57	* Revision 2.4 92/02/26 13:10:29 elf
	58	* Added stupid alaises to make i386/fpu.c compile. RVB will fix.
	59	*
	60	* [92/02/26 elf]
	61	*
	62	* Revision 2.3 92/02/26 12:47:46 elf
	63	* Installed from i386 directory.
	64	* [92/02/26 danner]
	65	*
	66	*
	67	* Revision 2.2 92/01/03 20:19:47 dbg
	68	* Move this file to mach/i386. Add FP_NO..FP_387 codes for
	69	* floating-point processor status. Error bits in control
	70	* register are masks, not enables.
	71	* [91/10/19 dbg]
	72	*
	73	*/
	74	/* CMU_ENDHIST */
	75	/*
	76	* Mach Operating System
	77	* Copyright (c) 1992-1989 Carnegie Mellon University
	78	* All Rights Reserved.
	79	*
	80	* Permission to use, copy, modify and distribute this software and its
	81	* documentation is hereby granted, provided that both the copyright
	82	* notice and this permission notice appear in all copies of the
83	* software, derivative works or modified versions, and any portions
84	* thereof, and that both notices appear in supporting documentation.
85	*
86	* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
87	* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
88	* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
89	*
90	* Carnegie Mellon requests users of this software to return to
91	*
92	* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
93	* School of Computer Science
94	* Carnegie Mellon University
95	* Pittsburgh PA 15213-3890
96	*
97	* any improvements or extensions that they make and grant Carnegie Mellon
98	* the rights to redistribute these changes.
99	*/
100	/*
101	*/
102
103	#ifndef _I386_FP_SAVE_H_
104	#define _I386_FP_SAVE_H_
105	/*
106	* Floating point registers and status, as saved
107	* and restored by FP save/restore instructions.
108	*/
109	struct i386_fp_save {
110	unsigned short fp_control; /* control */
111	unsigned short fp_unused_1;
112	unsigned short fp_status; /* status */
113	unsigned short fp_unused_2;
114	unsigned short fp_tag; /* register tags */
115	unsigned short fp_unused_3;
116	unsigned int fp_eip; /* eip at failed instruction */
117	unsigned short fp_cs; /* cs at failed instruction */
118	unsigned short fp_opcode; /* opcode of failed instruction */
119	unsigned int fp_dp; /* data address */
120	unsigned short fp_ds; /* data segment */
121	unsigned short fp_unused_4;
122	};
123
124	struct i386_fp_regs {
125	unsigned short fp_reg_word[5][8];
126	/* space for 8 80-bit FP registers */
127	};
128
55e303ae A	129	/* note when allocating this data structure, it must be 16 byte aligned. */
	130	struct i386_fx_save {
	131	unsigned short fx_control; /* control */
	132	unsigned short fx_status; /* status */
	133	unsigned char fx_tag; /* register tags */
	134	unsigned char fx_bbz1; /* better be zero when calling fxrtstor */
	135	unsigned short fx_opcode;
	136	unsigned int fx_eip; /* eip instruction */
	137	unsigned short fx_cs; /* cs instruction */
	138	unsigned short fx_bbz2; /* better be zero when calling fxrtstor */
	139	unsigned int fx_dp; /* data address */
	140	unsigned short fx_ds; /* data segment */
	141	unsigned short fx_bbz3; /* better be zero when calling fxrtstor */
	142	unsigned int fx_MXCSR;
	143	unsigned int fx_MXCSR_MASK;
	144	unsigned short fx_reg_word[8][8]; /* STx/MMx registers */
	145	unsigned short fx_XMM_reg[8][8]; /* XMM0-XMM7 */
	146	unsigned char fx_reserved[1614]; / reserved by intel for future expansion */
	147	};
	148
	149
1c79356b A	150	/*
	151	* Control register
	152	*/
	153	#define FPC_IE 0x0001 /* enable invalid operation
	154	exception */
	155	#define FPC_IM FPC_IE
	156	#define FPC_DE 0x0002 /* enable denormalized operation
	157	exception */
	158	#define FPC_DM FPC_DE
	159	#define FPC_ZE 0x0004 /* enable zero-divide exception */
	160	#define FPC_ZM FPC_ZE
	161	#define FPC_OE 0x0008 /* enable overflow exception */
	162	#define FPC_OM FPC_OE
	163	#define FPC_UE 0x0010 /* enable underflow exception */
	164	#define FPC_PE 0x0020 /* enable precision exception */
	165	#define FPC_PC 0x0300 /* precision control: */
	166	#define FPC_PC_24 0x0000 /* 24 bits */
	167	#define FPC_PC_53 0x0200 /* 53 bits */
	168	#define FPC_PC_64 0x0300 /* 64 bits */
	169	#define FPC_RC 0x0c00 /* rounding control: */
	170	#define FPC_RC_RN 0x0000 /* round to nearest or even */
	171	#define FPC_RC_RD 0x0400 /* round down */
	172	#define FPC_RC_RU 0x0800 /* round up */
	173	#define FPC_RC_CHOP 0x0c00 /* chop */
	174	#define FPC_IC 0x1000 /* infinity control (obsolete) */
	175	#define FPC_IC_PROJ 0x0000 /* projective infinity */
	176	#define FPC_IC_AFF 0x1000 /* affine infinity (std) */
	177
	178	/*
	179	* Status register
	180	*/
	181	#define FPS_IE 0x0001 /* invalid operation */
	182	#define FPS_DE 0x0002 /* denormalized operand */
	183	#define FPS_ZE 0x0004 /* divide by zero */
	184	#define FPS_OE 0x0008 /* overflow */
	185	#define FPS_UE 0x0010 /* underflow */
	186	#define FPS_PE 0x0020 /* precision */
	187	#define FPS_SF 0x0040 /* stack flag */
	188	#define FPS_ES 0x0080 /* error summary */
	189	#define FPS_C0 0x0100 /* condition code bit 0 */
	190	#define FPS_C1 0x0200 /* condition code bit 1 */
	191	#define FPS_C2 0x0400 /* condition code bit 2 */
	192	#define FPS_TOS 0x3800 /* top-of-stack pointer */
	193	#define FPS_TOS_SHIFT 11
	194	#define FPS_C3 0x4000 /* condition code bit 3 */
	195	#define FPS_BUSY 0x8000 /* FPU busy */
	196
	197	/*
	198	* Kind of floating-point support provided by kernel.
	199	*/
	200	#define FP_NO 0 /* no floating point */
	201	#define FP_SOFT 1 /* software FP emulator */
	202	#define FP_287 2 /* 80287 */
	203	#define FP_387 3 /* 80387 or 80486 */
55e303ae	204	#define FP_FXSR 4 /* Fast save/restore SIMD Extension */
1c79356b A	205
1c79356b A	206	#endif /* _I386_FP_SAVE_H_ */