[apple/xnu.git] / osfmk / mach / ppc / processor_info.h

/*
 * Copyright (c) 2000-2005 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_LICENSE_HEADER_START@
 * 
 * The contents of this file constitute Original Code as defined in and
 * are subject to the Apple Public Source License Version 1.1 (the
 * "License").  You may not use this file except in compliance with the
 * License.  Please obtain a copy of the License at
 * http://www.apple.com/publicsource and read it before using this file.
 * 
 * This Original Code and all software distributed under the License are
 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
 * License for the specific language governing rights and limitations
 * under the License.
 * 
 * @APPLE_LICENSE_HEADER_END@
 */

/*
 *	File:	mach/ppc/processor_info.h
 *
 *	Data structure definitions for ppc specific processor control
 */

#ifndef	_MACH_PPC_PROCESSOR_INFO_H_
#define _MACH_PPC_PROCESSOR_INFO_H_

#include <mach/machine.h>
#include <mach/message.h>

#ifdef	PRIVATE

/* processor_control command operations */
#define PROCESSOR_PM_SET_REGS     1     /* Set Performance Monitor Registers  */
#define PROCESSOR_PM_SET_MMCR     2     /* Set Monitor Mode Controls Registers  */
#define PROCESSOR_PM_CLR_PMC      3     /* Clear Performance Monitor Counter Registers */

/* 
 * Performance Monitor Register structures
 *
 * XXX - These have not been updated for ppc64.
 */

typedef union {
	unsigned int word;
	struct {
	        unsigned int dis	: 1;
		unsigned int dp 	: 1;
		unsigned int du 	: 1;
	        unsigned int dms	: 1;
	        unsigned int dmr	: 1;
	        unsigned int reserved3	: 1;        /* enint         */
	        unsigned int reserved4	: 1;        /* discount      */
	        unsigned int reserved5	: 2;        /* rtcselect     */
	        unsigned int reserved6	: 1;        /* intonbittrans */
	        unsigned int threshold	: 6;
	        unsigned int reserved7	: 1;        /* pmc1intcontrol */
	        unsigned int reserved8	: 1;        /* pmcintcontrol  */
	        unsigned int reserved9	: 1;        /* pmctrigger     */
	        unsigned int pmc1select	: 7;
	        unsigned int pmc2select	: 6;
	}bits;
}mmcr0_t;

typedef union {
	unsigned int word;
	struct {
	        unsigned int pmc3select	: 5;
	        unsigned int pmc4select	: 5;
	        unsigned int reserved	: 22;
	}bits;
}mmcr1_t;

typedef union {
	unsigned int word;
	struct {
	        unsigned int threshmult	 : 1;
	        unsigned int reserved	 : 31;
	}bits;
}mmcr2_t;

typedef union {
	unsigned int word;
	struct {
	        unsigned int ov : 1;        /* overflow value */
	        unsigned int cv : 31;       /* countervalue */
	}bits;
}pmcn_t;


/* Processor Performance Monitor Registers definitions */

struct processor_pm_regs {
      union {
	mmcr0_t mmcr0;
        mmcr1_t mmcr1;
        mmcr2_t mmcr2;
      }u;
      pmcn_t pmc[2];
};

typedef struct processor_pm_regs processor_pm_regs_data_t;
typedef struct processor_pm_regs *processor_pm_regs_t;
#define PROCESSOR_PM_REGS_COUNT ((mach_msg_type_number_t) \
        (sizeof(processor_pm_regs_data_t) / sizeof (unsigned int)))

#define PROCESSOR_PM_REGS_COUNT_POWERPC_750 \
            (PROCESSOR_PM_REGS_COUNT * 2 )

#define PROCESSOR_PM_REGS_COUNT_POWERPC_7400 \
            (PROCESSOR_PM_REGS_COUNT * 3 )

union processor_control_data {
        processor_pm_regs_data_t cmd_pm_regs[3];
};

struct processor_control_cmd {
    integer_t      cmd_op;
    cpu_type_t     cmd_cpu_type;
    cpu_subtype_t  cmd_cpu_subtype;
    union processor_control_data u;
};

typedef struct processor_control_cmd   processor_control_cmd_data_t;
typedef struct processor_control_cmd   *processor_control_cmd_t;
#define cmd_pm_regs u.cmd_pm_regs;
#define cmd_pm_ctls u.cmd_pm_ctls;

#define PROCESSOR_CONTROL_CMD_COUNT ((mach_msg_type_number_t) \
    (((sizeof(processor_control_cmd_data_t)) - \
      (sizeof(union processor_control_data))) / sizeof (integer_t)))

     /* x should be a processor_pm_regs_t */
#define PERFMON_MMCR0(x)    ((x)[0].u.mmcr0.word)
#define PERFMON_PMC1(x)     ((x)[0].pmc[0].word)
#define PERFMON_PMC2(x)     ((x)[0].pmc[1].word)
#define PERFMON_MMCR1(x)    ((x)[1].u.mmcr1.word)
#define PERFMON_PMC3(x)     ((x)[1].pmc[0].word)
#define PERFMON_PMC4(x)     ((x)[1].pmc[1].word)
#define PERFMON_MMCR2(x)    ((x)[2].u.mmcr2.word)

#define PERFMON_DIS(x)           ((x)[0].u.mmcr0.bits.dis)
#define PERFMON_DP(x)            ((x)[0].u.mmcr0.bits.dp)
#define PERFMON_DU(x)            ((x)[0].u.mmcr0.bits.du)
#define PERFMON_DMS(x)           ((x)[0].u.mmcr0.bits.dms)
#define PERFMON_DMR(x)           ((x)[0].u.mmcr0.bits.dmr)
#define PERFMON_THRESHOLD(x)     ((x)[0].u.mmcr0.bits.threshold)
#define PERFMON_PMC1SELECT(x)    ((x)[0].u.mmcr0.bits.pmc1select)
#define PERFMON_PMC2SELECT(x)    ((x)[0].u.mmcr0.bits.pmc2select)
#define PERFMON_PMC3SELECT(x)    ((x)[1].u.mmcr1.bits.pmc3select)
#define PERFMON_PMC4SELECT(x)    ((x)[1].u.mmcr1.bits.pmc4select)
#define PERFMON_THRESHMULT(x)    ((x)[2].u.mmcr2.bits.threshmult)
#define PERFMON_PMC1_CV(x)       ((x)[0].u.pmc[0].bits.cv)
#define PERFMON_PMC2_CV(x)       ((x)[0].u.pmc[1].bits.cv)
#define PERFMON_PMC3_CV(x)       ((x)[1].u.pmc[0].bits.cv)
#define PERFMON_PMC4_CV(x)       ((x)[1].u.pmc[1].bits.cv)

typedef unsigned int processor_temperature_data_t;
typedef unsigned int *processor_temperature_t;

#define PROCESSOR_TEMPERATURE_COUNT 1

#endif	/* PRIVATE */

#endif	/* _MACH_PPC_PROCESSOR_INFO_H_ */
Commit	Line	Data
1c79356b	1	/*
91447636	2	* Copyright (c) 2000-2005 Apple Computer, Inc. All rights reserved.
1c79356b A	3	*
	4	* @APPLE_LICENSE_HEADER_START@
	5	*
e5568f75 A	6	* The contents of this file constitute Original Code as defined in and
	7	* are subject to the Apple Public Source License Version 1.1 (the
	8	* "License"). You may not use this file except in compliance with the
	9	* License. Please obtain a copy of the License at
	10	* http://www.apple.com/publicsource and read it before using this file.
1c79356b	11	*
e5568f75 A	12	* This Original Code and all software distributed under the License are
e5568f75 A	13	* distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
1c79356b A	14	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
1c79356b A	15	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
e5568f75 A	16	* FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
	17	* License for the specific language governing rights and limitations
	18	* under the License.
1c79356b A	19	*
	20	* @APPLE_LICENSE_HEADER_END@
	21	*/
91447636	22
1c79356b A	23	/*
	24	* File: mach/ppc/processor_info.h
	25	*
	26	* Data structure definitions for ppc specific processor control
	27	*/
	28
1c79356b A	29	#ifndef _MACH_PPC_PROCESSOR_INFO_H_
	30	#define _MACH_PPC_PROCESSOR_INFO_H_
	31
	32	#include <mach/machine.h>
91447636 A	33	#include <mach/message.h>
	34
	35	#ifdef PRIVATE
1c79356b A	36
	37	/* processor_control command operations */
	38	#define PROCESSOR_PM_SET_REGS 1 /* Set Performance Monitor Registers */
	39	#define PROCESSOR_PM_SET_MMCR 2 /* Set Monitor Mode Controls Registers */
	40	#define PROCESSOR_PM_CLR_PMC 3 /* Clear Performance Monitor Counter Registers */
	41
	42	/*
	43	* Performance Monitor Register structures
91447636 A	44	*
91447636 A	45	* XXX - These have not been updated for ppc64.
1c79356b A	46	*/
	47
	48	typedef union {
	49	unsigned int word;
	50	struct {
	51	unsigned int dis : 1;
	52	unsigned int dp : 1;
	53	unsigned int du : 1;
	54	unsigned int dms : 1;
	55	unsigned int dmr : 1;
	56	unsigned int reserved3 : 1; /* enint */
	57	unsigned int reserved4 : 1; /* discount */
	58	unsigned int reserved5 : 2; /* rtcselect */
	59	unsigned int reserved6 : 1; /* intonbittrans */
	60	unsigned int threshold : 6;
	61	unsigned int reserved7 : 1; /* pmc1intcontrol */
	62	unsigned int reserved8 : 1; /* pmcintcontrol */
	63	unsigned int reserved9 : 1; /* pmctrigger */
	64	unsigned int pmc1select : 7;
	65	unsigned int pmc2select : 6;
	66	}bits;
	67	}mmcr0_t;
	68
	69	typedef union {
	70	unsigned int word;
	71	struct {
	72	unsigned int pmc3select : 5;
	73	unsigned int pmc4select : 5;
	74	unsigned int reserved : 22;
	75	}bits;
	76	}mmcr1_t;
	77
	78	typedef union {
	79	unsigned int word;
	80	struct {
	81	unsigned int threshmult : 1;
	82	unsigned int reserved : 31;
	83	}bits;
	84	}mmcr2_t;
	85
	86	typedef union {
	87	unsigned int word;
	88	struct {
	89	unsigned int ov : 1; /* overflow value */
	90	unsigned int cv : 31; /* countervalue */
	91	}bits;
	92	}pmcn_t;
	93
	94
	95
	96	/* Processor Performance Monitor Registers definitions */
	97
	98	struct processor_pm_regs {
	99	union {
	100	mmcr0_t mmcr0;
	101	mmcr1_t mmcr1;
	102	mmcr2_t mmcr2;
	103	}u;
	104	pmcn_t pmc[2];
	105	};
	106
	107	typedef struct processor_pm_regs processor_pm_regs_data_t;
	108	typedef struct processor_pm_regs *processor_pm_regs_t;
91447636 A	109	#define PROCESSOR_PM_REGS_COUNT ((mach_msg_type_number_t) \
91447636 A	110	(sizeof(processor_pm_regs_data_t) / sizeof (unsigned int)))
1c79356b	111
1c79356b A	112	#define PROCESSOR_PM_REGS_COUNT_POWERPC_750 \
	113	(PROCESSOR_PM_REGS_COUNT * 2 )
	114
	115	#define PROCESSOR_PM_REGS_COUNT_POWERPC_7400 \
	116	(PROCESSOR_PM_REGS_COUNT * 3 )
	117
1c79356b A	118	union processor_control_data {
	119	processor_pm_regs_data_t cmd_pm_regs[3];
	120	};
	121
	122	struct processor_control_cmd {
	123	integer_t cmd_op;
	124	cpu_type_t cmd_cpu_type;
	125	cpu_subtype_t cmd_cpu_subtype;
	126	union processor_control_data u;
	127	};
	128
	129	typedef struct processor_control_cmd processor_control_cmd_data_t;
	130	typedef struct processor_control_cmd *processor_control_cmd_t;
	131	#define cmd_pm_regs u.cmd_pm_regs;
	132	#define cmd_pm_ctls u.cmd_pm_ctls;
	133
91447636	134	#define PROCESSOR_CONTROL_CMD_COUNT ((mach_msg_type_number_t) \
1c79356b	135	(((sizeof(processor_control_cmd_data_t)) - \
91447636	136	(sizeof(union processor_control_data))) / sizeof (integer_t)))
1c79356b A	137
	138	/* x should be a processor_pm_regs_t */
	139	#define PERFMON_MMCR0(x) ((x)[0].u.mmcr0.word)
	140	#define PERFMON_PMC1(x) ((x)[0].pmc[0].word)
	141	#define PERFMON_PMC2(x) ((x)[0].pmc[1].word)
	142	#define PERFMON_MMCR1(x) ((x)[1].u.mmcr1.word)
	143	#define PERFMON_PMC3(x) ((x)[1].pmc[0].word)
	144	#define PERFMON_PMC4(x) ((x)[1].pmc[1].word)
	145	#define PERFMON_MMCR2(x) ((x)[2].u.mmcr2.word)
	146
	147	#define PERFMON_DIS(x) ((x)[0].u.mmcr0.bits.dis)
	148	#define PERFMON_DP(x) ((x)[0].u.mmcr0.bits.dp)
	149	#define PERFMON_DU(x) ((x)[0].u.mmcr0.bits.du)
	150	#define PERFMON_DMS(x) ((x)[0].u.mmcr0.bits.dms)
	151	#define PERFMON_DMR(x) ((x)[0].u.mmcr0.bits.dmr)
	152	#define PERFMON_THRESHOLD(x) ((x)[0].u.mmcr0.bits.threshold)
	153	#define PERFMON_PMC1SELECT(x) ((x)[0].u.mmcr0.bits.pmc1select)
	154	#define PERFMON_PMC2SELECT(x) ((x)[0].u.mmcr0.bits.pmc2select)
	155	#define PERFMON_PMC3SELECT(x) ((x)[1].u.mmcr1.bits.pmc3select)
	156	#define PERFMON_PMC4SELECT(x) ((x)[1].u.mmcr1.bits.pmc4select)
	157	#define PERFMON_THRESHMULT(x) ((x)[2].u.mmcr2.bits.threshmult)
	158	#define PERFMON_PMC1_CV(x) ((x)[0].u.pmc[0].bits.cv)
	159	#define PERFMON_PMC2_CV(x) ((x)[0].u.pmc[1].bits.cv)
	160	#define PERFMON_PMC3_CV(x) ((x)[1].u.pmc[0].bits.cv)
	161	#define PERFMON_PMC4_CV(x) ((x)[1].u.pmc[1].bits.cv)
	162
91447636 A	163	typedef unsigned int processor_temperature_data_t;
91447636 A	164	typedef unsigned int *processor_temperature_t;
1c79356b	165
91447636 A	166	#define PROCESSOR_TEMPERATURE_COUNT 1
	167
	168	#endif /* PRIVATE */
	169
	170	#endif /* _MACH_PPC_PROCESSOR_INFO_H_ */