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55e303ae 1/*
91447636 2 * Copyright (c) 2003-2004 Apple Computer, Inc. All rights reserved.
55e303ae 3 *
8f6c56a5 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
8ad349bb 5 *
8f6c56a5
A		 6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
8ad349bb 24 * limitations under the License.
8f6c56a5
A		 25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
55e303ae 27 */
91447636
A		 28#include <mach/mach_types.h>
29#include <mach/mach_host.h>
30
31#include <kern/host.h>
32#include <kern/processor.h>
55e303ae 33
89b3af67
A		 34#include <chud/chud_xnu.h>
35#include <chud/ppc/chud_spr.h>
36#include <chud/ppc/chud_cpu_asm.h>
55e303ae
A		 37#include <ppc/machine_routines.h>
38#include <ppc/exception.h>
91447636 39#include <ppc/hw_perfmon.h>
55e303ae
A		 40#include <ppc/Diagnostics.h>
41
91447636
A		 42// the macros in proc_reg.h fail with "expression must be absolute"
43
44#undef mtsprg
45#undef mfsprg
46#define mtsprg(n, reg) __asm__ volatile("mtsprg " # n ", %0" : : "r" (reg))
47#define mfsprg(reg, n) __asm__ volatile("mfsprg %0, " # n : "=r" (reg))
48
49#undef mtspr
50#undef mfspr
51#define mtspr(spr, reg) __asm__ volatile ("mtspr %0, %1" : : "n" (spr), "r" (reg))
52#define mfspr(reg, spr) __asm__ volatile("mfspr %0, %1" : "=r" (reg) : "n" (spr));
53
54#undef mtsr
55#undef mfsr
56#define mtsr(sr, reg) __asm__ volatile("sync" "@" "mtsr sr%0, %1 " "@" "isync" : : "i" (sr), "r" (reg));
57#define mfsr(reg, sr) __asm__ volatile("mfsr %0, sr%1" : "=r" (reg) : "i" (sr));
58
91447636
A		 59#pragma mark **** cpu enable/disable ****
60
61extern kern_return_t processor_start(processor_t processor); // osfmk/kern/processor.c
62extern kern_return_t processor_exit(processor_t processor); // osfmk/kern/processor.c
63
55e303ae
A		 64__private_extern__
65kern_return_t chudxnu_enable_cpu(int cpu, boolean_t enable)
66{
91447636 67 chudxnu_unbind_thread(current_thread());
55e303ae
A		 68
69 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
70 return KERN_FAILURE;
71 }
72
91447636
A		 73 if((PerProcTable[cpu].ppe_vaddr != (struct per_proc_info *)NULL)
74 && cpu != master_cpu) {
75 processor_t processor = cpu_to_processor(cpu);
76
55e303ae 77 if(enable) {
91447636 78 return processor_start(processor);
55e303ae 79 } else {
91447636 80 return processor_exit(processor);
55e303ae
A		 81 }
82 }
83 return KERN_FAILURE;
84}
85
91447636
A		 86#pragma mark **** nap ****
87
55e303ae
A		 88__private_extern__
89kern_return_t chudxnu_enable_cpu_nap(int cpu, boolean_t enable)
90{
91 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
92 return KERN_FAILURE;
93 }
94
91447636 95 if(PerProcTable[cpu].ppe_vaddr != (struct per_proc_info *)NULL) {
55e303ae
A		 96 ml_enable_nap(cpu, enable);
97 return KERN_SUCCESS;
98 }
99
100 return KERN_FAILURE;
101}
102
103__private_extern__
104boolean_t chudxnu_cpu_nap_enabled(int cpu)
105{
106 boolean_t prev;
107
108 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
109 cpu = 0;
110 }
111
112 prev = ml_enable_nap(cpu, TRUE);
113 ml_enable_nap(cpu, prev);
114
115 return prev;
116}
117
91447636
A		 118#pragma mark **** shadowed spr ****
119
55e303ae
A		 120__private_extern__
121kern_return_t chudxnu_set_shadowed_spr(int cpu, int spr, uint32_t val)
122{
91447636 123 cpu_subtype_t target_cpu_subtype;
55e303ae
A		 124 uint32_t available;
125 kern_return_t retval = KERN_FAILURE;
91447636
A		 126 struct per_proc_info *per_proc;
127 boolean_t didBind = FALSE;
55e303ae 128
91447636 129 if(cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
55e303ae
A		 130 return KERN_FAILURE;
131 }
132
91447636
A		 133 if(cpu<0) { // cpu<0 means don't bind (current cpu)
134 cpu = chudxnu_cpu_number();
135 didBind = FALSE;
136 } else {
137 chudxnu_bind_thread(current_thread(), cpu);
138 didBind = TRUE;
139 }
55e303ae 140
91447636
A		 141 per_proc = PerProcTable[cpu].ppe_vaddr;
142 available = per_proc->pf.Available;
143 target_cpu_subtype = per_proc->cpu_subtype;
55e303ae
A		 144
145 if(spr==chud_750_l2cr) {
91447636 146 switch(target_cpu_subtype) {
55e303ae
A		 147 case CPU_SUBTYPE_POWERPC_750:
148 case CPU_SUBTYPE_POWERPC_7400:
149 case CPU_SUBTYPE_POWERPC_7450:
150 if(available & pfL2) {
151// int enable = (val & 0x80000000) ? TRUE : FALSE;
152// if(enable) {
91447636 153// per_proc->pf.l2cr = val;
55e303ae 154// } else {
91447636 155// per_proc->pf.l2cr = 0;
55e303ae 156// }
91447636 157 per_proc->pf.l2cr = val;
55e303ae 158 cacheInit();
91447636 159 // mtspr(l2cr, per_proc->pf.l2cr); // XXXXXXX why is this necessary? XXXXXXX
55e303ae
A		 160 retval = KERN_SUCCESS;
161 } else {
162 retval = KERN_FAILURE;
163 }
164 break;
165 default:
166 retval = KERN_INVALID_ARGUMENT;
167 break;
168 }
169 }
170 else if(spr==chud_7450_l3cr) {
91447636 171 switch(target_cpu_subtype) {
55e303ae
A		 172 case CPU_SUBTYPE_POWERPC_7450:
173 if(available & pfL3) {
174 int enable = (val & 0x80000000) ? TRUE : FALSE;
175 if(enable) {
91447636 176 per_proc->pf.l3cr = val;
55e303ae 177 } else {
91447636 178 per_proc->pf.l3cr = 0;
55e303ae
A		 179 }
180 cacheInit();
181 retval = KERN_SUCCESS;
182 } else {
183 retval = KERN_FAILURE;
184 }
185 break;
186 default:
187 retval = KERN_INVALID_ARGUMENT;
188 break;
189 }
190 }
191 else if(spr==chud_750_hid0) {
91447636 192 switch(target_cpu_subtype) {
55e303ae
A		 193 case CPU_SUBTYPE_POWERPC_750:
194 cacheInit();
195 cacheDisable(); /* disable caches */
91447636
A		 196 mtspr(chud_750_hid0, val);
197 per_proc->pf.pfHID0 = val;
55e303ae
A		 198 cacheInit(); /* reenable caches */
199 retval = KERN_SUCCESS;
200 break;
201 case CPU_SUBTYPE_POWERPC_7400:
202 case CPU_SUBTYPE_POWERPC_7450:
91447636
A		 203 mtspr(chud_750_hid0, val);
204 per_proc->pf.pfHID0 = val;
55e303ae
A		 205 retval = KERN_SUCCESS;
206 break;
207 default:
208 retval = KERN_INVALID_ARGUMENT;
209 break;
210 }
211 }
212 else if(spr==chud_750_hid1) {
91447636 213 switch(target_cpu_subtype) {
55e303ae
A		 214 case CPU_SUBTYPE_POWERPC_750:
215 case CPU_SUBTYPE_POWERPC_7400:
216 case CPU_SUBTYPE_POWERPC_7450:
91447636
A		 217 mtspr(chud_750_hid1, val);
218 per_proc->pf.pfHID1 = val;
55e303ae
A		 219 retval = KERN_SUCCESS;
220 break;
221 default:
222 retval = KERN_INVALID_ARGUMENT;
223 break;
224 }
225 }
91447636
A		 226 else if(spr==chud_750fx_hid2 && target_cpu_subtype==CPU_SUBTYPE_POWERPC_750) {
227 mtspr(chud_750fx_hid2, val);
228 per_proc->pf.pfHID2 = val;
55e303ae
A		 229 retval = KERN_SUCCESS;
230 }
91447636
A		 231 else if(spr==chud_7400_msscr0 && (target_cpu_subtype==CPU_SUBTYPE_POWERPC_7400 || target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450)) {
232 mtspr(chud_7400_msscr0, val);
233 per_proc->pf.pfMSSCR0 = val;
55e303ae
A		 234 retval = KERN_SUCCESS;
235 }
91447636
A		 236 else if(spr==chud_7400_msscr1 && (target_cpu_subtype==CPU_SUBTYPE_POWERPC_7400 || target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450)) { // called msssr0 on 7450
237 mtspr(chud_7400_msscr1, val);
238 per_proc->pf.pfMSSCR1 = val;
55e303ae
A		 239 retval = KERN_SUCCESS;
240 }
91447636
A		 241 else if(spr==chud_7450_ldstcr && target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450) {
242 mtspr(chud_7450_ldstcr, val);
243 per_proc->pf.pfLDSTCR = val;
55e303ae
A		 244 retval = KERN_SUCCESS;
245 }
91447636
A		 246 else if(spr==chud_7450_ictrl && target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450) {
247 mtspr(chud_7450_ictrl, val);
248 per_proc->pf.pfICTRL = val;
55e303ae
A		 249 retval = KERN_SUCCESS;
250 } else {
251 retval = KERN_INVALID_ARGUMENT;
252 }
253
91447636
A		 254 if(didBind) {
255 chudxnu_unbind_thread(current_thread());
256 }
257
55e303ae
A		 258 return retval;
259}
260
261__private_extern__
262kern_return_t chudxnu_set_shadowed_spr64(int cpu, int spr, uint64_t val)
263{
91447636 264 cpu_subtype_t target_cpu_subtype;
55e303ae 265 kern_return_t retval = KERN_FAILURE;
91447636
A		 266 struct per_proc_info *per_proc;
267 boolean_t didBind = FALSE;
55e303ae 268
91447636 269 if(cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
55e303ae
A		 270 return KERN_FAILURE;
271 }
272
91447636
A		 273 if(cpu<0) { // cpu<0 means don't bind (current cpu)
274 cpu = chudxnu_cpu_number();
275 didBind = FALSE;
276 } else {
277 chudxnu_bind_thread(current_thread(), cpu);
278 didBind = TRUE;
279 }
55e303ae 280
91447636
A		 281 per_proc = PerProcTable[cpu].ppe_vaddr;
282 target_cpu_subtype = per_proc->cpu_subtype;
55e303ae
A		 283
284 if(spr==chud_970_hid0) {
91447636 285 switch(target_cpu_subtype) {
55e303ae 286 case CPU_SUBTYPE_POWERPC_970:
91447636
A		 287 mtspr64(chud_970_hid0, &val);
288 per_proc->pf.pfHID0 = val;
55e303ae
A		 289 retval = KERN_SUCCESS;
290 break;
291 default:
292 retval = KERN_INVALID_ARGUMENT;
293 break;
294 }
295 }
296 else if(spr==chud_970_hid1) {
91447636 297 switch(target_cpu_subtype) {
55e303ae 298 case CPU_SUBTYPE_POWERPC_970:
91447636
A		 299 mtspr64(chud_970_hid1, &val);
300 per_proc->pf.pfHID1 = val;
55e303ae
A		 301 retval = KERN_SUCCESS;
302 break;
303 default:
304 retval = KERN_INVALID_ARGUMENT;
305 break;
306 }
307 }
308 else if(spr==chud_970_hid4) {
91447636 309 switch(target_cpu_subtype) {
55e303ae 310 case CPU_SUBTYPE_POWERPC_970:
91447636
A		 311 mtspr64(chud_970_hid4, &val);
312 per_proc->pf.pfHID4 = val;
55e303ae
A		 313 retval = KERN_SUCCESS;
314 break;
315 default:
316 retval = KERN_INVALID_ARGUMENT;
317 break;
318 }
319 }
320 else if(spr==chud_970_hid5) {
91447636 321 switch(target_cpu_subtype) {
55e303ae 322 case CPU_SUBTYPE_POWERPC_970:
91447636
A		 323 mtspr64(chud_970_hid5, &val);
324 per_proc->pf.pfHID5 = val;
55e303ae
A		 325 retval = KERN_SUCCESS;
326 break;
327 default:
328 retval = KERN_INVALID_ARGUMENT;
329 break;
330 }
331 } else {
332 retval = KERN_INVALID_ARGUMENT;
333 }
334
91447636
A		 335 if(didBind) {
336 chudxnu_unbind_thread(current_thread());
337 }
55e303ae
A		 338
339 return retval;
340}
341
342__private_extern__
343uint32_t chudxnu_get_orig_cpu_l2cr(int cpu)
344{
345 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
346 cpu = 0;
347 }
91447636 348 return PerProcTable[cpu].ppe_vaddr->pf.l2crOriginal;
55e303ae
A		 349}
350
351__private_extern__
352uint32_t chudxnu_get_orig_cpu_l3cr(int cpu)
353{
354 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
355 cpu = 0;
356 }
91447636
A		 357 return PerProcTable[cpu].ppe_vaddr->pf.l3crOriginal;
358}
359
360#pragma mark **** spr ****
361
362__private_extern__
363kern_return_t chudxnu_read_spr(int cpu, int spr, uint32_t *val_p)
364{
365 kern_return_t retval = KERN_SUCCESS;
366 boolean_t oldlevel;
367 uint32_t val = 0xFFFFFFFF;
368
369 /* bind to requested CPU */
370 if(cpu>=0) { // cpu<0 means don't bind
371 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
372 return KERN_INVALID_ARGUMENT;
373 }
374 }
375
376 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
377
378 do {
379 /* PPC SPRs - 32-bit and 64-bit implementations */
380 if(spr==chud_ppc_srr0) { mfspr(val, chud_ppc_srr0); break; }
381 if(spr==chud_ppc_srr1) { mfspr(val, chud_ppc_srr1); break; }
382 if(spr==chud_ppc_dsisr) { mfspr(val, chud_ppc_dsisr); break; }
383 if(spr==chud_ppc_dar) { mfspr(val, chud_ppc_dar); break; }
384 if(spr==chud_ppc_dec) { mfspr(val, chud_ppc_dec); break; }
385 if(spr==chud_ppc_sdr1) { mfspr(val, chud_ppc_sdr1); break; }
386 if(spr==chud_ppc_sprg0) { mfspr(val, chud_ppc_sprg0); break; }
387 if(spr==chud_ppc_sprg1) { mfspr(val, chud_ppc_sprg1); break; }
388 if(spr==chud_ppc_sprg2) { mfspr(val, chud_ppc_sprg2); break; }
389 if(spr==chud_ppc_sprg3) { mfspr(val, chud_ppc_sprg3); break; }
390 if(spr==chud_ppc_ear) { mfspr(val, chud_ppc_ear); break; }
391 if(spr==chud_ppc_tbl) { mfspr(val, 268); break; } /* timebase consists of read registers and write registers */
392 if(spr==chud_ppc_tbu) { mfspr(val, 269); break; }
393 if(spr==chud_ppc_pvr) { mfspr(val, chud_ppc_pvr); break; }
394 if(spr==chud_ppc_ibat0u) { mfspr(val, chud_ppc_ibat0u); break; }
395 if(spr==chud_ppc_ibat0l) { mfspr(val, chud_ppc_ibat0l); break; }
396 if(spr==chud_ppc_ibat1u) { mfspr(val, chud_ppc_ibat1u); break; }
397 if(spr==chud_ppc_ibat1l) { mfspr(val, chud_ppc_ibat1l); break; }
398 if(spr==chud_ppc_ibat2u) { mfspr(val, chud_ppc_ibat2u); break; }
399 if(spr==chud_ppc_ibat2l) { mfspr(val, chud_ppc_ibat2l); break; }
400 if(spr==chud_ppc_ibat3u) { mfspr(val, chud_ppc_ibat3u); break; }
401 if(spr==chud_ppc_ibat3l) { mfspr(val, chud_ppc_ibat3l); break; }
402 if(spr==chud_ppc_dbat0u) { mfspr(val, chud_ppc_dbat0u); break; }
403 if(spr==chud_ppc_dbat0l) { mfspr(val, chud_ppc_dbat0l); break; }
404 if(spr==chud_ppc_dbat1u) { mfspr(val, chud_ppc_dbat1u); break; }
405 if(spr==chud_ppc_dbat1l) { mfspr(val, chud_ppc_dbat1l); break; }
406 if(spr==chud_ppc_dbat2u) { mfspr(val, chud_ppc_dbat2u); break; }
407 if(spr==chud_ppc_dbat2l) { mfspr(val, chud_ppc_dbat2l); break; }
408 if(spr==chud_ppc_dbat3u) { mfspr(val, chud_ppc_dbat3u); break; }
409 if(spr==chud_ppc_dbat3l) { mfspr(val, chud_ppc_dbat3l); break; }
410 if(spr==chud_ppc_dabr) { mfspr(val, chud_ppc_dabr); break; }
411 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
412 struct ppc_thread_state64 state;
413 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
414 kern_return_t kr;
415 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
416 if(KERN_SUCCESS==kr) {
417 val = state.srr1;
418 } else {
419 retval = KERN_FAILURE;
420 }
421 break;
422 }
423
424 /* PPC SPRs - 32-bit implementations */
425 if(spr==chud_ppc32_sr0) { mfsr(val, 0); break; }
426 if(spr==chud_ppc32_sr1) { mfsr(val, 1); break; }
427 if(spr==chud_ppc32_sr2) { mfsr(val, 2); break; }
428 if(spr==chud_ppc32_sr3) { mfsr(val, 3); break; }
429 if(spr==chud_ppc32_sr4) { mfsr(val, 4); break; }
430 if(spr==chud_ppc32_sr5) { mfsr(val, 5); break; }
431 if(spr==chud_ppc32_sr6) { mfsr(val, 6); break; }
432 if(spr==chud_ppc32_sr7) { mfsr(val, 7); break; }
433 if(spr==chud_ppc32_sr8) { mfsr(val, 8); break; }
434 if(spr==chud_ppc32_sr9) { mfsr(val, 9); break; }
435 if(spr==chud_ppc32_sr10) { mfsr(val, 10); break; }
436 if(spr==chud_ppc32_sr11) { mfsr(val, 11); break; }
437 if(spr==chud_ppc32_sr12) { mfsr(val, 12); break; }
438 if(spr==chud_ppc32_sr13) { mfsr(val, 13); break; }
439 if(spr==chud_ppc32_sr14) { mfsr(val, 14); break; }
440 if(spr==chud_ppc32_sr15) { mfsr(val, 15); break; }
441
442 /* PPC SPRs - 64-bit implementations */
443 if(spr==chud_ppc64_ctrl) { mfspr(val, chud_ppc64_ctrl); break; }
444
445 /* Implementation Specific SPRs */
446 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_750) {
447 if(spr==chud_750_mmcr0) { mfspr(val, chud_750_mmcr0); break; }
448 if(spr==chud_750_pmc1) { mfspr(val, chud_750_pmc1); break; }
449 if(spr==chud_750_pmc2) { mfspr(val, chud_750_pmc2); break; }
450 if(spr==chud_750_sia) { mfspr(val, chud_750_sia); break; }
451 if(spr==chud_750_mmcr1) { mfspr(val, chud_750_mmcr1); break; }
452 if(spr==chud_750_pmc3) { mfspr(val, chud_750_pmc3); break; }
453 if(spr==chud_750_pmc4) { mfspr(val, chud_750_pmc4); break; }
454 if(spr==chud_750_hid0) { mfspr(val, chud_750_hid0); break; }
455 if(spr==chud_750_hid1) { mfspr(val, chud_750_hid1); break; }
456 if(spr==chud_750_iabr) { mfspr(val, chud_750_iabr); break; }
457 if(spr==chud_750_ictc) { mfspr(val, chud_750_ictc); break; }
458 if(spr==chud_750_thrm1) { mfspr(val, chud_750_thrm1); break; }
459 if(spr==chud_750_thrm2) { mfspr(val, chud_750_thrm2); break; }
460 if(spr==chud_750_thrm3) { mfspr(val, chud_750_thrm3); break; }
461 if(spr==chud_750_l2cr) { mfspr(val, chud_750_l2cr); break; }
462
463 // 750FX only
464 if(spr==chud_750fx_ibat4u) { mfspr(val, chud_750fx_ibat4u); break; }
465 if(spr==chud_750fx_ibat4l) { mfspr(val, chud_750fx_ibat4l); break; }
466 if(spr==chud_750fx_ibat5u) { mfspr(val, chud_750fx_ibat5u); break; }
467 if(spr==chud_750fx_ibat5l) { mfspr(val, chud_750fx_ibat5l); break; }
468 if(spr==chud_750fx_ibat6u) { mfspr(val, chud_750fx_ibat6u); break; }
469 if(spr==chud_750fx_ibat6l) { mfspr(val, chud_750fx_ibat6l); break; }
470 if(spr==chud_750fx_ibat7u) { mfspr(val, chud_750fx_ibat7u); break; }
471 if(spr==chud_750fx_ibat7l) { mfspr(val, chud_750fx_ibat7l); break; }
472 if(spr==chud_750fx_dbat4u) { mfspr(val, chud_750fx_dbat4u); break; }
473 if(spr==chud_750fx_dbat4l) { mfspr(val, chud_750fx_dbat4l); break; }
474 if(spr==chud_750fx_dbat5u) { mfspr(val, chud_750fx_dbat5u); break; }
475 if(spr==chud_750fx_dbat5l) { mfspr(val, chud_750fx_dbat5l); break; }
476 if(spr==chud_750fx_dbat6u) { mfspr(val, chud_750fx_dbat6u); break; }
477 if(spr==chud_750fx_dbat6l) { mfspr(val, chud_750fx_dbat6l); break; }
478 if(spr==chud_750fx_dbat7u) { mfspr(val, chud_750fx_dbat7u); break; }
479 if(spr==chud_750fx_dbat7l) { mfspr(val, chud_750fx_dbat7l); break; }
480
481 // 750FX >= DDR2.x only
482 if(spr==chud_750fx_hid2) { mfspr(val, chud_750fx_hid2); break; }
483 }
484
485 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7400) {
486 if(spr==chud_7400_mmcr2) { mfspr(val, chud_7400_mmcr2); break; }
487 if(spr==chud_7400_bamr) { mfspr(val, chud_7400_bamr); break; }
488 if(spr==chud_7400_mmcr0) { mfspr(val, chud_7400_mmcr0); break; }
489 if(spr==chud_7400_pmc1) { mfspr(val, chud_7400_pmc1); break; }
490 if(spr==chud_7400_pmc2) { mfspr(val, chud_7400_pmc2); break; }
491 if(spr==chud_7400_siar) { mfspr(val, chud_7400_siar); break; }
492 if(spr==chud_7400_mmcr1) { mfspr(val, chud_7400_mmcr1); break; }
493 if(spr==chud_7400_pmc3) { mfspr(val, chud_7400_pmc3); break; }
494 if(spr==chud_7400_pmc4) { mfspr(val, chud_7400_pmc4); break; }
495 if(spr==chud_7400_hid0) { mfspr(val, chud_7400_hid0); break; }
496 if(spr==chud_7400_hid1) { mfspr(val, chud_7400_hid1); break; }
497 if(spr==chud_7400_iabr) { mfspr(val, chud_7400_iabr); break; }
498 if(spr==chud_7400_msscr0) { mfspr(val, chud_7400_msscr0); break; }
499 if(spr==chud_7400_msscr1) { mfspr(val, chud_7400_msscr1); break; } /* private */
500 if(spr==chud_7400_ictc) { mfspr(val, chud_7400_ictc); break; }
501 if(spr==chud_7400_thrm1) { mfspr(val, chud_7400_thrm1); break; }
502 if(spr==chud_7400_thrm2) { mfspr(val, chud_7400_thrm2); break; }
503 if(spr==chud_7400_thrm3) { mfspr(val, chud_7400_thrm3); break; }
504 if(spr==chud_7400_pir) { mfspr(val, chud_7400_pir); break; }
505 if(spr==chud_7400_l2cr) { mfspr(val, chud_7400_l2cr); break; }
506
507 // 7410 only
508 if(spr==chud_7410_l2pmcr) { mfspr(val, chud_7410_l2pmcr); break; }
509 }
510
511 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7450) {
512 if(spr==chud_7450_mmcr2) { mfspr(val, chud_7450_mmcr2); break; }
513 if(spr==chud_7450_pmc5) { mfspr(val, chud_7450_pmc5); break; }
514 if(spr==chud_7450_pmc6) { mfspr(val, chud_7450_pmc6); break; }
515 if(spr==chud_7450_bamr) { mfspr(val, chud_7450_bamr); break; }
516 if(spr==chud_7450_mmcr0) { mfspr(val, chud_7450_mmcr0); break; }
517 if(spr==chud_7450_pmc1) { mfspr(val, chud_7450_pmc1); break; }
518 if(spr==chud_7450_pmc2) { mfspr(val, chud_7450_pmc2); break; }
519 if(spr==chud_7450_siar) { mfspr(val, chud_7450_siar); break; }
520 if(spr==chud_7450_mmcr1) { mfspr(val, chud_7450_mmcr1); break; }
521 if(spr==chud_7450_pmc3) { mfspr(val, chud_7450_pmc3); break; }
522 if(spr==chud_7450_pmc4) { mfspr(val, chud_7450_pmc4); break; }
523 if(spr==chud_7450_tlbmiss) { mfspr(val, chud_7450_tlbmiss); break; }
524 if(spr==chud_7450_ptehi) { mfspr(val, chud_7450_ptehi); break; }
525 if(spr==chud_7450_ptelo) { mfspr(val, chud_7450_ptelo); break; }
526 if(spr==chud_7450_l3pm) { mfspr(val, chud_7450_l3pm); break; }
527 if(spr==chud_7450_hid0) { mfspr(val, chud_7450_hid0); break; }
528 if(spr==chud_7450_hid1) { mfspr(val, chud_7450_hid1); break; }
529 if(spr==chud_7450_iabr) { mfspr(val, chud_7450_iabr); break; }
530 if(spr==chud_7450_ldstdb) { mfspr(val, chud_7450_ldstdb); break; }
531 if(spr==chud_7450_msscr0) { mfspr(val, chud_7450_msscr0); break; }
532 if(spr==chud_7450_msssr0) { mfspr(val, chud_7450_msssr0); break; }
533 if(spr==chud_7450_ldstcr) { mfspr(val, chud_7450_ldstcr); break; }
534 if(spr==chud_7450_ictc) { mfspr(val, chud_7450_ictc); break; }
535 if(spr==chud_7450_ictrl) { mfspr(val, chud_7450_ictrl); break; }
536 if(spr==chud_7450_thrm1) { mfspr(val, chud_7450_thrm1); break; }
537 if(spr==chud_7450_thrm2) { mfspr(val, chud_7450_thrm2); break; }
538 if(spr==chud_7450_thrm3) { mfspr(val, chud_7450_thrm3); break; }
539 if(spr==chud_7450_pir) { mfspr(val, chud_7450_pir); break; }
540 if(spr==chud_7450_l2cr) { mfspr(val, chud_7450_l2cr); break; }
541 if(spr==chud_7450_l3cr) { mfspr(val, chud_7450_l3cr); break; }
542
543 // 7455/7457 only
544 if(spr==chud_7455_sprg4) { mfspr(val, chud_7455_sprg4); break; }
545 if(spr==chud_7455_sprg5) { mfspr(val, chud_7455_sprg5); break; }
546 if(spr==chud_7455_sprg6) { mfspr(val, chud_7455_sprg6); break; }
547 if(spr==chud_7455_sprg7) { mfspr(val, chud_7455_sprg7); break; }
548 if(spr==chud_7455_ibat4u) { mfspr(val, chud_7455_ibat4u); break; }
549 if(spr==chud_7455_ibat4l) { mfspr(val, chud_7455_ibat4l); break; }
550 if(spr==chud_7455_ibat5u) { mfspr(val, chud_7455_ibat5u); break; }
551 if(spr==chud_7455_ibat5l) { mfspr(val, chud_7455_ibat5l); break; }
552 if(spr==chud_7455_ibat6u) { mfspr(val, chud_7455_ibat6u); break; }
553 if(spr==chud_7455_ibat6l) { mfspr(val, chud_7455_ibat6l); break; }
554 if(spr==chud_7455_ibat7u) { mfspr(val, chud_7455_ibat7u); break; }
555 if(spr==chud_7455_ibat7l) { mfspr(val, chud_7455_ibat7l); break; }
556 if(spr==chud_7455_dbat4u) { mfspr(val, chud_7455_dbat4u); break; }
557 if(spr==chud_7455_dbat4l) { mfspr(val, chud_7455_dbat4l); break; }
558 if(spr==chud_7455_dbat5u) { mfspr(val, chud_7455_dbat5u); break; }
559 if(spr==chud_7455_dbat5l) { mfspr(val, chud_7455_dbat5l); break; }
560 if(spr==chud_7455_dbat6u) { mfspr(val, chud_7455_dbat6u); break; }
561 if(spr==chud_7455_dbat6l) { mfspr(val, chud_7455_dbat6l); break; }
562 if(spr==chud_7455_dbat7u) { mfspr(val, chud_7455_dbat7u); break; }
563 if(spr==chud_7455_dbat7l) { mfspr(val, chud_7455_dbat7l); break; }
564 }
565
566 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
567 if(spr==chud_970_pir) { mfspr(val, chud_970_pir); break; }
568 if(spr==chud_970_pmc1) { mfspr(val, chud_970_pmc1); break; }
569 if(spr==chud_970_pmc2) { mfspr(val, chud_970_pmc2); break; }
570 if(spr==chud_970_pmc3) { mfspr(val, chud_970_pmc3); break; }
571 if(spr==chud_970_pmc4) { mfspr(val, chud_970_pmc4); break; }
572 if(spr==chud_970_pmc5) { mfspr(val, chud_970_pmc5); break; }
573 if(spr==chud_970_pmc6) { mfspr(val, chud_970_pmc6); break; }
574 if(spr==chud_970_pmc7) { mfspr(val, chud_970_pmc7); break; }
575 if(spr==chud_970_pmc8) { mfspr(val, chud_970_pmc8); break; }
576 if(spr==chud_970_hdec) { mfspr(val, chud_970_hdec); break; }
577 }
578
579 /* we only get here if none of the above cases qualify */
580 retval = KERN_INVALID_ARGUMENT;
581 } while(0);
582
583 chudxnu_set_interrupts_enabled(oldlevel); /* enable interrupts */
584
585 if(cpu>=0) { // cpu<0 means don't bind
586 chudxnu_unbind_thread(current_thread());
587 }
588
589 *val_p = val;
590
591 return retval;
592}
593
594__private_extern__
595kern_return_t chudxnu_read_spr64(int cpu, int spr, uint64_t *val_p)
596{
597 kern_return_t retval = KERN_SUCCESS;
598 boolean_t oldlevel;
599
600 /* bind to requested CPU */
601 if(cpu>=0) { // cpu<0 means don't bind
602 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
603 return KERN_INVALID_ARGUMENT;
604 }
605 }
606
607 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
608
609 do {
610 /* PPC SPRs - 32-bit and 64-bit implementations */
611 if(spr==chud_ppc_srr0) { retval = mfspr64(val_p, chud_ppc_srr0); break; }
612 if(spr==chud_ppc_srr1) { retval = mfspr64(val_p, chud_ppc_srr1); break; }
613 if(spr==chud_ppc_dar) { retval = mfspr64(val_p, chud_ppc_dar); break; }
614 if(spr==chud_ppc_dsisr) { retval = mfspr64(val_p, chud_ppc_dsisr); break; }
615 if(spr==chud_ppc_sdr1) { retval = mfspr64(val_p, chud_ppc_sdr1); break; }
616 if(spr==chud_ppc_sprg0) { retval = mfspr64(val_p, chud_ppc_sprg0); break; }
617 if(spr==chud_ppc_sprg1) { retval = mfspr64(val_p, chud_ppc_sprg1); break; }
618 if(spr==chud_ppc_sprg2) { retval = mfspr64(val_p, chud_ppc_sprg2); break; }
619 if(spr==chud_ppc_sprg3) { retval = mfspr64(val_p, chud_ppc_sprg3); break; }
620 if(spr==chud_ppc_dabr) { retval = mfspr64(val_p, chud_ppc_dabr); break; }
621 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
622 struct ppc_thread_state64 state;
623 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
624 kern_return_t kr;
625 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
626 if(KERN_SUCCESS==kr) {
627 *val_p = state.srr1;
628 } else {
629 retval = KERN_FAILURE;
630 }
631 break;
632 }
633
634 /* PPC SPRs - 64-bit implementations */
635 if(spr==chud_ppc64_asr) { retval = mfspr64(val_p, chud_ppc64_asr); break; }
636 if(spr==chud_ppc64_accr) { retval = mfspr64(val_p, chud_ppc64_accr); break; }
637
638 /* Implementation Specific SPRs */
639 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
640 if(spr==chud_970_hid0) { retval = mfspr64(val_p, chud_970_hid0); break; }
641 if(spr==chud_970_hid1) { retval = mfspr64(val_p, chud_970_hid1); break; }
642 if(spr==chud_970_hid4) { retval = mfspr64(val_p, chud_970_hid4); break; }
643 if(spr==chud_970_hid5) { retval = mfspr64(val_p, chud_970_hid5); break; }
644 if(spr==chud_970_mmcr0) { retval = mfspr64(val_p, chud_970_mmcr0); break; }
645 if(spr==chud_970_mmcr1) { retval = mfspr64(val_p, chud_970_mmcr1); break; }
646 if(spr==chud_970_mmcra) { retval = mfspr64(val_p, chud_970_mmcra); break; }
647 if(spr==chud_970_siar) { retval = mfspr64(val_p, chud_970_siar); break; }
648 if(spr==chud_970_sdar) { retval = mfspr64(val_p, chud_970_sdar); break; }
649 if(spr==chud_970_imc) { retval = mfspr64(val_p, chud_970_imc); break; }
650 if(spr==chud_970_rmor) { retval = mfspr64(val_p, chud_970_rmor); break; }
651 if(spr==chud_970_hrmor) { retval = mfspr64(val_p, chud_970_hrmor); break; }
652 if(spr==chud_970_hior) { retval = mfspr64(val_p, chud_970_hior); break; }
653 if(spr==chud_970_lpidr) { retval = mfspr64(val_p, chud_970_lpidr); break; }
654 if(spr==chud_970_lpcr) { retval = mfspr64(val_p, chud_970_lpcr); break; }
655 if(spr==chud_970_dabrx) { retval = mfspr64(val_p, chud_970_dabrx); break; }
656 if(spr==chud_970_hsprg0) { retval = mfspr64(val_p, chud_970_hsprg0); break; }
657 if(spr==chud_970_hsprg1) { retval = mfspr64(val_p, chud_970_hsprg1); break; }
658 if(spr==chud_970_hsrr0) { retval = mfspr64(val_p, chud_970_hsrr0); break; }
659 if(spr==chud_970_hsrr1) { retval = mfspr64(val_p, chud_970_hsrr1); break; }
660 if(spr==chud_970_hdec) { retval = mfspr64(val_p, chud_970_hdec); break; }
661 if(spr==chud_970_trig0) { retval = mfspr64(val_p, chud_970_trig0); break; }
662 if(spr==chud_970_trig1) { retval = mfspr64(val_p, chud_970_trig1); break; }
663 if(spr==chud_970_trig2) { retval = mfspr64(val_p, chud_970_trig2); break; }
664 if(spr==chud_970_scomc) { retval = mfspr64(val_p, chud_970_scomc); break; }
665 if(spr==chud_970_scomd) { retval = mfspr64(val_p, chud_970_scomd); break; }
666 }
667
668 /* we only get here if none of the above cases qualify */
669 *val_p = 0xFFFFFFFFFFFFFFFFLL;
670 retval = KERN_INVALID_ARGUMENT;
671 } while(0);
672
673 chudxnu_set_interrupts_enabled(oldlevel); /* enable interrupts */
674
675 if(cpu>=0) { // cpu<0 means don't bind
676 chudxnu_unbind_thread(current_thread());
677 }
678
679 return retval;
55e303ae
A		 680}
681
91447636
A		 682__private_extern__
683kern_return_t chudxnu_write_spr(int cpu, int spr, uint32_t val)
684{
685 kern_return_t retval = KERN_SUCCESS;
686 boolean_t oldlevel;
687
688 /* bind to requested CPU */
689 if(cpu>=0) { // cpu<0 means don't bind
690 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
691 return KERN_INVALID_ARGUMENT;
692 }
693 }
694
695 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
696
697 do {
698 /* PPC SPRs - 32-bit and 64-bit implementations */
699 if(spr==chud_ppc_srr0) { mtspr(chud_ppc_srr0, val); break; }
700 if(spr==chud_ppc_srr1) { mtspr(chud_ppc_srr1, val); break; }
701 if(spr==chud_ppc_dsisr) { mtspr(chud_ppc_dsisr, val); break; }
702 if(spr==chud_ppc_dar) { mtspr(chud_ppc_dar, val); break; }
703 if(spr==chud_ppc_dec) { mtspr(chud_ppc_dec, val); break; }
704 if(spr==chud_ppc_sdr1) { mtspr(chud_ppc_sdr1, val); break; }
705 if(spr==chud_ppc_sprg0) { mtspr(chud_ppc_sprg0, val); break; }
706 if(spr==chud_ppc_sprg1) { mtspr(chud_ppc_sprg1, val); break; }
707 if(spr==chud_ppc_sprg2) { mtspr(chud_ppc_sprg2, val); break; }
708 if(spr==chud_ppc_sprg3) { mtspr(chud_ppc_sprg3, val); break; }
709 if(spr==chud_ppc_ear) { mtspr(chud_ppc_ear, val); break; }
710 if(spr==chud_ppc_tbl) { mtspr(284, val); break; } /* timebase consists of read registers and write registers */
711 if(spr==chud_ppc_tbu) { mtspr(285, val); break; }
712 if(spr==chud_ppc_pvr) { mtspr(chud_ppc_pvr, val); break; }
713 if(spr==chud_ppc_ibat0u) { mtspr(chud_ppc_ibat0u, val); break; }
714 if(spr==chud_ppc_ibat0l) { mtspr(chud_ppc_ibat0l, val); break; }
715 if(spr==chud_ppc_ibat1u) { mtspr(chud_ppc_ibat1u, val); break; }
716 if(spr==chud_ppc_ibat1l) { mtspr(chud_ppc_ibat1l, val); break; }
717 if(spr==chud_ppc_ibat2u) { mtspr(chud_ppc_ibat2u, val); break; }
718 if(spr==chud_ppc_ibat2l) { mtspr(chud_ppc_ibat2l, val); break; }
719 if(spr==chud_ppc_ibat3u) { mtspr(chud_ppc_ibat3u, val); break; }
720 if(spr==chud_ppc_ibat3l) { mtspr(chud_ppc_ibat3l, val); break; }
721 if(spr==chud_ppc_dbat0u) { mtspr(chud_ppc_dbat0u, val); break; }
722 if(spr==chud_ppc_dbat0l) { mtspr(chud_ppc_dbat0l, val); break; }
723 if(spr==chud_ppc_dbat1u) { mtspr(chud_ppc_dbat1u, val); break; }
724 if(spr==chud_ppc_dbat1l) { mtspr(chud_ppc_dbat1l, val); break; }
725 if(spr==chud_ppc_dbat2u) { mtspr(chud_ppc_dbat2u, val); break; }
726 if(spr==chud_ppc_dbat2l) { mtspr(chud_ppc_dbat2l, val); break; }
727 if(spr==chud_ppc_dbat3u) { mtspr(chud_ppc_dbat3u, val); break; }
728 if(spr==chud_ppc_dbat3l) { mtspr(chud_ppc_dbat3l, val); break; }
729 if(spr==chud_ppc_dabr) { mtspr(chud_ppc_dabr, val); break; }
730 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
731 struct ppc_thread_state64 state;
732 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
733 kern_return_t kr;
734 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
735 if(KERN_SUCCESS==kr) {
736 state.srr1 = val;
737 kr = chudxnu_thread_set_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, count, TRUE /* user only */);
738 if(KERN_SUCCESS!=kr) {
739 retval = KERN_FAILURE;
740 }
741 } else {
742 retval = KERN_FAILURE;
743 }
744 break;
745 }
746
747 /* PPC SPRs - 32-bit implementations */
748 if(spr==chud_ppc32_sr0) { mtsr(0, val); break; }
749 if(spr==chud_ppc32_sr1) { mtsr(1, val); break; }
750 if(spr==chud_ppc32_sr2) { mtsr(2, val); break; }
751 if(spr==chud_ppc32_sr3) { mtsr(3, val); break; }
752 if(spr==chud_ppc32_sr4) { mtsr(4, val); break; }
753 if(spr==chud_ppc32_sr5) { mtsr(5, val); break; }
754 if(spr==chud_ppc32_sr6) { mtsr(6, val); break; }
755 if(spr==chud_ppc32_sr7) { mtsr(7, val); break; }
756 if(spr==chud_ppc32_sr8) { mtsr(8, val); break; }
757 if(spr==chud_ppc32_sr9) { mtsr(9, val); break; }
758 if(spr==chud_ppc32_sr10) { mtsr(10, val); break; }
759 if(spr==chud_ppc32_sr11) { mtsr(11, val); break; }
760 if(spr==chud_ppc32_sr12) { mtsr(12, val); break; }
761 if(spr==chud_ppc32_sr13) { mtsr(13, val); break; }
762 if(spr==chud_ppc32_sr14) { mtsr(14, val); break; }
763 if(spr==chud_ppc32_sr15) { mtsr(15, val); break; }
764
765 /* Implementation Specific SPRs */
766 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_750) {
767 if(spr==chud_750_mmcr0) { mtspr(chud_750_mmcr0, val); break; }
768 if(spr==chud_750_pmc1) { mtspr(chud_750_pmc1, val); break; }
769 if(spr==chud_750_pmc2) { mtspr(chud_750_pmc2, val); break; }
770 if(spr==chud_750_sia) { mtspr(chud_750_sia, val); break; }
771 if(spr==chud_750_mmcr1) { mtspr(chud_750_mmcr1, val); break; }
772 if(spr==chud_750_pmc3) { mtspr(chud_750_pmc3, val); break; }
773 if(spr==chud_750_pmc4) { mtspr(chud_750_pmc4, val); break; }
774 if(spr==chud_750_iabr) { mtspr(chud_750_iabr, val); break; }
775 if(spr==chud_750_ictc) { mtspr(chud_750_ictc, val); break; }
776 if(spr==chud_750_thrm1) { mtspr(chud_750_thrm1, val); break; }
777 if(spr==chud_750_thrm2) { mtspr(chud_750_thrm2, val); break; }
778 if(spr==chud_750_thrm3) { mtspr(chud_750_thrm3, val); break; }
779 if(spr==chud_750_l2cr) {
780 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
781 break;
782 }
783 if(spr==chud_750_hid0) {
784 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
785 break;
786 }
787 if(spr==chud_750_hid1) {
788 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
789 break;
790 }
791
792 // 750FX only
793 if(spr==chud_750fx_ibat4u) { mtspr(chud_750fx_ibat4u, val); break; }
794 if(spr==chud_750fx_ibat4l) { mtspr(chud_750fx_ibat4l, val); break; }
795 if(spr==chud_750fx_ibat5u) { mtspr(chud_750fx_ibat5u, val); break; }
796 if(spr==chud_750fx_ibat5l) { mtspr(chud_750fx_ibat5l, val); break; }
797 if(spr==chud_750fx_ibat6u) { mtspr(chud_750fx_ibat6u, val); break; }
798 if(spr==chud_750fx_ibat6l) { mtspr(chud_750fx_ibat6l, val); break; }
799 if(spr==chud_750fx_ibat7u) { mtspr(chud_750fx_ibat7u, val); break; }
800 if(spr==chud_750fx_ibat7l) { mtspr(chud_750fx_ibat7l, val); break; }
801 if(spr==chud_750fx_dbat4u) { mtspr(chud_750fx_dbat4u, val); break; }
802 if(spr==chud_750fx_dbat4l) { mtspr(chud_750fx_dbat4l, val); break; }
803 if(spr==chud_750fx_dbat5u) { mtspr(chud_750fx_dbat5u, val); break; }
804 if(spr==chud_750fx_dbat5l) { mtspr(chud_750fx_dbat5l, val); break; }
805 if(spr==chud_750fx_dbat6u) { mtspr(chud_750fx_dbat6u, val); break; }
806 if(spr==chud_750fx_dbat6l) { mtspr(chud_750fx_dbat6l, val); break; }
807 if(spr==chud_750fx_dbat7u) { mtspr(chud_750fx_dbat7u, val); break; }
808 if(spr==chud_750fx_dbat7l) { mtspr(chud_750fx_dbat7l, val); break; }
809
810 // 750FX >= DDR2.x
811 if(spr==chud_750fx_hid2) { mtspr(chud_750fx_hid2, val); break; }
812 }
813
814 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7400) {
815 if(spr==chud_7400_mmcr2) { mtspr(chud_7400_mmcr2, val); break; }
816 if(spr==chud_7400_bamr) { mtspr(chud_7400_bamr, val); break; }
817 if(spr==chud_7400_mmcr0) { mtspr(chud_7400_mmcr0, val); break; }
818 if(spr==chud_7400_pmc1) { mtspr(chud_7400_pmc1, val); break; }
819 if(spr==chud_7400_pmc2) { mtspr(chud_7400_pmc2, val); break; }
820 if(spr==chud_7400_siar) { mtspr(chud_7400_siar, val); break; }
821 if(spr==chud_7400_mmcr1) { mtspr(chud_7400_mmcr1, val); break; }
822 if(spr==chud_7400_pmc3) { mtspr(chud_7400_pmc3, val); break; }
823 if(spr==chud_7400_pmc4) { mtspr(chud_7400_pmc4, val); break; }
824 if(spr==chud_7400_iabr) { mtspr(chud_7400_iabr, val); break; }
825 if(spr==chud_7400_ictc) { mtspr(chud_7400_ictc, val); break; }
826 if(spr==chud_7400_thrm1) { mtspr(chud_7400_thrm1, val); break; }
827 if(spr==chud_7400_thrm2) { mtspr(chud_7400_thrm2, val); break; }
828 if(spr==chud_7400_thrm3) { mtspr(chud_7400_thrm3, val); break; }
829 if(spr==chud_7400_pir) { mtspr(chud_7400_pir, val); break; }
830
831 if(spr==chud_7400_l2cr) {
832 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
833 break;
834 }
835 if(spr==chud_7400_hid0) {
836 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
837 break;
838 }
839 if(spr==chud_7400_hid1) {
840 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
841 break;
842 }
843 if(spr==chud_7400_msscr0) {
844 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
845 break;
846 }
847 if(spr==chud_7400_msscr1) { /* private */
848 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
849 break;
850 }
851
852 // 7410 only
853 if(spr==chud_7410_l2pmcr) { mtspr(chud_7410_l2pmcr, val); break; }
854 }
855
856 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7450) {
857 if(spr==chud_7450_mmcr2) { mtspr(chud_7450_mmcr2, val); break; }
858 if(spr==chud_7450_pmc5) { mtspr(chud_7450_pmc5, val); break; }
859 if(spr==chud_7450_pmc6) { mtspr(chud_7450_pmc6, val); break; }
860 if(spr==chud_7450_bamr) { mtspr(chud_7450_bamr, val); break; }
861 if(spr==chud_7450_mmcr0) { mtspr(chud_7450_mmcr0, val); break; }
862 if(spr==chud_7450_pmc1) { mtspr(chud_7450_pmc1, val); break; }
863 if(spr==chud_7450_pmc2) { mtspr(chud_7450_pmc2, val); break; }
864 if(spr==chud_7450_siar) { mtspr(chud_7450_siar, val); break; }
865 if(spr==chud_7450_mmcr1) { mtspr(chud_7450_mmcr1, val); break; }
866 if(spr==chud_7450_pmc3) { mtspr(chud_7450_pmc3, val); break; }
867 if(spr==chud_7450_pmc4) { mtspr(chud_7450_pmc4, val); break; }
868 if(spr==chud_7450_tlbmiss) { mtspr(chud_7450_tlbmiss, val); break; }
869 if(spr==chud_7450_ptehi) { mtspr(chud_7450_ptehi, val); break; }
870 if(spr==chud_7450_ptelo) { mtspr(chud_7450_ptelo, val); break; }
871 if(spr==chud_7450_l3pm) { mtspr(chud_7450_l3pm, val); break; }
872 if(spr==chud_7450_iabr) { mtspr(chud_7450_iabr, val); break; }
873 if(spr==chud_7450_ldstdb) { mtspr(chud_7450_ldstdb, val); break; }
874 if(spr==chud_7450_ictc) { mtspr(chud_7450_ictc, val); break; }
875 if(spr==chud_7450_thrm1) { mtspr(chud_7450_thrm1, val); break; }
876 if(spr==chud_7450_thrm2) { mtspr(chud_7450_thrm2, val); break; }
877 if(spr==chud_7450_thrm3) { mtspr(chud_7450_thrm3, val); break; }
878 if(spr==chud_7450_pir) { mtspr(chud_7450_pir, val); break; }
879
880 if(spr==chud_7450_l2cr) {
881 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
882 break;
883 }
884
885 if(spr==chud_7450_l3cr) {
886 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
887 break;
888 }
889 if(spr==chud_7450_ldstcr) {
890 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
891 break;
892 }
893 if(spr==chud_7450_hid0) {
894 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
895 break;
896 }
897 if(spr==chud_7450_hid1) {
898 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
899 break;
900 }
901 if(spr==chud_7450_msscr0) {
902 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
903 break;
904 }
905 if(spr==chud_7450_msssr0) {
906 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
907 break;
908 }
909 if(spr==chud_7450_ictrl) {
910 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
911 break;
912 }
913
914 // 7455/7457 only
915 if(spr==chud_7455_sprg4) { mtspr(chud_7455_sprg4, val); break; }
916 if(spr==chud_7455_sprg5) { mtspr(chud_7455_sprg5, val); break; }
917 if(spr==chud_7455_sprg6) { mtspr(chud_7455_sprg6, val); break; }
918 if(spr==chud_7455_sprg7) { mtspr(chud_7455_sprg7, val); break; }
919 if(spr==chud_7455_ibat4u) { mtspr(chud_7455_ibat4u, val); break; }
920 if(spr==chud_7455_ibat4l) { mtspr(chud_7455_ibat4l, val); break; }
921 if(spr==chud_7455_ibat5u) { mtspr(chud_7455_ibat5u, val); break; }
922 if(spr==chud_7455_ibat5l) { mtspr(chud_7455_ibat5l, val); break; }
923 if(spr==chud_7455_ibat6u) { mtspr(chud_7455_ibat6u, val); break; }
924 if(spr==chud_7455_ibat6l) { mtspr(chud_7455_ibat6l, val); break; }
925 if(spr==chud_7455_ibat7u) { mtspr(chud_7455_ibat7u, val); break; }
926 if(spr==chud_7455_ibat7l) { mtspr(chud_7455_ibat7l, val); break; }
927 if(spr==chud_7455_dbat4u) { mtspr(chud_7455_dbat4u, val); break; }
928 if(spr==chud_7455_dbat4l) { mtspr(chud_7455_dbat4l, val); break; }
929 if(spr==chud_7455_dbat5u) { mtspr(chud_7455_dbat5u, val); break; }
930 if(spr==chud_7455_dbat5l) { mtspr(chud_7455_dbat5l, val); break; }
931 if(spr==chud_7455_dbat6u) { mtspr(chud_7455_dbat6u, val); break; }
932 if(spr==chud_7455_dbat6l) { mtspr(chud_7455_dbat6l, val); break; }
933 if(spr==chud_7455_dbat7u) { mtspr(chud_7455_dbat7u, val); break; }
934 if(spr==chud_7455_dbat7l) { mtspr(chud_7455_dbat7l, val); break; }
935 }
936
937 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
938 if(spr==chud_970_pir) { mtspr(chud_970_pir, val); break; }
939 if(spr==chud_970_pmc1) { mtspr(chud_970_pmc1, val); break; }
940 if(spr==chud_970_pmc2) { mtspr(chud_970_pmc2, val); break; }
941 if(spr==chud_970_pmc3) { mtspr(chud_970_pmc3, val); break; }
942 if(spr==chud_970_pmc4) { mtspr(chud_970_pmc4, val); break; }
943 if(spr==chud_970_pmc5) { mtspr(chud_970_pmc5, val); break; }
944 if(spr==chud_970_pmc6) { mtspr(chud_970_pmc6, val); break; }
945 if(spr==chud_970_pmc7) { mtspr(chud_970_pmc7, val); break; }
946 if(spr==chud_970_pmc8) { mtspr(chud_970_pmc8, val); break; }
947 if(spr==chud_970_hdec) { mtspr(chud_970_hdec, val); break; }
948 }
949
950 /* we only get here if none of the above cases qualify */
951 retval = KERN_INVALID_ARGUMENT;
952 } while(0);
953
954 chudxnu_set_interrupts_enabled(oldlevel); /* re-enable interrupts */
955
956 if(cpu>=0) { // cpu<0 means don't bind
957 chudxnu_unbind_thread(current_thread());
958 }
959
960 return retval;
961}
962
963__private_extern__
964kern_return_t chudxnu_write_spr64(int cpu, int spr, uint64_t val)
965{
966 kern_return_t retval = KERN_SUCCESS;
967 boolean_t oldlevel;
968 uint64_t *val_p = &val;
969
970 /* bind to requested CPU */
971 if(cpu>=0) { // cpu<0 means don't bind
972 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
973 return KERN_INVALID_ARGUMENT;
974 }
975 }
976
977 oldlevel = ml_set_interrupts_enabled(FALSE); /* disable interrupts */
978
979 do {
980 /* PPC SPRs - 32-bit and 64-bit implementations */
981 if(spr==chud_ppc_srr0) { retval = mtspr64(chud_ppc_srr0, val_p); break; }
982 if(spr==chud_ppc_srr1) { retval = mtspr64(chud_ppc_srr1, val_p); break; }
983 if(spr==chud_ppc_dar) { retval = mtspr64(chud_ppc_dar, val_p); break; }
984 if(spr==chud_ppc_dsisr) { retval = mtspr64(chud_ppc_dsisr, val_p); break; }
985 if(spr==chud_ppc_sdr1) { retval = mtspr64(chud_ppc_sdr1, val_p); break; }
986 if(spr==chud_ppc_sprg0) { retval = mtspr64(chud_ppc_sprg0, val_p); break; }
987 if(spr==chud_ppc_sprg1) { retval = mtspr64(chud_ppc_sprg1, val_p); break; }
988 if(spr==chud_ppc_sprg2) { retval = mtspr64(chud_ppc_sprg2, val_p); break; }
989 if(spr==chud_ppc_sprg3) { retval = mtspr64(chud_ppc_sprg3, val_p); break; }
990 if(spr==chud_ppc_dabr) { retval = mtspr64(chud_ppc_dabr, val_p); break; }
991 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
992 struct ppc_thread_state64 state;
993 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
994 kern_return_t kr;
995 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
996 if(KERN_SUCCESS==kr) {
997 state.srr1 = val;
998 kr = chudxnu_thread_set_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, count, TRUE /* user only */);
999 if(KERN_SUCCESS!=kr) {
1000 retval = KERN_FAILURE;
1001 }
1002 } else {
1003 retval = KERN_FAILURE;
1004 }
1005 break;
1006 }
1007
1008 /* PPC SPRs - 64-bit implementations */
1009 if(spr==chud_ppc64_asr) { retval = mtspr64(chud_ppc64_asr, val_p); break; }
1010 if(spr==chud_ppc64_accr) { retval = mtspr64(chud_ppc64_accr, val_p); break; }
1011 if(spr==chud_ppc64_ctrl) { retval = mtspr64(chud_ppc64_ctrl, val_p); break; }
1012
1013 /* Implementation Specific SPRs */
1014 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
1015 if(spr==chud_970_hid0) { retval = mtspr64(chud_970_hid0, val_p); break; }
1016 if(spr==chud_970_hid1) { retval = mtspr64(chud_970_hid1, val_p); break; }
1017 if(spr==chud_970_hid4) { retval = mtspr64(chud_970_hid4, val_p); break; }
1018 if(spr==chud_970_hid5) { retval = mtspr64(chud_970_hid5, val_p); break; }
1019 if(spr==chud_970_mmcr0) { retval = mtspr64(chud_970_mmcr0, val_p); break; }
1020 if(spr==chud_970_mmcr1) { retval = mtspr64(chud_970_mmcr1, val_p); break; }
1021 if(spr==chud_970_mmcra) { retval = mtspr64(chud_970_mmcra, val_p); break; }
1022 if(spr==chud_970_siar) { retval = mtspr64(chud_970_siar, val_p); break; }
1023 if(spr==chud_970_sdar) { retval = mtspr64(chud_970_sdar, val_p); break; }
1024 if(spr==chud_970_imc) { retval = mtspr64(chud_970_imc, val_p); break; }
1025
1026 if(spr==chud_970_rmor) { retval = mtspr64(chud_970_rmor, val_p); break; }
1027 if(spr==chud_970_hrmor) { retval = mtspr64(chud_970_hrmor, val_p); break; }
1028 if(spr==chud_970_hior) { retval = mtspr64(chud_970_hior, val_p); break; }
1029 if(spr==chud_970_lpidr) { retval = mtspr64(chud_970_lpidr, val_p); break; }
1030 if(spr==chud_970_lpcr) { retval = mtspr64(chud_970_lpcr, val_p); break; }
1031 if(spr==chud_970_dabrx) { retval = mtspr64(chud_970_dabrx, val_p); break; }
1032
1033 if(spr==chud_970_hsprg0) { retval = mtspr64(chud_970_hsprg0, val_p); break; }
1034 if(spr==chud_970_hsprg1) { retval = mtspr64(chud_970_hsprg1, val_p); break; }
1035 if(spr==chud_970_hsrr0) { retval = mtspr64(chud_970_hsrr0, val_p); break; }
1036 if(spr==chud_970_hsrr1) { retval = mtspr64(chud_970_hsrr1, val_p); break; }
1037 if(spr==chud_970_hdec) { retval = mtspr64(chud_970_hdec, val_p); break; }
1038 if(spr==chud_970_trig0) { retval = mtspr64(chud_970_trig0, val_p); break; }
1039 if(spr==chud_970_trig1) { retval = mtspr64(chud_970_trig1, val_p); break; }
1040 if(spr==chud_970_trig2) { retval = mtspr64(chud_970_trig2, val_p); break; }
1041 if(spr==chud_970_scomc) { retval = mtspr64(chud_970_scomc, val_p); break; }
1042 if(spr==chud_970_scomd) { retval = mtspr64(chud_970_scomd, val_p); break; }
1043
1044 if(spr==chud_970_hid0) {
1045 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1046 break;
1047 }
1048
1049 if(spr==chud_970_hid1) {
1050 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1051 break;
1052 }
1053
1054 if(spr==chud_970_hid4) {
1055 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1056 break;
1057 }
1058
1059 if(spr==chud_970_hid5) {
1060 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1061 break;
1062 }
1063
1064 }
1065
1066 /* we only get here if none of the above cases qualify */
1067 retval = KERN_INVALID_ARGUMENT;
1068 } while(0);
1069
1070 chudxnu_set_interrupts_enabled(oldlevel); /* re-enable interrupts */
1071
1072 if(cpu>=0) { // cpu<0 means don't bind
1073 chudxnu_unbind_thread(current_thread());
1074 }
1075
1076 return retval;
1077}
1078
1079#pragma mark **** cache flush ****
1080
55e303ae
A		 1081__private_extern__
1082void chudxnu_flush_caches(void)
1083{
1084 cacheInit();
1085}
1086
1087__private_extern__
1088void chudxnu_enable_caches(boolean_t enable)
1089{
1090 if(!enable) {
1091 cacheInit();
1092 cacheDisable();
1093 } else {
1094 cacheInit();
1095 }
1096}
1097
91447636
A		 1098#pragma mark **** perfmon facility ****
1099
55e303ae
A		 1100__private_extern__
1101kern_return_t chudxnu_perfmon_acquire_facility(task_t task)
1102{
1103 return perfmon_acquire_facility(task);
1104}
1105
1106__private_extern__
1107kern_return_t chudxnu_perfmon_release_facility(task_t task)
1108{
1109 return perfmon_release_facility(task);
1110}
1111
91447636
A		 1112#pragma mark **** rupt counters ****
1113
55e303ae
A		 1114__private_extern__
1115kern_return_t chudxnu_get_cpu_rupt_counters(int cpu, rupt_counters_t *rupts)
1116{
1117 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
1118 return KERN_FAILURE;
1119 }
1120
1121 if(rupts) {
1122 boolean_t oldlevel = ml_set_interrupts_enabled(FALSE);
91447636 1123 struct per_proc_info *per_proc;
55e303ae 1124
91447636
A		 1125 per_proc = PerProcTable[cpu].ppe_vaddr;
1126 rupts->hwResets = per_proc->hwCtr.hwResets;
1127 rupts->hwMachineChecks = per_proc->hwCtr.hwMachineChecks;
1128 rupts->hwDSIs = per_proc->hwCtr.hwDSIs;
1129 rupts->hwISIs = per_proc->hwCtr.hwISIs;
1130 rupts->hwExternals = per_proc->hwCtr.hwExternals;
1131 rupts->hwAlignments = per_proc->hwCtr.hwAlignments;
1132 rupts->hwPrograms = per_proc->hwCtr.hwPrograms;
1133 rupts->hwFloatPointUnavailable = per_proc->hwCtr.hwFloatPointUnavailable;
1134 rupts->hwDecrementers = per_proc->hwCtr.hwDecrementers;
1135 rupts->hwIOErrors = per_proc->hwCtr.hwIOErrors;
1136 rupts->hwSystemCalls = per_proc->hwCtr.hwSystemCalls;
1137 rupts->hwTraces = per_proc->hwCtr.hwTraces;
1138 rupts->hwFloatingPointAssists = per_proc->hwCtr.hwFloatingPointAssists;
1139 rupts->hwPerformanceMonitors = per_proc->hwCtr.hwPerformanceMonitors;
1140 rupts->hwAltivecs = per_proc->hwCtr.hwAltivecs;
1141 rupts->hwInstBreakpoints = per_proc->hwCtr.hwInstBreakpoints;
1142 rupts->hwSystemManagements = per_proc->hwCtr.hwSystemManagements;
1143 rupts->hwAltivecAssists = per_proc->hwCtr.hwAltivecAssists;
1144 rupts->hwThermal = per_proc->hwCtr.hwThermal;
1145 rupts->hwSoftPatches = per_proc->hwCtr.hwSoftPatches;
1146 rupts->hwMaintenances = per_proc->hwCtr.hwMaintenances;
1147 rupts->hwInstrumentations = per_proc->hwCtr.hwInstrumentations;
55e303ae
A		 1148
1149 ml_set_interrupts_enabled(oldlevel);
1150 return KERN_SUCCESS;
1151 } else {
1152 return KERN_FAILURE;
1153 }
1154}
1155
1156__private_extern__
1157kern_return_t chudxnu_clear_cpu_rupt_counters(int cpu)
1158{
1159 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
1160 return KERN_FAILURE;
1161 }
1162
91447636 1163 bzero((char *)&(PerProcTable[cpu].ppe_vaddr->hwCtr), sizeof(struct hwCtrs));
55e303ae
A		 1164 return KERN_SUCCESS;
1165}
1166
91447636
A		 1167#pragma mark **** alignment exceptions ****
1168
55e303ae
A		 1169__private_extern__
1170kern_return_t chudxnu_passup_alignment_exceptions(boolean_t enable)
1171{
1172 if(enable) {
1173 dgWork.dgFlags |= enaNotifyEM;
1174 } else {
1175 dgWork.dgFlags &= ~enaNotifyEM;
1176 }
91447636
A		 1177 return KERN_SUCCESS;
1178}
1179
1180#pragma mark **** scom ****
1181kern_return_t chudxnu_scom_read(uint32_t reg, uint64_t *data)
1182{
1183 ml_scom_read(reg, data);
1184 return KERN_SUCCESS;
1185}
1186
1187kern_return_t chudxnu_scom_write(uint32_t reg, uint64_t data)
1188{
1189 ml_scom_write(reg, data);
1190 return KERN_SUCCESS;
55e303ae 1191}
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