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1c79356b 1/*
b0d623f7 2 * Copyright (c) 2000-2009 Apple Inc. All rights reserved.
1c79356b 3 *
2d21ac55 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
1c79356b 5 *
2d21ac55
A
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
8f6c56a5 14 *
2d21ac55
A
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
8f6c56a5
A
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
2d21ac55
A
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
8f6c56a5 25 *
2d21ac55 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
1c79356b
A
27 */
28/*
29 * @OSF_COPYRIGHT@
30 */
31
32#ifndef _I386_MACHINE_ROUTINES_H_
33#define _I386_MACHINE_ROUTINES_H_
34
35#include <mach/mach_types.h>
36#include <mach/boolean.h>
37#include <kern/kern_types.h>
38#include <pexpert/pexpert.h>
39
91447636 40#include <sys/cdefs.h>
9bccf70c 41#include <sys/appleapiopts.h>
1c79356b 42
91447636
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43__BEGIN_DECLS
44
b0d623f7
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45#ifdef XNU_KERNEL_PRIVATE
46
0c530ab8
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47/* are we a 64 bit platform ? */
48
49boolean_t ml_is64bit(void);
50
51/* is this a 64bit thread? */
52
53boolean_t ml_thread_is64bit(thread_t);
54
55/* is this a 64bit thread? */
56
57boolean_t ml_state_is64bit(void *);
58
59/* set state of fpu save area for signal handling */
60
61void ml_fp_setvalid(boolean_t);
62
63void ml_cpu_set_ldt(int);
64
1c79356b
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65/* Interrupt handling */
66
55e303ae
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67/* Initialize Interrupts */
68void ml_init_interrupt(void);
69
1c79356b
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70/* Generate a fake interrupt */
71void ml_cause_interrupt(void);
72
b0d623f7
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73/* Initialize Interrupts */
74void ml_install_interrupt_handler(
75 void *nub,
76 int source,
77 void *target,
78 IOInterruptHandler handler,
79 void *refCon);
80
9bccf70c 81void ml_get_timebase(unsigned long long *timestamp);
0c530ab8 82void ml_init_lock_timeout(void);
d52fe63f 83
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84vm_offset_t
85ml_static_ptovirt(
86 vm_offset_t);
87
88void ml_static_mfree(
89 vm_offset_t,
90 vm_size_t);
91
92/* boot memory allocation */
93vm_offset_t ml_static_malloc(
94 vm_size_t size);
95
96/* virtual to physical on wired pages */
97vm_offset_t ml_vtophys(
98 vm_offset_t vaddr);
99
100vm_size_t ml_nofault_copy(
101 vm_offset_t virtsrc, vm_offset_t virtdst, vm_size_t size);
102
103/* Machine topology info */
104uint64_t ml_cpu_cache_size(unsigned int level);
105uint64_t ml_cpu_cache_sharing(unsigned int level);
106
107/* Initialize the maximum number of CPUs */
108void ml_init_max_cpus(
109 unsigned long max_cpus);
110
111extern void ml_cpu_up(void);
112extern void ml_cpu_down(void);
113
114void bzero_phys_nc(
115 addr64_t phys_address,
116 uint32_t length);
117
118#if defined(PEXPERT_KERNEL_PRIVATE) || defined(MACH_KERNEL_PRIVATE)
119/* IO memory map services */
120
121/* Map memory map IO space */
122vm_offset_t ml_io_map(
123 vm_offset_t phys_addr,
124 vm_size_t size);
125
b0d623f7
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126
127void ml_get_bouncepool_info(
128 vm_offset_t *phys_addr,
129 vm_size_t *size);
060df5ea
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130/* Indicates if spinlock, IPI and other timeouts should be suspended */
131boolean_t machine_timeout_suspended(void);
b0d623f7
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132#endif /* PEXPERT_KERNEL_PRIVATE || MACH_KERNEL_PRIVATE */
133
6d2010ae
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134/* Warm up a CPU to receive an interrupt */
135kern_return_t ml_interrupt_prewarm(uint64_t deadline);
060df5ea 136
b0d623f7
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137#endif /* XNU_KERNEL_PRIVATE */
138
139#ifdef KERNEL_PRIVATE
140
55e303ae
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141/* Type for the Time Base Enable function */
142typedef void (*time_base_enable_t)(cpu_id_t cpu_id, boolean_t enable);
143
9bccf70c
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144/* Type for the IPI Hander */
145typedef void (*ipi_handler_t)(void);
146
55e303ae
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147/* Struct for ml_processor_register */
148struct ml_processor_info {
149 cpu_id_t cpu_id;
150 boolean_t boot_cpu;
151 vm_offset_t start_paddr;
152 boolean_t supports_nap;
153 unsigned long l2cr_value;
154 time_base_enable_t time_base_enable;
155};
156
157typedef struct ml_processor_info ml_processor_info_t;
158
91447636 159
9bccf70c 160/* Register a processor */
b0d623f7
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161kern_return_t
162ml_processor_register(
163 cpu_id_t cpu_id,
164 uint32_t lapic_id,
165 processor_t *processor_out,
166 boolean_t boot_cpu,
167 boolean_t start );
0c530ab8 168
43866e37
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169/* PCI config cycle probing */
170boolean_t ml_probe_read(
171 vm_offset_t paddr,
172 unsigned int *val);
55e303ae
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173boolean_t ml_probe_read_64(
174 addr64_t paddr,
175 unsigned int *val);
43866e37
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176
177/* Read physical address byte */
178unsigned int ml_phys_read_byte(
179 vm_offset_t paddr);
55e303ae
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180unsigned int ml_phys_read_byte_64(
181 addr64_t paddr);
43866e37
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182
183/* Read physical address half word */
184unsigned int ml_phys_read_half(
185 vm_offset_t paddr);
55e303ae
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186unsigned int ml_phys_read_half_64(
187 addr64_t paddr);
43866e37
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188
189/* Read physical address word*/
190unsigned int ml_phys_read(
191 vm_offset_t paddr);
55e303ae
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192unsigned int ml_phys_read_64(
193 addr64_t paddr);
43866e37
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194unsigned int ml_phys_read_word(
195 vm_offset_t paddr);
55e303ae
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196unsigned int ml_phys_read_word_64(
197 addr64_t paddr);
43866e37
A
198
199/* Read physical address double word */
200unsigned long long ml_phys_read_double(
201 vm_offset_t paddr);
55e303ae
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202unsigned long long ml_phys_read_double_64(
203 addr64_t paddr);
43866e37
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204
205/* Write physical address byte */
206void ml_phys_write_byte(
207 vm_offset_t paddr, unsigned int data);
55e303ae
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208void ml_phys_write_byte_64(
209 addr64_t paddr, unsigned int data);
43866e37
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210
211/* Write physical address half word */
212void ml_phys_write_half(
213 vm_offset_t paddr, unsigned int data);
55e303ae
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214void ml_phys_write_half_64(
215 addr64_t paddr, unsigned int data);
43866e37
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216
217/* Write physical address word */
218void ml_phys_write(
219 vm_offset_t paddr, unsigned int data);
55e303ae
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220void ml_phys_write_64(
221 addr64_t paddr, unsigned int data);
43866e37
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222void ml_phys_write_word(
223 vm_offset_t paddr, unsigned int data);
55e303ae
A
224void ml_phys_write_word_64(
225 addr64_t paddr, unsigned int data);
43866e37
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226
227/* Write physical address double word */
228void ml_phys_write_double(
229 vm_offset_t paddr, unsigned long long data);
55e303ae
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230void ml_phys_write_double_64(
231 addr64_t paddr, unsigned long long data);
43866e37 232
43866e37
A
233/* Struct for ml_cpu_get_info */
234struct ml_cpu_info {
6d2010ae
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235 uint32_t vector_unit;
236 uint32_t cache_line_size;
237 uint32_t l1_icache_size;
238 uint32_t l1_dcache_size;
239 uint32_t l2_settings;
240 uint32_t l2_cache_size;
241 uint32_t l3_settings;
242 uint32_t l3_cache_size;
43866e37
A
243};
244
245typedef struct ml_cpu_info ml_cpu_info_t;
246
247/* Get processor info */
91447636 248void ml_cpu_get_info(ml_cpu_info_t *ml_cpu_info);
43866e37 249
9bccf70c
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250void ml_thread_policy(
251 thread_t thread,
252 unsigned policy_id,
253 unsigned policy_info);
1c79356b 254
9bccf70c
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255#define MACHINE_GROUP 0x00000001
256#define MACHINE_NETWORK_GROUP 0x10000000
257#define MACHINE_NETWORK_WORKLOOP 0x00000001
258#define MACHINE_NETWORK_NETISR 0x00000002
1c79356b 259
43866e37
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260/* Return the maximum number of CPUs set by ml_init_max_cpus() */
261int ml_get_max_cpus(
262 void);
263
2d21ac55
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264/*
265 * The following are in pmCPU.c not machine_routines.c.
266 */
0c530ab8
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267extern void ml_set_maxsnoop(uint32_t maxdelay);
268extern unsigned ml_get_maxsnoop(void);
269extern void ml_set_maxbusdelay(uint32_t mdelay);
270extern uint32_t ml_get_maxbusdelay(void);
593a1d5f
A
271extern void ml_set_maxintdelay(uint64_t mdelay);
272extern uint64_t ml_get_maxintdelay(void);
6d2010ae 273extern boolean_t ml_get_interrupt_prewake_applicable(void);
2d21ac55
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274
275
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276extern uint64_t tmrCvt(uint64_t time, uint64_t conversion);
277
2d21ac55
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278extern uint64_t ml_cpu_int_event_time(void);
279
b0d623f7
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280#endif /* KERNEL_PRIVATE */
281
282/* Get Interrupts Enabled */
283boolean_t ml_get_interrupts_enabled(void);
284
285/* Set Interrupts Enabled */
286boolean_t ml_set_interrupts_enabled(boolean_t enable);
287
288/* Check if running at interrupt context */
289boolean_t ml_at_interrupt_context(void);
290
291/* Zero bytes starting at a physical address */
292void bzero_phys(
293 addr64_t phys_address,
294 uint32_t length);
295
296/* Bytes available on current stack */
297vm_offset_t ml_stack_remaining(void);
298
299#if CONFIG_COUNTERS
300void ml_get_csw_threads(thread_t * /*old*/, thread_t * /*new*/);
301#endif /* CONFIG_COUNTERS */
1c79356b 302
91447636
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303__END_DECLS
304
6d2010ae
A
305#ifdef XNU_KERNEL_PRIVATE
306boolean_t ml_fpu_avx_enabled(void);
307void interrupt_latency_tracker_setup(void);
308void interrupt_reset_latency_stats(void);
309void interrupt_populate_latency_stats(char *, unsigned);
060df5ea 310
6d2010ae 311#endif /* XNU_KERNEL_PRIVATE */
1c79356b 312#endif /* _I386_MACHINE_ROUTINES_H_ */