[apple/xnu.git] / osfmk / mach / ppc / processor_info.h

/*
 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_LICENSE_HEADER_START@
 * 
 * Copyright (c) 1999-2003 Apple Computer, Inc.  All Rights Reserved.
 * 
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this
 * file.
 * 
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 * 
 * @APPLE_LICENSE_HEADER_END@
 */
/*
 *	File:	mach/ppc/processor_info.h
 *
 *	Data structure definitions for ppc specific processor control
 */


#ifndef	_MACH_PPC_PROCESSOR_INFO_H_
#define _MACH_PPC_PROCESSOR_INFO_H_

#include <mach/machine.h>

/* processor_control command operations */
#define PROCESSOR_PM_SET_REGS     1     /* Set Performance Monitor Registers  */
#define PROCESSOR_PM_SET_MMCR     2     /* Set Monitor Mode Controls Registers  */
#define PROCESSOR_PM_CLR_PMC      3     /* Clear Performance Monitor Counter Registers */

/* 
 * Performance Monitor Register structures
 */

typedef union {
	unsigned int word;
	struct {
	        unsigned int dis	: 1;
		unsigned int dp 	: 1;
		unsigned int du 	: 1;
	        unsigned int dms	: 1;
	        unsigned int dmr	: 1;
	        unsigned int reserved3	: 1;        /* enint         */
	        unsigned int reserved4	: 1;        /* discount      */
	        unsigned int reserved5	: 2;        /* rtcselect     */
	        unsigned int reserved6	: 1;        /* intonbittrans */
	        unsigned int threshold	: 6;
	        unsigned int reserved7	: 1;        /* pmc1intcontrol */
	        unsigned int reserved8	: 1;        /* pmcintcontrol  */
	        unsigned int reserved9	: 1;        /* pmctrigger     */
	        unsigned int pmc1select	: 7;
	        unsigned int pmc2select	: 6;
	}bits;
}mmcr0_t;

typedef union {
	unsigned int word;
	struct {
	        unsigned int pmc3select	: 5;
	        unsigned int pmc4select	: 5;
	        unsigned int reserved	: 22;
	}bits;
}mmcr1_t;

typedef union {
	unsigned int word;
	struct {
	        unsigned int threshmult	 : 1;
	        unsigned int reserved	 : 31;
	}bits;
}mmcr2_t;

typedef union {
	unsigned int word;
	struct {
	        unsigned int ov : 1;        /* overflow value */
	        unsigned int cv : 31;       /* countervalue */
	}bits;
}pmcn_t;


/* Processor Performance Monitor Registers definitions */

struct processor_pm_regs {
      union {
	mmcr0_t mmcr0;
        mmcr1_t mmcr1;
        mmcr2_t mmcr2;
      }u;
      pmcn_t pmc[2];
};

typedef struct processor_pm_regs processor_pm_regs_data_t;
typedef struct processor_pm_regs *processor_pm_regs_t;
#define PROCESSOR_PM_REGS_COUNT \
        (sizeof(processor_pm_regs_data_t) / sizeof (unsigned int))

#define PROCESSOR_PM_REGS_COUNT_POWERPC_750 \
            (PROCESSOR_PM_REGS_COUNT * 2 )

#define PROCESSOR_PM_REGS_COUNT_POWERPC_7400 \
            (PROCESSOR_PM_REGS_COUNT * 3 )

typedef unsigned int processor_temperature_data_t;
typedef unsigned int *processor_temperature_t;

#define PROCESSOR_TEMPERATURE_COUNT 1

union processor_control_data {
        processor_pm_regs_data_t cmd_pm_regs[3];
};

struct processor_control_cmd {
    integer_t      cmd_op;
    cpu_type_t     cmd_cpu_type;
    cpu_subtype_t  cmd_cpu_subtype;
    union processor_control_data u;
};

typedef struct processor_control_cmd   processor_control_cmd_data_t;
typedef struct processor_control_cmd   *processor_control_cmd_t;
#define cmd_pm_regs u.cmd_pm_regs;
#define cmd_pm_ctls u.cmd_pm_ctls;

#define PROCESSOR_CONTROL_CMD_COUNT \
    (((sizeof(processor_control_cmd_data_t)) - \
      (sizeof(union processor_control_data))) / sizeof (integer_t))

     /* x should be a processor_pm_regs_t */
#define PERFMON_MMCR0(x)    ((x)[0].u.mmcr0.word)
#define PERFMON_PMC1(x)     ((x)[0].pmc[0].word)
#define PERFMON_PMC2(x)     ((x)[0].pmc[1].word)
#define PERFMON_MMCR1(x)    ((x)[1].u.mmcr1.word)
#define PERFMON_PMC3(x)     ((x)[1].pmc[0].word)
#define PERFMON_PMC4(x)     ((x)[1].pmc[1].word)
#define PERFMON_MMCR2(x)    ((x)[2].u.mmcr2.word)

#define PERFMON_DIS(x)           ((x)[0].u.mmcr0.bits.dis)
#define PERFMON_DP(x)            ((x)[0].u.mmcr0.bits.dp)
#define PERFMON_DU(x)            ((x)[0].u.mmcr0.bits.du)
#define PERFMON_DMS(x)           ((x)[0].u.mmcr0.bits.dms)
#define PERFMON_DMR(x)           ((x)[0].u.mmcr0.bits.dmr)
#define PERFMON_THRESHOLD(x)     ((x)[0].u.mmcr0.bits.threshold)
#define PERFMON_PMC1SELECT(x)    ((x)[0].u.mmcr0.bits.pmc1select)
#define PERFMON_PMC2SELECT(x)    ((x)[0].u.mmcr0.bits.pmc2select)
#define PERFMON_PMC3SELECT(x)    ((x)[1].u.mmcr1.bits.pmc3select)
#define PERFMON_PMC4SELECT(x)    ((x)[1].u.mmcr1.bits.pmc4select)
#define PERFMON_THRESHMULT(x)    ((x)[2].u.mmcr2.bits.threshmult)
#define PERFMON_PMC1_CV(x)       ((x)[0].u.pmc[0].bits.cv)
#define PERFMON_PMC2_CV(x)       ((x)[0].u.pmc[1].bits.cv)
#define PERFMON_PMC3_CV(x)       ((x)[1].u.pmc[0].bits.cv)
#define PERFMON_PMC4_CV(x)       ((x)[1].u.pmc[1].bits.cv)

#endif	/* _MACH_PPC_PROCESSOR_INFO_H_ */
Commit	Line	Data
1c79356b A	1	/*
	2	* Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
	3	*
	4	* @APPLE_LICENSE_HEADER_START@
	5	*
43866e37	6	* Copyright (c) 1999-2003 Apple Computer, Inc. All Rights Reserved.
1c79356b	7	*
43866e37 A	8	* This file contains Original Code and/or Modifications of Original Code
	9	* as defined in and that are subject to the Apple Public Source License
	10	* Version 2.0 (the 'License'). You may not use this file except in
	11	* compliance with the License. Please obtain a copy of the License at
	12	* http://www.opensource.apple.com/apsl/ and read it before using this
	13	* file.
	14	*
	15	* The Original Code and all software distributed under the License are
	16	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
1c79356b A	17	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
1c79356b A	18	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
43866e37 A	19	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	20	* Please see the License for the specific language governing rights and
	21	* limitations under the License.
1c79356b A	22	*
	23	* @APPLE_LICENSE_HEADER_END@
	24	*/
	25	/*
	26	* File: mach/ppc/processor_info.h
	27	*
	28	* Data structure definitions for ppc specific processor control
	29	*/
	30
	31
	32	#ifndef _MACH_PPC_PROCESSOR_INFO_H_
	33	#define _MACH_PPC_PROCESSOR_INFO_H_
	34
	35	#include <mach/machine.h>
	36
	37	/* processor_control command operations */
	38	#define PROCESSOR_PM_SET_REGS 1 /* Set Performance Monitor Registers */
	39	#define PROCESSOR_PM_SET_MMCR 2 /* Set Monitor Mode Controls Registers */
	40	#define PROCESSOR_PM_CLR_PMC 3 /* Clear Performance Monitor Counter Registers */
	41
	42	/*
	43	* Performance Monitor Register structures
	44	*/
	45
	46	typedef union {
	47	unsigned int word;
	48	struct {
	49	unsigned int dis : 1;
	50	unsigned int dp : 1;
	51	unsigned int du : 1;
	52	unsigned int dms : 1;
	53	unsigned int dmr : 1;
	54	unsigned int reserved3 : 1; /* enint */
	55	unsigned int reserved4 : 1; /* discount */
	56	unsigned int reserved5 : 2; /* rtcselect */
	57	unsigned int reserved6 : 1; /* intonbittrans */
	58	unsigned int threshold : 6;
	59	unsigned int reserved7 : 1; /* pmc1intcontrol */
	60	unsigned int reserved8 : 1; /* pmcintcontrol */
	61	unsigned int reserved9 : 1; /* pmctrigger */
	62	unsigned int pmc1select : 7;
	63	unsigned int pmc2select : 6;
	64	}bits;
	65	}mmcr0_t;
	66
	67	typedef union {
	68	unsigned int word;
	69	struct {
	70	unsigned int pmc3select : 5;
	71	unsigned int pmc4select : 5;
	72	unsigned int reserved : 22;
	73	}bits;
	74	}mmcr1_t;
	75
	76	typedef union {
	77	unsigned int word;
	78	struct {
	79	unsigned int threshmult : 1;
	80	unsigned int reserved : 31;
	81	}bits;
	82	}mmcr2_t;
	83
	84	typedef union {
	85	unsigned int word;
86	struct {
87	unsigned int ov : 1; /* overflow value */
88	unsigned int cv : 31; /* countervalue */
89	}bits;
90	}pmcn_t;
91
92
93
94	/* Processor Performance Monitor Registers definitions */
95
96	struct processor_pm_regs {
97	union {
98	mmcr0_t mmcr0;
99	mmcr1_t mmcr1;
100	mmcr2_t mmcr2;
101	}u;
102	pmcn_t pmc[2];
103	};
104
105	typedef struct processor_pm_regs processor_pm_regs_data_t;
106	typedef struct processor_pm_regs *processor_pm_regs_t;
107	#define PROCESSOR_PM_REGS_COUNT \
108	(sizeof(processor_pm_regs_data_t) / sizeof (unsigned int))
109
1c79356b A	110	#define PROCESSOR_PM_REGS_COUNT_POWERPC_750 \
	111	(PROCESSOR_PM_REGS_COUNT * 2 )
	112
	113	#define PROCESSOR_PM_REGS_COUNT_POWERPC_7400 \
	114	(PROCESSOR_PM_REGS_COUNT * 3 )
	115
	116	typedef unsigned int processor_temperature_data_t;
	117	typedef unsigned int *processor_temperature_t;
	118
	119	#define PROCESSOR_TEMPERATURE_COUNT 1
	120
	121	union processor_control_data {
	122	processor_pm_regs_data_t cmd_pm_regs[3];
	123	};
	124
	125	struct processor_control_cmd {
	126	integer_t cmd_op;
	127	cpu_type_t cmd_cpu_type;
	128	cpu_subtype_t cmd_cpu_subtype;
	129	union processor_control_data u;
	130	};
	131
	132	typedef struct processor_control_cmd processor_control_cmd_data_t;
	133	typedef struct processor_control_cmd *processor_control_cmd_t;
	134	#define cmd_pm_regs u.cmd_pm_regs;
	135	#define cmd_pm_ctls u.cmd_pm_ctls;
	136
	137	#define PROCESSOR_CONTROL_CMD_COUNT \
	138	(((sizeof(processor_control_cmd_data_t)) - \
	139	(sizeof(union processor_control_data))) / sizeof (integer_t))
	140
	141	/* x should be a processor_pm_regs_t */
	142	#define PERFMON_MMCR0(x) ((x)[0].u.mmcr0.word)
	143	#define PERFMON_PMC1(x) ((x)[0].pmc[0].word)
	144	#define PERFMON_PMC2(x) ((x)[0].pmc[1].word)
	145	#define PERFMON_MMCR1(x) ((x)[1].u.mmcr1.word)
	146	#define PERFMON_PMC3(x) ((x)[1].pmc[0].word)
	147	#define PERFMON_PMC4(x) ((x)[1].pmc[1].word)
	148	#define PERFMON_MMCR2(x) ((x)[2].u.mmcr2.word)
	149
	150	#define PERFMON_DIS(x) ((x)[0].u.mmcr0.bits.dis)
	151	#define PERFMON_DP(x) ((x)[0].u.mmcr0.bits.dp)
	152	#define PERFMON_DU(x) ((x)[0].u.mmcr0.bits.du)
	153	#define PERFMON_DMS(x) ((x)[0].u.mmcr0.bits.dms)
	154	#define PERFMON_DMR(x) ((x)[0].u.mmcr0.bits.dmr)
	155	#define PERFMON_THRESHOLD(x) ((x)[0].u.mmcr0.bits.threshold)
	156	#define PERFMON_PMC1SELECT(x) ((x)[0].u.mmcr0.bits.pmc1select)
	157	#define PERFMON_PMC2SELECT(x) ((x)[0].u.mmcr0.bits.pmc2select)
	158	#define PERFMON_PMC3SELECT(x) ((x)[1].u.mmcr1.bits.pmc3select)
	159	#define PERFMON_PMC4SELECT(x) ((x)[1].u.mmcr1.bits.pmc4select)
	160	#define PERFMON_THRESHMULT(x) ((x)[2].u.mmcr2.bits.threshmult)
	161	#define PERFMON_PMC1_CV(x) ((x)[0].u.pmc[0].bits.cv)
	162	#define PERFMON_PMC2_CV(x) ((x)[0].u.pmc[1].bits.cv)
	163	#define PERFMON_PMC3_CV(x) ((x)[1].u.pmc[0].bits.cv)
	164	#define PERFMON_PMC4_CV(x) ((x)[1].u.pmc[1].bits.cv)
	165
	166	#endif /* _MACH_PPC_PROCESSOR_INFO_H_ */
	167