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1 | /* |
2 | * Copyright (c) 2000 Apple Computer, Inc. All rights reserved. | |
3 | * | |
2d21ac55 | 4 | * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ |
55e303ae | 5 | * |
2d21ac55 A |
6 | * This file contains Original Code and/or Modifications of Original Code |
7 | * as defined in and that are subject to the Apple Public Source License | |
8 | * Version 2.0 (the 'License'). You may not use this file except in | |
9 | * compliance with the License. The rights granted to you under the License | |
10 | * may not be used to create, or enable the creation or redistribution of, | |
11 | * unlawful or unlicensed copies of an Apple operating system, or to | |
12 | * circumvent, violate, or enable the circumvention or violation of, any | |
13 | * terms of an Apple operating system software license agreement. | |
8f6c56a5 | 14 | * |
2d21ac55 A |
15 | * Please obtain a copy of the License at |
16 | * http://www.opensource.apple.com/apsl/ and read it before using this file. | |
17 | * | |
18 | * The Original Code and all software distributed under the License are | |
19 | * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER | |
8f6c56a5 A |
20 | * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, |
21 | * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, | |
2d21ac55 A |
22 | * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. |
23 | * Please see the License for the specific language governing rights and | |
24 | * limitations under the License. | |
8f6c56a5 | 25 | * |
2d21ac55 | 26 | * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ |
55e303ae A |
27 | */ |
28 | #ifndef _HW_PERFMON_H_ | |
29 | #define _HW_PERFMON_H_ | |
30 | ||
31 | #ifndef __ppc__ | |
32 | #error This file is only useful on PowerPC. | |
33 | #endif | |
34 | ||
35 | #define MAX_CPUPMC_COUNT 8 | |
36 | ||
37 | #define PMC_1 0 | |
38 | #define PMC_2 1 | |
39 | #define PMC_3 2 | |
40 | #define PMC_4 3 | |
41 | #define PMC_5 4 | |
42 | #define PMC_6 5 | |
43 | #define PMC_7 6 | |
44 | #define PMC_8 7 | |
45 | ||
46 | /* these actions can be combined and simultaneously performed with a single call to perfmon_control() */ | |
47 | typedef enum { | |
48 | PPC_PERFMON_CLEAR_COUNTERS = 0x0002, | |
49 | PPC_PERFMON_START_COUNTERS = 0x0004, | |
50 | PPC_PERFMON_STOP_COUNTERS = 0x0008, | |
51 | PPC_PERFMON_READ_COUNTERS = 0x0010, | |
52 | PPC_PERFMON_WRITE_COUNTERS = 0x0020 | |
53 | } perfmon_multi_action_t; | |
54 | ||
55 | /* these actions can not be combined and each requires a separate call to perfmon_control() */ | |
56 | typedef enum { | |
57 | PPC_PERFMON_ENABLE = 0x00010000, | |
58 | PPC_PERFMON_DISABLE = 0x00020000, | |
59 | PPC_PERFMON_SET_EVENT = 0x00030000, | |
60 | PPC_PERFMON_SET_THRESHOLD = 0x00040000, | |
61 | PPC_PERFMON_SET_TBSEL = 0x00050000, | |
62 | PPC_PERFMON_SET_EVENT_FUNC = 0x00060000, | |
63 | PPC_PERFMON_ENABLE_PMI_BRKPT = 0x00070000 | |
64 | } perfmon_single_action_t; | |
65 | ||
66 | /* used to select byte lane and speculative events (currently 970 only) */ | |
67 | typedef enum { /* SPECSEL[0:1] TD_CP_DBGxSEL[0:1] TTM3SEL[0:1] TTM1SEL[0:1] TTM0SEL[0:1] */ | |
68 | PPC_PERFMON_FUNC_FPU = 0, /* 00 00 00 00 00 */ | |
69 | PPC_PERFMON_FUNC_ISU = 1, /* 00 00 00 00 01 */ | |
70 | PPC_PERFMON_FUNC_IFU = 2, /* 00 00 00 00 10 */ | |
71 | PPC_PERFMON_FUNC_VMX = 3, /* 00 00 00 00 11 */ | |
72 | PPC_PERFMON_FUNC_IDU = 64, /* 00 01 00 00 00 */ | |
73 | PPC_PERFMON_FUNC_GPS = 76, /* 00 01 00 11 00 */ | |
74 | PPC_PERFMON_FUNC_LSU0 = 128, /* 00 10 00 00 00 */ | |
75 | PPC_PERFMON_FUNC_LSU1A = 192, /* 00 11 00 00 00 */ | |
76 | PPC_PERFMON_FUNC_LSU1B = 240, /* 00 11 11 00 00 */ | |
77 | PPC_PERFMON_FUNC_SPECA = 256, /* 01 00 00 00 00 */ | |
78 | PPC_PERFMON_FUNC_SPECB = 512, /* 10 00 00 00 00 */ | |
79 | PPC_PERFMON_FUNC_SPECC = 768, /* 11 00 00 00 00 */ | |
80 | } perfmon_functional_unit_t; | |
81 | ||
82 | #ifdef MACH_KERNEL_PRIVATE | |
83 | int perfmon_acquire_facility(task_t task); | |
84 | int perfmon_release_facility(task_t task); | |
85 | ||
91447636 | 86 | extern int perfmon_disable(thread_t thr_act); |
55e303ae A |
87 | extern int perfmon_init(void); |
88 | extern int perfmon_control(struct savearea *save); | |
89 | extern int perfmon_handle_pmi(struct savearea *ssp); | |
90 | ||
91 | /* perfmonFlags */ | |
92 | #define PERFMONFLAG_BREAKPOINT_FOR_PMI 0x1 | |
93 | ||
94 | #endif /* MACH_KERNEL_PRIVATE */ | |
95 | ||
96 | /* | |
97 | * From user space: | |
98 | * | |
99 | * int perfmon_control(thread_t thread, perfmon_action_t action, int pmc, u_int32_t val, u_int64_t *pmcs); | |
100 | * | |
101 | * r3: thread | |
102 | * r4: action | |
103 | * r5: pmc | |
104 | * r6: event/threshold/tbsel/count | |
105 | * r7: pointer to space for PMC counts: uint64_t[MAX_CPUPMC_COUNT] | |
106 | * | |
107 | * perfmon_control(thread, PPC_PERFMON_CLEAR_COUNTERS, 0, 0, NULL); | |
108 | * perfmon_control(thread, PPC_PERFMON_START_COUNTERS, 0, 0, NULL); | |
109 | * perfmon_control(thread, PPC_PERFMON_STOP_COUNTERS, 0, 0, NULL); | |
110 | * perfmon_control(thread, PPC_PERFMON_READ_COUNTERS, 0, 0, uint64_t *pmcs); | |
111 | * perfmon_control(thread, PPC_PERFMON_WRITE_COUNTERS, 0, 0, uint64_t *pmcs); | |
112 | * perfmon_control(thread, PPC_PERFMON_ENABLE, 0, 0, NULL); | |
113 | * perfmon_control(thread, PPC_PERFMON_DISABLE, 0, 0, NULL); | |
114 | * perfmon_control(thread, PPC_PERFMON_SET_EVENT, int pmc, int event, NULL); | |
115 | * perfmon_control(thread, PPC_PERFMON_SET_THRESHOLD, 0, int threshold, NULL); | |
116 | * perfmon_control(thread, PPC_PERFMON_SET_TBSEL, 0, int tbsel, NULL); | |
117 | * perfmon_control(thread, PPC_PERFMON_SET_EVENT_FUNC, 0, perfmon_functional_unit_t func, NULL); | |
118 | * perfmon_control(thread, PPC_PERFMON_ENABLE_PMI_BRKPT, 0, boolean_t enable, NULL); | |
119 | * | |
120 | */ | |
121 | ||
122 | #endif /* _HW_PERFMON_H_ */ |