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1 | /* |
2 | * Copyright (c) 2000 Apple Computer, Inc. All rights reserved. | |
3 | * | |
8f6c56a5 | 4 | * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ |
1c79356b | 5 | * |
8f6c56a5 A |
6 | * This file contains Original Code and/or Modifications of Original Code |
7 | * as defined in and that are subject to the Apple Public Source License | |
8 | * Version 2.0 (the 'License'). You may not use this file except in | |
9 | * compliance with the License. The rights granted to you under the License | |
10 | * may not be used to create, or enable the creation or redistribution of, | |
11 | * unlawful or unlicensed copies of an Apple operating system, or to | |
12 | * circumvent, violate, or enable the circumvention or violation of, any | |
13 | * terms of an Apple operating system software license agreement. | |
14 | * | |
15 | * Please obtain a copy of the License at | |
16 | * http://www.opensource.apple.com/apsl/ and read it before using this file. | |
17 | * | |
18 | * The Original Code and all software distributed under the License are | |
19 | * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER | |
20 | * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, | |
21 | * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, | |
22 | * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. | |
23 | * Please see the License for the specific language governing rights and | |
8ad349bb | 24 | * limitations under the License. |
8f6c56a5 A |
25 | * |
26 | * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ | |
1c79356b A |
27 | */ |
28 | /* | |
29 | * @OSF_COPYRIGHT@ | |
30 | */ | |
31 | /* | |
32 | * Mach Operating System | |
33 | * Copyright (c) 1991 Carnegie Mellon University | |
34 | * All Rights Reserved. | |
35 | * | |
36 | * Permission to use, copy, modify and distribute this software and its | |
37 | * documentation is hereby granted, provided that both the copyright | |
38 | * notice and this permission notice appear in all copies of the | |
39 | * software, derivative works or modified versions, and any portions | |
40 | * thereof, and that both notices appear in supporting documentation. | |
41 | * | |
42 | * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" | |
43 | * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR | |
44 | * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. | |
45 | * | |
46 | * Carnegie Mellon requests users of this software to return to | |
47 | * | |
48 | * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU | |
49 | * School of Computer Science | |
50 | * Carnegie Mellon University | |
51 | * Pittsburgh PA 15213-3890 | |
52 | * | |
53 | * any improvements or extensions that they make and grant Carnegie Mellon | |
54 | * the rights to redistribute these changes. | |
55 | */ | |
56 | ||
57 | /* | |
58 | */ | |
59 | ||
60 | #ifndef _I386_FPU_H_ | |
61 | #define _I386_FPU_H_ | |
62 | ||
63 | /* | |
64 | * Macro definitions for routines to manipulate the | |
65 | * floating-point processor. | |
66 | */ | |
4452a7af | 67 | #include <kern/thread.h> |
1c79356b A |
68 | #include <i386/thread.h> |
69 | #include <kern/kern_types.h> | |
70 | #include <mach/i386/kern_return.h> | |
71 | #include <mach/i386/thread_status.h> | |
4452a7af A |
72 | #include <i386/proc_reg.h> |
73 | ||
74 | extern int fp_kind; | |
75 | ||
76 | extern void init_fpu(void); | |
77 | extern void fpu_module_init(void); | |
78 | extern void fpu_free( | |
79 | struct x86_fpsave_state * fps); | |
80 | extern kern_return_t fpu_set_fxstate( | |
81 | thread_t thr_act, | |
82 | thread_state_t state); | |
83 | extern kern_return_t fpu_get_fxstate( | |
84 | thread_t thr_act, | |
85 | thread_state_t state); | |
86 | extern void fpu_dup_fxstate( | |
87 | thread_t parent, | |
88 | thread_t child); | |
89 | extern void fpnoextflt(void); | |
90 | extern void fpextovrflt(void); | |
91 | extern void fpexterrflt(void); | |
92 | extern void fpSSEexterrflt(void); | |
93 | extern void fpflush(thread_t); | |
94 | extern void fp_setvalid(boolean_t); | |
95 | extern void fxsave64(struct x86_fx_save *); | |
96 | extern void fxrstor64(struct x86_fx_save *); | |
1c79356b A |
97 | |
98 | /* | |
99 | * FPU instructions. | |
100 | */ | |
101 | #define fninit() \ | |
102 | __asm__ volatile("fninit") | |
103 | ||
104 | #define fnstcw(control) \ | |
105 | __asm__("fnstcw %0" : "=m" (*(unsigned short *)(control))) | |
106 | ||
107 | #define fldcw(control) \ | |
108 | __asm__ volatile("fldcw %0" : : "m" (*(unsigned short *) &(control)) ) | |
109 | ||
110 | extern unsigned short fnstsw(void); | |
111 | ||
112 | extern __inline__ unsigned short fnstsw(void) | |
113 | { | |
114 | unsigned short status; | |
115 | __asm__ volatile("fnstsw %0" : "=ma" (status)); | |
116 | return(status); | |
117 | } | |
118 | ||
119 | #define fnclex() \ | |
120 | __asm__ volatile("fnclex") | |
121 | ||
55e303ae | 122 | #define fnsave(state) \ |
1c79356b A |
123 | __asm__ volatile("fnsave %0" : "=m" (*state)) |
124 | ||
125 | #define frstor(state) \ | |
126 | __asm__ volatile("frstor %0" : : "m" (state)) | |
127 | ||
128 | #define fwait() \ | |
129 | __asm__("fwait"); | |
130 | ||
55e303ae A |
131 | #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) |
132 | #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) | |
133 | ||
134 | #define FXSAFE() (fp_kind == FP_FXSR) | |
1c79356b | 135 | |
4452a7af A |
136 | |
137 | static inline void clear_fpu(void) | |
138 | { | |
139 | set_ts(); | |
140 | } | |
1c79356b A |
141 | |
142 | /* | |
143 | * Save thread`s FPU context. | |
1c79356b | 144 | */ |
1c79356b | 145 | |
4452a7af A |
146 | static inline void fpu_save_context(thread_t thread) |
147 | { | |
148 | struct x86_fpsave_state *ifps; | |
149 | ||
150 | assert(ml_get_interrupts_enabled() == FALSE); | |
151 | ifps = (thread)->machine.pcb->ifps; | |
152 | if (ifps != 0 && !ifps->fp_valid) { | |
153 | /* Clear CR0.TS in preparation for the FP context save. In | |
154 | * theory, this shouldn't be necessary since a live FPU should | |
155 | * indicate that TS is clear. However, various routines | |
156 | * (such as sendsig & sigreturn) manipulate TS directly. | |
157 | */ | |
158 | clear_ts(); | |
159 | /* registers are in FPU - save to memory */ | |
160 | ifps->fp_valid = TRUE; | |
161 | if (!thread_is_64bit(thread) || is_saved_state32(thread->machine.pcb->iss)) { | |
162 | /* save the compatibility/legacy mode XMM+x87 state */ | |
163 | fxsave(&ifps->fx_save_state); | |
164 | ifps->fp_save_layout = FXSAVE32; | |
165 | } | |
166 | else { | |
167 | /* Execute a brief jump to 64-bit mode to save the 64 | |
168 | * bit state | |
169 | */ | |
170 | fxsave64(&ifps->fx_save_state); | |
171 | ifps->fp_save_layout = FXSAVE64; | |
172 | } | |
173 | } | |
174 | set_ts(); | |
175 | } | |
1c79356b A |
176 | |
177 | #endif /* _I386_FPU_H_ */ |