[apple/xnu.git] / osfmk / chud / ppc / chud_cpu_asm.s

/*
 * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
 * 
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. The rights granted to you under the License
 * may not be used to create, or enable the creation or redistribution of,
 * unlawful or unlicensed copies of an Apple operating system, or to
 * circumvent, violate, or enable the circumvention or violation of, any
 * terms of an Apple operating system software license agreement.
 * 
 * Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this file.
 * 
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 * 
 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
 */
 
#define ASSEMBLER
#include <chud/ppc/chud_spr.h>
#include <ppc/asm.h>
#include <mach/kern_return.h>

/*
 * kern_return_t mfspr64(uint64_t *val, int spr);
 * 
 * r3: address to store value in
 * r4: spr to read from
 *
 */
 
;           Force a line boundry here
            .align  5
            .globl  EXT(mfspr64)

EXT(mfspr64):
            ;; generic PPC 64-bit wide SPRs
            cmpwi	r4,chud_ppc_srr0
            beq		mfspr64_srr0
            cmpwi	r4,chud_ppc_srr1
            beq		mfspr64_srr1
            cmpwi	r4,chud_ppc_dar
            beq		mfspr64_dar
            cmpwi	r4,chud_ppc_sdr1
            beq		mfspr64_sdr1
            cmpwi	r4,chud_ppc_sprg0
            beq		mfspr64_sprg0       
            cmpwi	r4,chud_ppc_sprg1
            beq		mfspr64_sprg1  
            cmpwi	r4,chud_ppc_sprg2
            beq		mfspr64_sprg2  
            cmpwi	r4,chud_ppc_sprg3
            beq		mfspr64_sprg3
            cmpwi	r4,chud_ppc64_asr
            beq		mfspr64_asr
            cmpwi	r4,chud_ppc_dabr
            beq		mfspr64_dabr
            
            ;; GPUL specific 64-bit wide SPRs
            cmpwi	r4,chud_970_hid0
            beq		mfspr64_hid0
            cmpwi	r4,chud_970_hid1
            beq		mfspr64_hid1
            cmpwi	r4,chud_970_hid4
            beq		mfspr64_hid4
            cmpwi	r4,chud_970_hid5
            beq		mfspr64_hid5       
            cmpwi	r4,chud_970_mmcr0
            beq		mfspr64_mmcr0            
            cmpwi	r4,chud_970_mmcr1
            beq		mfspr64_mmcr1
            cmpwi	r4,chud_970_mmcra
            beq		mfspr64_mmcra
            cmpwi	r4,chud_970_siar
            beq		mfspr64_siar
            cmpwi	r4,chud_970_sdar
            beq		mfspr64_sdar
            cmpwi	r4,chud_970_imc
            beq		mfspr64_imc
            cmpwi	r4,chud_970_rmor
            beq		mfspr64_rmor
            cmpwi	r4,chud_970_hrmor
            beq		mfspr64_hrmor
            cmpwi	r4,chud_970_hior
            beq		mfspr64_hior
            cmpwi	r4,chud_970_lpidr
            beq		mfspr64_lpidr
            cmpwi	r4,chud_970_lpcr
            beq		mfspr64_lpcr
            cmpwi	r4,chud_970_dabrx
            beq		mfspr64_dabrx
            cmpwi	r4,chud_970_hsprg0
            beq		mfspr64_hsprg0
            cmpwi	r4,chud_970_hsprg1
            beq		mfspr64_hsprg1
            cmpwi	r4,chud_970_hsrr0
            beq		mfspr64_hsrr0
            cmpwi	r4,chud_970_hsrr1
            beq		mfspr64_hsrr1
            cmpwi	r4,chud_970_hdec
            beq		mfspr64_hdec
            cmpwi	r4,chud_970_trig0
            beq		mfspr64_trig0
            cmpwi	r4,chud_970_trig1
            beq		mfspr64_trig1
            cmpwi	r4,chud_970_trig2
            beq		mfspr64_trig2
            cmpwi	r4,chud_ppc64_accr
            beq		mfspr64_accr
            cmpwi	r4,chud_970_scomc
            beq		mfspr64_scomc
            cmpwi	r4,chud_970_scomd
            beq		mfspr64_scomd
                                                                                                                                                            
            b		mfspr64_failure
            
mfspr64_srr0:
            mfspr	r5,chud_ppc_srr0
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_srr1:
            mfspr	r5,chud_ppc_srr1
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_dar:
            mfspr	r5,chud_ppc_dar
            std		r5,0(r3)
            b		mfspr64_success          
mfspr64_sdr1:
            mfspr	r5,chud_ppc_sdr1
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_sprg0:
            mfspr	r5,chud_ppc_sprg0
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_sprg1:
            mfspr	r5,chud_ppc_sprg1
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_sprg2:
            mfspr	r5,chud_ppc_sprg2
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_sprg3:
            mfspr	r5,chud_ppc_sprg3
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_asr:
            mfspr	r5,chud_ppc64_asr
            std		r5,0(r3)
            b		mfspr64_success             
mfspr64_dabr:
            mfspr	r5,chud_ppc_dabr
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_hid0:
            mfspr	r5,chud_970_hid0
            std		r5,0(r3)
            b		mfspr64_success            
mfspr64_hid1:
            mfspr	r5,chud_970_hid1
            std		r5,0(r3)
            b		mfspr64_success     
mfspr64_hid4:
            mfspr	r5,chud_970_hid4
            std		r5,0(r3)
            b		mfspr64_success             
mfspr64_hid5:
            mfspr	r5,chud_970_hid5
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_mmcr0:
            mfspr	r5,chud_970_mmcr0
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_mmcr1:
            mfspr	r5,chud_970_mmcr1
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_mmcra:
            mfspr	r5,chud_970_mmcra
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_siar:
            mfspr	r5,chud_970_siar
            std		r5,0(r3)
            b		mfspr64_success            
mfspr64_sdar:
            mfspr	r5,chud_970_sdar
            std		r5,0(r3)
            b		mfspr64_success              
mfspr64_imc:
            mfspr	r5,chud_970_imc
            std		r5,0(r3)
            b		mfspr64_success                          
mfspr64_rmor:
            mfspr	r5,chud_970_rmor
            std		r5,0(r3)
            b		mfspr64_success              
mfspr64_hrmor:
            mfspr	r5,chud_970_hrmor
            std		r5,0(r3)
            b		mfspr64_success  
mfspr64_hior:
            mfspr	r5,chud_970_hior
            std		r5,0(r3)
            b		mfspr64_success  
mfspr64_lpidr:
            mfspr	r5,chud_970_lpidr
            std		r5,0(r3)
            b		mfspr64_success   
mfspr64_lpcr:
            mfspr	r5,chud_970_lpcr
            std		r5,0(r3)
            b		mfspr64_success  
mfspr64_dabrx:
            mfspr	r5,chud_970_dabrx
            std		r5,0(r3)
            b		mfspr64_success  
mfspr64_hsprg0:
            mfspr	r5,chud_970_hsprg0
            std		r5,0(r3)
            b		mfspr64_success   
mfspr64_hsprg1:
            mfspr	r5,chud_970_hsprg1
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_hsrr0:
            mfspr	r5,chud_970_hsrr0
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_hsrr1:
            mfspr	r5,chud_970_hsrr1
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_hdec:
            mfspr	r5,chud_970_hdec
            std		r5,0(r3)
            b		mfspr64_success             
mfspr64_trig0:
            mfspr	r5,chud_970_trig0
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_trig1:
            mfspr	r5,chud_970_trig1
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_trig2:
            mfspr	r5,chud_970_trig2
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_accr:
            mfspr	r5,chud_ppc64_accr
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_scomc:
            mfspr	r5,chud_970_scomc
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_scomd:
            mfspr	r5,chud_970_scomd
            std		r5,0(r3)
            b		mfspr64_success
            
mfspr64_failure:
            li		r3,KERN_FAILURE
            blr
            
mfspr64_success:
            li		r3,KERN_SUCCESS
            blr


/*
 * kern_return_t mtspr64(int spr, uint64_t *val);
 * 
 * r3: spr to write to
 * r4: address to get value from
 *
 */
 
;           Force a line boundry here
            .align  5
            .globl  EXT(mtspr64)

EXT(mtspr64):
            ;; generic PPC 64-bit wide SPRs
            cmpwi	r3,chud_ppc_srr0
            beq		mtspr64_srr0
            cmpwi	r3,chud_ppc_srr1
            beq		mtspr64_srr1
            cmpwi	r3,chud_ppc_dar
            beq		mtspr64_dar
            cmpwi	r3,chud_ppc_sdr1
            beq		mtspr64_sdr1
            cmpwi	r3,chud_ppc_sprg0
            beq		mtspr64_sprg0       
            cmpwi	r3,chud_ppc_sprg1
            beq		mtspr64_sprg1  
            cmpwi	r3,chud_ppc_sprg2
            beq		mtspr64_sprg2  
            cmpwi	r3,chud_ppc_sprg3
            beq		mtspr64_sprg3
            cmpwi	r3,chud_ppc64_asr
            beq		mtspr64_asr
            cmpwi	r3,chud_ppc_dabr
            beq		mtspr64_dabr
            
            ;; GPUL specific 64-bit wide SPRs
            cmpwi	r3,chud_970_hid0
            beq		mtspr64_hid0
            cmpwi	r3,chud_970_hid1
            beq		mtspr64_hid1
            cmpwi	r3,chud_970_hid4
            beq		mtspr64_hid4
            cmpwi	r3,chud_970_hid5
            beq		mtspr64_hid5       
            cmpwi	r3,chud_970_mmcr0
            beq		mtspr64_mmcr0            
            cmpwi	r3,chud_970_mmcr1
            beq		mtspr64_mmcr1
            cmpwi	r3,chud_970_mmcra
            beq		mtspr64_mmcra
            cmpwi	r3,chud_970_siar
            beq		mtspr64_siar
            cmpwi	r3,chud_970_sdar
            beq		mtspr64_sdar
            cmpwi	r3,chud_970_imc
            beq		mtspr64_imc
            cmpwi	r3,chud_970_rmor
            beq		mtspr64_rmor
            cmpwi	r3,chud_970_hrmor
            beq		mtspr64_hrmor
            cmpwi	r3,chud_970_hior
            beq		mtspr64_hior
            cmpwi	r3,chud_970_lpidr
            beq		mtspr64_lpidr
            cmpwi	r3,chud_970_lpcr
            beq		mtspr64_lpcr
            cmpwi	r3,chud_970_dabrx
            beq		mtspr64_dabrx       
            cmpwi	r3,chud_970_hsprg0
            beq		mtspr64_hsprg0
            cmpwi	r3,chud_970_hsprg1
            beq		mtspr64_hsprg1
            cmpwi	r3,chud_970_hsrr0
            beq		mtspr64_hsrr0
            cmpwi	r3,chud_970_hsrr1
            beq		mtspr64_hsrr1
            cmpwi	r3,chud_970_hdec
            beq		mtspr64_hdec
            cmpwi	r3,chud_970_trig0
            beq		mtspr64_trig0
            cmpwi	r3,chud_970_trig1
            beq		mtspr64_trig1
            cmpwi	r3,chud_970_trig2
            beq		mtspr64_trig2
            cmpwi	r3,chud_ppc64_accr
            beq		mtspr64_accr
            cmpwi	r3,chud_970_scomc
            beq		mtspr64_scomc
            cmpwi	r3,chud_970_scomd
            beq		mtspr64_scomd
                                                                                                                                                            
            b		mtspr64_failure
            
mtspr64_srr0:
            ld		r5,0(r4)
            mtspr	chud_ppc_srr0,r5
            b		mtspr64_success
mtspr64_srr1:
            ld		r5,0(r4)
            mtspr	chud_ppc_srr1,r5
            b		mtspr64_success
mtspr64_dar:
            ld		r5,0(r4)
            mtspr	chud_ppc_dar,r5
            b		mtspr64_success          
mtspr64_sdr1:
            ld		r5,0(r4)
            mtspr	chud_ppc_sdr1,r5
            b		mtspr64_success 
mtspr64_sprg0:
            ld		r5,0(r4)
            mtspr	chud_ppc_sprg0,r5
            b		mtspr64_success
mtspr64_sprg1:
            ld		r5,0(r4)
            mtspr	chud_ppc_sprg1,r5
            b		mtspr64_success 
mtspr64_sprg2:
            ld		r5,0(r4)
            mtspr	chud_ppc_sprg2,r5
            b		mtspr64_success 
mtspr64_sprg3:
            ld		r5,0(r4)
            mtspr	chud_ppc_sprg3,r5
            b		mtspr64_success 
mtspr64_asr:
            ld		r5,0(r4)
            mtspr	chud_ppc64_asr,r5
            b		mtspr64_success             
mtspr64_dabr:
            ld		r5,0(r4)
            mtspr	chud_ppc_dabr,r5
            b		mtspr64_success 
mtspr64_hid0:
            ld		r5,0(r4)
            sync
            mtspr	chud_970_hid0,r5
            mfspr	r5,chud_970_hid0	/* syncronization requirements */
            mfspr	r5,chud_970_hid0
            mfspr	r5,chud_970_hid0
            mfspr	r5,chud_970_hid0
            mfspr	r5,chud_970_hid0
            mfspr	r5,chud_970_hid0
            b		mtspr64_success            
mtspr64_hid1:
            ld		r5,0(r4)
            mtspr	chud_970_hid1,r5	/* tell you twice */
            mtspr	chud_970_hid1,r5
            isync
            b		mtspr64_success     
mtspr64_hid4:
            ld		r5,0(r4)
            sync				/* syncronization requirements */
            mtspr	chud_970_hid4,r5
            isync
            b		mtspr64_success             
mtspr64_hid5:
            ld		r5,0(r4)
            mtspr	chud_970_hid5,r5
            b		mtspr64_success
mtspr64_mmcr0:
            ld		r5,0(r4)
            mtspr	chud_970_mmcr0,r5
            b		mtspr64_success
mtspr64_mmcr1:
            ld		r5,0(r4)
            mtspr	chud_970_mmcr1,r5
            b		mtspr64_success
mtspr64_mmcra:
            ld		r5,0(r4)
            mtspr	chud_970_mmcra,r5
            b		mtspr64_success
mtspr64_siar:
            ld		r5,0(r4)
            mtspr	chud_970_siar,r5
            b		mtspr64_success            
mtspr64_sdar:
            ld		r5,0(r4)
            mtspr	chud_970_sdar,r5
            b		mtspr64_success              
mtspr64_imc:
            ld		r5,0(r4)
            mtspr	chud_970_imc,r5
            b		mtspr64_success                          
mtspr64_rmor:
            ld		r5,0(r4)
            mtspr	chud_970_rmor,r5
            b		mtspr64_success              
mtspr64_hrmor:
            ld		r5,0(r4)
            mtspr	chud_970_hrmor,r5
            b		mtspr64_success  
mtspr64_hior:
            ld		r5,0(r4)
            mtspr	chud_970_hior,r5
            b		mtspr64_success  
mtspr64_lpidr:
            ld		r5,0(r4)
            mtspr	chud_970_lpidr,r5
            b		mtspr64_success   
mtspr64_lpcr:
            ld		r5,0(r4)
            mtspr	chud_970_lpcr,r5
            b		mtspr64_success    
mtspr64_dabrx:
            ld		r5,0(r4)
            mtspr	chud_970_dabrx,r5
            b		mtspr64_success    
mtspr64_hsprg0:
            ld		r5,0(r4)
            mtspr	chud_970_hsprg0,r5
            b		mtspr64_success   
mtspr64_hsprg1:
            ld		r5,0(r4)
            mtspr	chud_970_hsprg1,r5
            b		mtspr64_success 
mtspr64_hsrr0:
            ld		r5,0(r4)
            mtspr	chud_970_hsrr0,r5
            b		mtspr64_success 
mtspr64_hsrr1:
            ld		r5,0(r4)
            mtspr	chud_970_hsrr1,r5
            b		mtspr64_success 
mtspr64_hdec:
            ld		r5,0(r4)
            mtspr	chud_970_hdec,r5
            b		mtspr64_success             
mtspr64_trig0:
            ld		r5,0(r4)
            mtspr	chud_970_trig0,r5
            b		mtspr64_success 
mtspr64_trig1:
            ld		r5,0(r4)
            mtspr	chud_970_trig1,r5
            b		mtspr64_success
mtspr64_trig2:
            ld		r5,0(r4)
            mtspr	chud_970_trig2,r5
            b		mtspr64_success
mtspr64_accr:
            ld		r5,0(r4)
            mtspr	chud_ppc64_accr,r5
            b		mtspr64_success
mtspr64_scomc:
            ld		r5,0(r4)
            mtspr	chud_970_scomc,r5
            b		mtspr64_success
mtspr64_scomd:
            ld		r5,0(r4)
            mtspr	chud_970_scomd,r5
            b		mtspr64_success
            
mtspr64_failure:
            li		r3,KERN_FAILURE
            blr
            
mtspr64_success:
            li		r3,KERN_SUCCESS
            blr


/*
 * kern_return_t mfmsr64(uint64_t *val);
 * 
 * r3: address to store value in
 *
 */
 
;           Force a line boundry here
            .align  5
            .globl  EXT(mfmsr64)

EXT(mfmsr64):            
            mfmsr	r5
            std		r5,0(r3)
mfmsr64_success:
            li		r3,KERN_SUCCESS
            blr

mfmsr64_failure:
            li		r3,KERN_FAILURE
            blr


/*
 * kern_return_t mtmsr64(uint64_t *val);
 * 
 * r3: address to load value from
 *
 */
 
;           Force a line boundry here
            .align  5
            .globl  EXT(mtmsr64)

EXT(mtmsr64):            
            ld		r5,0(r3)
            mtmsrd	r5
            b		mtmsr64_success
            
mtmsr64_success:
            li		r3,KERN_SUCCESS
            blr

mtmsr64_failure:
            li		r3,KERN_FAILURE
            blr

.L_end:
Commit	Line	Data
55e303ae A	1	/*
	2	* Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
	3	*
8f6c56a5	4	* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
55e303ae	5	*
8f6c56a5 A	6	* This file contains Original Code and/or Modifications of Original Code
	7	* as defined in and that are subject to the Apple Public Source License
	8	* Version 2.0 (the 'License'). You may not use this file except in
	9	* compliance with the License. The rights granted to you under the License
	10	* may not be used to create, or enable the creation or redistribution of,
	11	* unlawful or unlicensed copies of an Apple operating system, or to
	12	* circumvent, violate, or enable the circumvention or violation of, any
	13	* terms of an Apple operating system software license agreement.
	14	*
	15	* Please obtain a copy of the License at
	16	* http://www.opensource.apple.com/apsl/ and read it before using this file.
	17	*
	18	* The Original Code and all software distributed under the License are
	19	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
	20	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
	21	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
	22	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	23	* Please see the License for the specific language governing rights and
8ad349bb	24	* limitations under the License.
8f6c56a5 A	25	*
8f6c56a5 A	26	* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
55e303ae A	27	*/
	28
	29	#define ASSEMBLER
4452a7af	30	#include <chud/ppc/chud_spr.h>
55e303ae A	31	#include <ppc/asm.h>
	32	#include <mach/kern_return.h>
	33
91447636 A	34	/*
	35	* kern_return_t mfspr64(uint64_t *val, int spr);
	36	*
	37	* r3: address to store value in
	38	* r4: spr to read from
	39	*
	40	*/
	41
	42	; Force a line boundry here
	43	.align 5
	44	.globl EXT(mfspr64)
	45
	46	EXT(mfspr64):
	47	;; generic PPC 64-bit wide SPRs
	48	cmpwi r4,chud_ppc_srr0
	49	beq mfspr64_srr0
	50	cmpwi r4,chud_ppc_srr1
	51	beq mfspr64_srr1
	52	cmpwi r4,chud_ppc_dar
	53	beq mfspr64_dar
	54	cmpwi r4,chud_ppc_sdr1
	55	beq mfspr64_sdr1
	56	cmpwi r4,chud_ppc_sprg0
	57	beq mfspr64_sprg0
	58	cmpwi r4,chud_ppc_sprg1
	59	beq mfspr64_sprg1
	60	cmpwi r4,chud_ppc_sprg2
	61	beq mfspr64_sprg2
	62	cmpwi r4,chud_ppc_sprg3
	63	beq mfspr64_sprg3
	64	cmpwi r4,chud_ppc64_asr
	65	beq mfspr64_asr
	66	cmpwi r4,chud_ppc_dabr
	67	beq mfspr64_dabr
	68
	69	;; GPUL specific 64-bit wide SPRs
	70	cmpwi r4,chud_970_hid0
	71	beq mfspr64_hid0
	72	cmpwi r4,chud_970_hid1
	73	beq mfspr64_hid1
	74	cmpwi r4,chud_970_hid4
	75	beq mfspr64_hid4
	76	cmpwi r4,chud_970_hid5
	77	beq mfspr64_hid5
	78	cmpwi r4,chud_970_mmcr0
	79	beq mfspr64_mmcr0
	80	cmpwi r4,chud_970_mmcr1
	81	beq mfspr64_mmcr1
	82	cmpwi r4,chud_970_mmcra
	83	beq mfspr64_mmcra
	84	cmpwi r4,chud_970_siar
	85	beq mfspr64_siar
	86	cmpwi r4,chud_970_sdar
	87	beq mfspr64_sdar
	88	cmpwi r4,chud_970_imc
	89	beq mfspr64_imc
	90	cmpwi r4,chud_970_rmor
	91	beq mfspr64_rmor
	92	cmpwi r4,chud_970_hrmor
	93	beq mfspr64_hrmor
	94	cmpwi r4,chud_970_hior
	95	beq mfspr64_hior
	96	cmpwi r4,chud_970_lpidr
	97	beq mfspr64_lpidr
98	cmpwi r4,chud_970_lpcr
99	beq mfspr64_lpcr
100	cmpwi r4,chud_970_dabrx
101	beq mfspr64_dabrx
102	cmpwi r4,chud_970_hsprg0
103	beq mfspr64_hsprg0
104	cmpwi r4,chud_970_hsprg1
105	beq mfspr64_hsprg1
106	cmpwi r4,chud_970_hsrr0
107	beq mfspr64_hsrr0
108	cmpwi r4,chud_970_hsrr1
109	beq mfspr64_hsrr1
110	cmpwi r4,chud_970_hdec
111	beq mfspr64_hdec
112	cmpwi r4,chud_970_trig0
113	beq mfspr64_trig0
114	cmpwi r4,chud_970_trig1
115	beq mfspr64_trig1
116	cmpwi r4,chud_970_trig2
117	beq mfspr64_trig2
118	cmpwi r4,chud_ppc64_accr
119	beq mfspr64_accr
120	cmpwi r4,chud_970_scomc
121	beq mfspr64_scomc
122	cmpwi r4,chud_970_scomd
123	beq mfspr64_scomd
124
125	b mfspr64_failure
126
127	mfspr64_srr0:
55e303ae A	128	mfspr r5,chud_ppc_srr0
55e303ae A	129	std r5,0(r3)
91447636 A	130	b mfspr64_success
91447636 A	131	mfspr64_srr1:
55e303ae A	132	mfspr r5,chud_ppc_srr1
55e303ae A	133	std r5,0(r3)
91447636 A	134	b mfspr64_success
91447636 A	135	mfspr64_dar:
55e303ae A	136	mfspr r5,chud_ppc_dar
55e303ae A	137	std r5,0(r3)
91447636 A	138	b mfspr64_success
91447636 A	139	mfspr64_sdr1:
55e303ae A	140	mfspr r5,chud_ppc_sdr1
55e303ae A	141	std r5,0(r3)
91447636 A	142	b mfspr64_success
91447636 A	143	mfspr64_sprg0:
55e303ae A	144	mfspr r5,chud_ppc_sprg0
55e303ae A	145	std r5,0(r3)
91447636 A	146	b mfspr64_success
91447636 A	147	mfspr64_sprg1:
55e303ae A	148	mfspr r5,chud_ppc_sprg1
55e303ae A	149	std r5,0(r3)
91447636 A	150	b mfspr64_success
91447636 A	151	mfspr64_sprg2:
55e303ae A	152	mfspr r5,chud_ppc_sprg2
55e303ae A	153	std r5,0(r3)
91447636 A	154	b mfspr64_success
91447636 A	155	mfspr64_sprg3:
55e303ae A	156	mfspr r5,chud_ppc_sprg3
55e303ae A	157	std r5,0(r3)
91447636 A	158	b mfspr64_success
91447636 A	159	mfspr64_asr:
55e303ae A	160	mfspr r5,chud_ppc64_asr
55e303ae A	161	std r5,0(r3)
91447636 A	162	b mfspr64_success
91447636 A	163	mfspr64_dabr:
55e303ae A	164	mfspr r5,chud_ppc_dabr
55e303ae A	165	std r5,0(r3)
91447636 A	166	b mfspr64_success
91447636 A	167	mfspr64_hid0:
55e303ae A	168	mfspr r5,chud_970_hid0
55e303ae A	169	std r5,0(r3)
91447636 A	170	b mfspr64_success
91447636 A	171	mfspr64_hid1:
55e303ae A	172	mfspr r5,chud_970_hid1
55e303ae A	173	std r5,0(r3)
91447636 A	174	b mfspr64_success
91447636 A	175	mfspr64_hid4:
55e303ae A	176	mfspr r5,chud_970_hid4
55e303ae A	177	std r5,0(r3)
91447636 A	178	b mfspr64_success
91447636 A	179	mfspr64_hid5:
55e303ae A	180	mfspr r5,chud_970_hid5
55e303ae A	181	std r5,0(r3)
91447636 A	182	b mfspr64_success
91447636 A	183	mfspr64_mmcr0:
55e303ae A	184	mfspr r5,chud_970_mmcr0
55e303ae A	185	std r5,0(r3)
91447636 A	186	b mfspr64_success
91447636 A	187	mfspr64_mmcr1:
55e303ae A	188	mfspr r5,chud_970_mmcr1
55e303ae A	189	std r5,0(r3)
91447636 A	190	b mfspr64_success
91447636 A	191	mfspr64_mmcra:
55e303ae A	192	mfspr r5,chud_970_mmcra
55e303ae A	193	std r5,0(r3)
91447636 A	194	b mfspr64_success
91447636 A	195	mfspr64_siar:
55e303ae A	196	mfspr r5,chud_970_siar
55e303ae A	197	std r5,0(r3)
91447636 A	198	b mfspr64_success
91447636 A	199	mfspr64_sdar:
55e303ae A	200	mfspr r5,chud_970_sdar
55e303ae A	201	std r5,0(r3)
91447636 A	202	b mfspr64_success
91447636 A	203	mfspr64_imc:
55e303ae A	204	mfspr r5,chud_970_imc
55e303ae A	205	std r5,0(r3)
91447636 A	206	b mfspr64_success
91447636 A	207	mfspr64_rmor:
55e303ae A	208	mfspr r5,chud_970_rmor
55e303ae A	209	std r5,0(r3)
91447636 A	210	b mfspr64_success
91447636 A	211	mfspr64_hrmor:
55e303ae A	212	mfspr r5,chud_970_hrmor
55e303ae A	213	std r5,0(r3)
91447636 A	214	b mfspr64_success
91447636 A	215	mfspr64_hior:
55e303ae A	216	mfspr r5,chud_970_hior
55e303ae A	217	std r5,0(r3)
91447636 A	218	b mfspr64_success
91447636 A	219	mfspr64_lpidr:
55e303ae A	220	mfspr r5,chud_970_lpidr
55e303ae A	221	std r5,0(r3)
91447636 A	222	b mfspr64_success
91447636 A	223	mfspr64_lpcr:
55e303ae A	224	mfspr r5,chud_970_lpcr
55e303ae A	225	std r5,0(r3)
91447636 A	226	b mfspr64_success
91447636 A	227	mfspr64_dabrx:
55e303ae A	228	mfspr r5,chud_970_dabrx
55e303ae A	229	std r5,0(r3)
91447636 A	230	b mfspr64_success
91447636 A	231	mfspr64_hsprg0:
55e303ae A	232	mfspr r5,chud_970_hsprg0
55e303ae A	233	std r5,0(r3)
91447636 A	234	b mfspr64_success
91447636 A	235	mfspr64_hsprg1:
55e303ae A	236	mfspr r5,chud_970_hsprg1
55e303ae A	237	std r5,0(r3)
91447636 A	238	b mfspr64_success
91447636 A	239	mfspr64_hsrr0:
55e303ae A	240	mfspr r5,chud_970_hsrr0
55e303ae A	241	std r5,0(r3)
91447636 A	242	b mfspr64_success
91447636 A	243	mfspr64_hsrr1:
55e303ae A	244	mfspr r5,chud_970_hsrr1
55e303ae A	245	std r5,0(r3)
91447636 A	246	b mfspr64_success
91447636 A	247	mfspr64_hdec:
55e303ae A	248	mfspr r5,chud_970_hdec
55e303ae A	249	std r5,0(r3)
91447636 A	250	b mfspr64_success
91447636 A	251	mfspr64_trig0:
55e303ae A	252	mfspr r5,chud_970_trig0
55e303ae A	253	std r5,0(r3)
91447636 A	254	b mfspr64_success
91447636 A	255	mfspr64_trig1:
55e303ae A	256	mfspr r5,chud_970_trig1
55e303ae A	257	std r5,0(r3)
91447636 A	258	b mfspr64_success
91447636 A	259	mfspr64_trig2:
55e303ae A	260	mfspr r5,chud_970_trig2
55e303ae A	261	std r5,0(r3)
91447636 A	262	b mfspr64_success
91447636 A	263	mfspr64_accr:
55e303ae A	264	mfspr r5,chud_ppc64_accr
55e303ae A	265	std r5,0(r3)
91447636 A	266	b mfspr64_success
91447636 A	267	mfspr64_scomc:
55e303ae A	268	mfspr r5,chud_970_scomc
55e303ae A	269	std r5,0(r3)
91447636 A	270	b mfspr64_success
91447636 A	271	mfspr64_scomd:
55e303ae A	272	mfspr r5,chud_970_scomd
55e303ae A	273	std r5,0(r3)
91447636 A	274	b mfspr64_success
	275
	276	mfspr64_failure:
	277	li r3,KERN_FAILURE
55e303ae A	278	blr
55e303ae A	279
91447636 A	280	mfspr64_success:
91447636 A	281	li r3,KERN_SUCCESS
55e303ae A	282	blr
55e303ae A	283
91447636 A	284
	285	/*
	286	* kern_return_t mtspr64(int spr, uint64_t *val);
	287	*
	288	* r3: spr to write to
	289	* r4: address to get value from
	290	*
	291	*/
	292
	293	; Force a line boundry here
	294	.align 5
	295	.globl EXT(mtspr64)
	296
	297	EXT(mtspr64):
	298	;; generic PPC 64-bit wide SPRs
	299	cmpwi r3,chud_ppc_srr0
	300	beq mtspr64_srr0
	301	cmpwi r3,chud_ppc_srr1
	302	beq mtspr64_srr1
	303	cmpwi r3,chud_ppc_dar
	304	beq mtspr64_dar
	305	cmpwi r3,chud_ppc_sdr1
	306	beq mtspr64_sdr1
	307	cmpwi r3,chud_ppc_sprg0
	308	beq mtspr64_sprg0
	309	cmpwi r3,chud_ppc_sprg1
	310	beq mtspr64_sprg1
	311	cmpwi r3,chud_ppc_sprg2
	312	beq mtspr64_sprg2
	313	cmpwi r3,chud_ppc_sprg3
	314	beq mtspr64_sprg3
	315	cmpwi r3,chud_ppc64_asr
	316	beq mtspr64_asr
	317	cmpwi r3,chud_ppc_dabr
	318	beq mtspr64_dabr
	319
	320	;; GPUL specific 64-bit wide SPRs
	321	cmpwi r3,chud_970_hid0
	322	beq mtspr64_hid0
	323	cmpwi r3,chud_970_hid1
	324	beq mtspr64_hid1
	325	cmpwi r3,chud_970_hid4
	326	beq mtspr64_hid4
	327	cmpwi r3,chud_970_hid5
	328	beq mtspr64_hid5
	329	cmpwi r3,chud_970_mmcr0
	330	beq mtspr64_mmcr0
	331	cmpwi r3,chud_970_mmcr1
	332	beq mtspr64_mmcr1
	333	cmpwi r3,chud_970_mmcra
	334	beq mtspr64_mmcra
	335	cmpwi r3,chud_970_siar
	336	beq mtspr64_siar
	337	cmpwi r3,chud_970_sdar
	338	beq mtspr64_sdar
	339	cmpwi r3,chud_970_imc
	340	beq mtspr64_imc
	341	cmpwi r3,chud_970_rmor
	342	beq mtspr64_rmor
	343	cmpwi r3,chud_970_hrmor
	344	beq mtspr64_hrmor
	345	cmpwi r3,chud_970_hior
	346	beq mtspr64_hior
	347	cmpwi r3,chud_970_lpidr
348	beq mtspr64_lpidr
349	cmpwi r3,chud_970_lpcr
350	beq mtspr64_lpcr
351	cmpwi r3,chud_970_dabrx
352	beq mtspr64_dabrx
353	cmpwi r3,chud_970_hsprg0
354	beq mtspr64_hsprg0
355	cmpwi r3,chud_970_hsprg1
356	beq mtspr64_hsprg1
357	cmpwi r3,chud_970_hsrr0
358	beq mtspr64_hsrr0
359	cmpwi r3,chud_970_hsrr1
360	beq mtspr64_hsrr1
361	cmpwi r3,chud_970_hdec
362	beq mtspr64_hdec
363	cmpwi r3,chud_970_trig0
364	beq mtspr64_trig0
365	cmpwi r3,chud_970_trig1
366	beq mtspr64_trig1
367	cmpwi r3,chud_970_trig2
368	beq mtspr64_trig2
369	cmpwi r3,chud_ppc64_accr
370	beq mtspr64_accr
371	cmpwi r3,chud_970_scomc
372	beq mtspr64_scomc
373	cmpwi r3,chud_970_scomd
374	beq mtspr64_scomd
375
376	b mtspr64_failure
377
378	mtspr64_srr0:
379	ld r5,0(r4)
380	mtspr chud_ppc_srr0,r5
381	b mtspr64_success
382	mtspr64_srr1:
55e303ae A	383	ld r5,0(r4)
55e303ae A	384	mtspr chud_ppc_srr1,r5
91447636 A	385	b mtspr64_success
91447636 A	386	mtspr64_dar:
55e303ae A	387	ld r5,0(r4)
55e303ae A	388	mtspr chud_ppc_dar,r5
91447636 A	389	b mtspr64_success
91447636 A	390	mtspr64_sdr1:
55e303ae A	391	ld r5,0(r4)
55e303ae A	392	mtspr chud_ppc_sdr1,r5
91447636 A	393	b mtspr64_success
91447636 A	394	mtspr64_sprg0:
55e303ae A	395	ld r5,0(r4)
55e303ae A	396	mtspr chud_ppc_sprg0,r5
91447636 A	397	b mtspr64_success
91447636 A	398	mtspr64_sprg1:
55e303ae A	399	ld r5,0(r4)
55e303ae A	400	mtspr chud_ppc_sprg1,r5
91447636 A	401	b mtspr64_success
91447636 A	402	mtspr64_sprg2:
55e303ae A	403	ld r5,0(r4)
55e303ae A	404	mtspr chud_ppc_sprg2,r5
91447636 A	405	b mtspr64_success
91447636 A	406	mtspr64_sprg3:
55e303ae A	407	ld r5,0(r4)
55e303ae A	408	mtspr chud_ppc_sprg3,r5
91447636 A	409	b mtspr64_success
91447636 A	410	mtspr64_asr:
55e303ae A	411	ld r5,0(r4)
55e303ae A	412	mtspr chud_ppc64_asr,r5
91447636 A	413	b mtspr64_success
91447636 A	414	mtspr64_dabr:
55e303ae A	415	ld r5,0(r4)
55e303ae A	416	mtspr chud_ppc_dabr,r5
91447636 A	417	b mtspr64_success
91447636 A	418	mtspr64_hid0:
55e303ae A	419	ld r5,0(r4)
	420	sync
	421	mtspr chud_970_hid0,r5
	422	mfspr r5,chud_970_hid0 /* syncronization requirements */
	423	mfspr r5,chud_970_hid0
	424	mfspr r5,chud_970_hid0
	425	mfspr r5,chud_970_hid0
	426	mfspr r5,chud_970_hid0
	427	mfspr r5,chud_970_hid0
91447636 A	428	b mtspr64_success
91447636 A	429	mtspr64_hid1:
55e303ae A	430	ld r5,0(r4)
	431	mtspr chud_970_hid1,r5 /* tell you twice */
	432	mtspr chud_970_hid1,r5
	433	isync
91447636 A	434	b mtspr64_success
91447636 A	435	mtspr64_hid4:
55e303ae A	436	ld r5,0(r4)
	437	sync /* syncronization requirements */
	438	mtspr chud_970_hid4,r5
	439	isync
91447636 A	440	b mtspr64_success
91447636 A	441	mtspr64_hid5:
55e303ae A	442	ld r5,0(r4)
55e303ae A	443	mtspr chud_970_hid5,r5
91447636 A	444	b mtspr64_success
91447636 A	445	mtspr64_mmcr0:
55e303ae A	446	ld r5,0(r4)
55e303ae A	447	mtspr chud_970_mmcr0,r5
91447636 A	448	b mtspr64_success
91447636 A	449	mtspr64_mmcr1:
55e303ae A	450	ld r5,0(r4)
55e303ae A	451	mtspr chud_970_mmcr1,r5
91447636 A	452	b mtspr64_success
91447636 A	453	mtspr64_mmcra:
55e303ae A	454	ld r5,0(r4)
55e303ae A	455	mtspr chud_970_mmcra,r5
91447636 A	456	b mtspr64_success
91447636 A	457	mtspr64_siar:
55e303ae A	458	ld r5,0(r4)
55e303ae A	459	mtspr chud_970_siar,r5
91447636 A	460	b mtspr64_success
91447636 A	461	mtspr64_sdar:
55e303ae A	462	ld r5,0(r4)
55e303ae A	463	mtspr chud_970_sdar,r5
91447636 A	464	b mtspr64_success
91447636 A	465	mtspr64_imc:
55e303ae A	466	ld r5,0(r4)
55e303ae A	467	mtspr chud_970_imc,r5
91447636 A	468	b mtspr64_success
91447636 A	469	mtspr64_rmor:
55e303ae A	470	ld r5,0(r4)
55e303ae A	471	mtspr chud_970_rmor,r5
91447636 A	472	b mtspr64_success
91447636 A	473	mtspr64_hrmor:
55e303ae A	474	ld r5,0(r4)
55e303ae A	475	mtspr chud_970_hrmor,r5
91447636 A	476	b mtspr64_success
91447636 A	477	mtspr64_hior:
55e303ae A	478	ld r5,0(r4)
55e303ae A	479	mtspr chud_970_hior,r5
91447636 A	480	b mtspr64_success
91447636 A	481	mtspr64_lpidr:
55e303ae A	482	ld r5,0(r4)
55e303ae A	483	mtspr chud_970_lpidr,r5
91447636 A	484	b mtspr64_success
91447636 A	485	mtspr64_lpcr:
55e303ae A	486	ld r5,0(r4)
55e303ae A	487	mtspr chud_970_lpcr,r5
91447636 A	488	b mtspr64_success
91447636 A	489	mtspr64_dabrx:
55e303ae	490	ld r5,0(r4)
91447636 A	491	mtspr chud_970_dabrx,r5
	492	b mtspr64_success
	493	mtspr64_hsprg0:
55e303ae A	494	ld r5,0(r4)
55e303ae A	495	mtspr chud_970_hsprg0,r5
91447636 A	496	b mtspr64_success
91447636 A	497	mtspr64_hsprg1:
55e303ae A	498	ld r5,0(r4)
55e303ae A	499	mtspr chud_970_hsprg1,r5
91447636 A	500	b mtspr64_success
91447636 A	501	mtspr64_hsrr0:
55e303ae A	502	ld r5,0(r4)
55e303ae A	503	mtspr chud_970_hsrr0,r5
91447636 A	504	b mtspr64_success
91447636 A	505	mtspr64_hsrr1:
55e303ae A	506	ld r5,0(r4)
55e303ae A	507	mtspr chud_970_hsrr1,r5
91447636 A	508	b mtspr64_success
91447636 A	509	mtspr64_hdec:
55e303ae A	510	ld r5,0(r4)
55e303ae A	511	mtspr chud_970_hdec,r5
91447636 A	512	b mtspr64_success
91447636 A	513	mtspr64_trig0:
55e303ae A	514	ld r5,0(r4)
55e303ae A	515	mtspr chud_970_trig0,r5
91447636 A	516	b mtspr64_success
91447636 A	517	mtspr64_trig1:
55e303ae A	518	ld r5,0(r4)
55e303ae A	519	mtspr chud_970_trig1,r5
91447636 A	520	b mtspr64_success
91447636 A	521	mtspr64_trig2:
55e303ae A	522	ld r5,0(r4)
55e303ae A	523	mtspr chud_970_trig2,r5
91447636 A	524	b mtspr64_success
91447636 A	525	mtspr64_accr:
55e303ae A	526	ld r5,0(r4)
55e303ae A	527	mtspr chud_ppc64_accr,r5
91447636 A	528	b mtspr64_success
91447636 A	529	mtspr64_scomc:
55e303ae A	530	ld r5,0(r4)
55e303ae A	531	mtspr chud_970_scomc,r5
91447636 A	532	b mtspr64_success
91447636 A	533	mtspr64_scomd:
55e303ae A	534	ld r5,0(r4)
55e303ae A	535	mtspr chud_970_scomd,r5
91447636 A	536	b mtspr64_success
	537
	538	mtspr64_failure:
	539	li r3,KERN_FAILURE
	540	blr
55e303ae	541
91447636 A	542	mtspr64_success:
	543	li r3,KERN_SUCCESS
	544	blr
	545
	546
	547	/*
	548	* kern_return_t mfmsr64(uint64_t *val);
	549	*
	550	* r3: address to store value in
	551	*
	552	*/
	553
	554	; Force a line boundry here
55e303ae	555	.align 5
91447636 A	556	.globl EXT(mfmsr64)
	557
	558	EXT(mfmsr64):
55e303ae A	559	mfmsr r5
55e303ae A	560	std r5,0(r3)
91447636 A	561	mfmsr64_success:
	562	li r3,KERN_SUCCESS
	563	blr
	564
	565	mfmsr64_failure:
	566	li r3,KERN_FAILURE
55e303ae A	567	blr
55e303ae A	568
91447636 A	569
	570	/*
	571	* kern_return_t mtmsr64(uint64_t *val);
	572	*
	573	* r3: address to load value from
	574	*
	575	*/
	576
	577	; Force a line boundry here
55e303ae	578	.align 5
91447636 A	579	.globl EXT(mtmsr64)
	580
	581	EXT(mtmsr64):
55e303ae A	582	ld r5,0(r3)
55e303ae A	583	mtmsrd r5
91447636 A	584	b mtmsr64_success
	585
	586	mtmsr64_success:
	587	li r3,KERN_SUCCESS
	588	blr
	589
	590	mtmsr64_failure:
	591	li r3,KERN_FAILURE
55e303ae A	592	blr
55e303ae A	593
4a249263	594	.L_end: