[apple/xnu.git] / osfmk / i386 / machine_routines_asm.s

/*
 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_LICENSE_HEADER_START@
 * 
 * Copyright (c) 1999-2003 Apple Computer, Inc.  All Rights Reserved.
 * 
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this
 * file.
 * 
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 * 
 * @APPLE_LICENSE_HEADER_END@
 */
#include <i386/asm.h>

/*
**      ml_get_timebase()
**
**      Entry   - %esp contains pointer to 64 bit structure.
**
**      Exit    - 64 bit structure filled in.
**
*/
ENTRY(ml_get_timebase)

        movl    S_ARG0, %ecx

        rdtsc

        movl    %edx, 0(%ecx)
        movl    %eax, 4(%ecx)

        ret


/* PCI config cycle probing
 *
 *      boolean_t ml_probe_read(vm_offset_t paddr, unsigned int *val)
 *
 *      Read the memory location at physical address paddr.
 *  This is a part of a device probe, so there is a good chance we will
 *  have a machine check here. So we have to be able to handle that.
 *  We assume that machine checks are enabled both in MSR and HIDs
 */
ENTRY(ml_probe_read)

        movl S_ARG0, %ecx
        movl S_ARG1, %eax
        movl 0(%ecx), %ecx
        movl %ecx, 0(%eax)
        movl $1, %eax

        ret


/* PCI config cycle probing - 64-bit
 *
 *      boolean_t ml_probe_read_64(addr64_t paddr, unsigned int *val)
 *
 *      Read the memory location at physical address paddr.
 *  This is a part of a device probe, so there is a good chance we will
 *  have a machine check here. So we have to be able to handle that.
 *  We assume that machine checks are enabled both in MSR and HIDs
 */
ENTRY(ml_probe_read_64)

        /* Only use lower 32 bits of address for now */
        movl S_ARG0, %ecx
        movl S_ARG2, %eax
        movl 0(%ecx), %ecx
        movl %ecx, 0(%eax)
        movl $1, %eax

        ret


/* Read physical address byte
 *
 *      unsigned int ml_phys_read_byte(vm_offset_t paddr)
 *      unsigned int ml_phys_read_byte_64(addr64_t paddr)
 *
 *      Read the byte at physical address paddr. Memory should not be cache inhibited.
 */
ENTRY(ml_phys_read_byte_64)

        /* Only use lower 32 bits of address for now */
        movl S_ARG0, %ecx
        xor %eax, %eax
        movb 0(%ecx), %eax

	ret

ENTRY(ml_phys_read_byte)

        movl S_ARG0, %ecx
        xor %eax, %eax
        movb 0(%ecx), %eax

	ret


/* Read physical address half word
 *
 *      unsigned int ml_phys_read_half(vm_offset_t paddr)
 *      unsigned int ml_phys_read_half_64(addr64_t paddr)
 *
 *      Read the half word at physical address paddr. Memory should not be cache inhibited.
 */
ENTRY(ml_phys_read_half_64)

        /* Only use lower 32 bits of address for now */
        movl S_ARG0, %ecx
        xor %eax, %eax
        movw 0(%ecx), %eax

	ret

ENTRY(ml_phys_read_half)

        movl S_ARG0, %ecx
        xor %eax, %eax
        movw 0(%ecx), %eax

	ret


/* Read physical address word
 *
 *      unsigned int ml_phys_read(vm_offset_t paddr)
 *      unsigned int ml_phys_read_64(addr64_t paddr)
 *      unsigned int ml_phys_read_word(vm_offset_t paddr)
 *      unsigned int ml_phys_read_word_64(addr64_t paddr)
 *
 *      Read the word at physical address paddr. Memory should not be cache inhibited.
 */
ENTRY(ml_phys_read_64)
ENTRY(ml_phys_read_word_64)

        /* Only use lower 32 bits of address for now */
        movl S_ARG0, %ecx
        movl 0(%ecx), %eax

	ret

ENTRY(ml_phys_read)
ENTRY(ml_phys_read_word)

        movl S_ARG0, %ecx
        movl 0(%ecx), %eax

	ret


/* Read physical address double
 *
 *      unsigned long long ml_phys_read_double(vm_offset_t paddr)
 *      unsigned long long ml_phys_read_double_64(addr64_t paddr)
 *
 *      Read the double word at physical address paddr. Memory should not be cache inhibited.
 */
ENTRY(ml_phys_read_double_64)

        /* Only use lower 32 bits of address for now */
        movl S_ARG0, %ecx
        movl 0(%ecx), %eax
        movl 4(%ecx), %edx

	ret

ENTRY(ml_phys_read_double)

        movl S_ARG0, %ecx
        movl 0(%ecx), %eax
        movl 4(%ecx), %edx

	ret


/* Write physical address byte
 *
 *      void ml_phys_write_byte(vm_offset_t paddr, unsigned int data)
 *      void ml_phys_write_byte_64(addr64_t paddr, unsigned int data)
 *
 *      Write the byte at physical address paddr. Memory should not be cache inhibited.
 */
ENTRY(ml_phys_write_byte_64)

        /* Only use lower 32 bits of address for now */
        movl S_ARG0, %ecx
        movl S_ARG2, %eax
        movb %eax, 0(%ecx)

	ret

ENTRY(ml_phys_write_byte)

        movl S_ARG0, %ecx
        movl S_ARG1, %eax
        movb %eax, 0(%ecx)

	ret


/* Write physical address half word
 *
 *      void ml_phys_write_half(vm_offset_t paddr, unsigned int data)
 *      void ml_phys_write_half_64(addr64_t paddr, unsigned int data)
 *
 *      Write the byte at physical address paddr. Memory should not be cache inhibited.
 */
ENTRY(ml_phys_write_half_64)

        /* Only use lower 32 bits of address for now */
        movl S_ARG0, %ecx
        movl S_ARG2, %eax
        movw %eax, 0(%ecx)

	ret

ENTRY(ml_phys_write_half)

        movl S_ARG0, %ecx
        movl S_ARG1, %eax
        movw %eax, 0(%ecx)

	ret


/* Write physical address word
 *
 *      void ml_phys_write(vm_offset_t paddr, unsigned int data)
 *      void ml_phys_write_64(addr64_t paddr, unsigned int data)
 *      void ml_phys_write_word(vm_offset_t paddr, unsigned int data)
 *      void ml_phys_write_word_64(addr64_t paddr, unsigned int data)
 *
 *      Write the word at physical address paddr. Memory should not be cache inhibited.
 */
ENTRY(ml_phys_write_64)
ENTRY(ml_phys_write_word_64)

        /* Only use lower 32 bits of address for now */
        movl S_ARG0, %ecx
        movl S_ARG2, %eax
        movl %eax, 0(%ecx)

	ret

ENTRY(ml_phys_write)
ENTRY(ml_phys_write_word)

        movl S_ARG0, %ecx
        movl S_ARG1, %eax
        movl %eax, 0(%ecx)

	ret


/* Write physical address double word
 *
 *      void ml_phys_write_double(vm_offset_t paddr, unsigned long long data)
 *      void ml_phys_write_double_64(addr64_t paddr, unsigned long long data)
 *
 *      Write the double word at physical address paddr. Memory should not be cache inhibited.
 */
ENTRY(ml_phys_write_double_64)

        /* Only use lower 32 bits of address for now */
        movl S_ARG0, %ecx
        movl S_ARG2, %eax
        movl %eax, 0(%ecx)
        movl S_ARG3, %eax
        movl %eax, 4(%ecx)

	ret

ENTRY(ml_phys_write_double)

        movl S_ARG0, %ecx
        movl S_ARG1, %eax
        movl %eax, 0(%ecx)
        movl S_ARG2, %eax
        movl %eax, 4(%ecx)

	ret
Commit	Line	Data
1c79356b A	1	/*
	2	* Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
	3	*
	4	* @APPLE_LICENSE_HEADER_START@
	5	*
43866e37	6	* Copyright (c) 1999-2003 Apple Computer, Inc. All Rights Reserved.
1c79356b	7	*
43866e37 A	8	* This file contains Original Code and/or Modifications of Original Code
	9	* as defined in and that are subject to the Apple Public Source License
	10	* Version 2.0 (the 'License'). You may not use this file except in
	11	* compliance with the License. Please obtain a copy of the License at
	12	* http://www.opensource.apple.com/apsl/ and read it before using this
	13	* file.
	14	*
	15	* The Original Code and all software distributed under the License are
	16	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
1c79356b A	17	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
1c79356b A	18	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
43866e37 A	19	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	20	* Please see the License for the specific language governing rights and
	21	* limitations under the License.
1c79356b A	22	*
	23	* @APPLE_LICENSE_HEADER_END@
	24	*/
	25	#include <i386/asm.h>
	26
	27	/*
	28	** ml_get_timebase()
	29	**
	30	** Entry - %esp contains pointer to 64 bit structure.
	31	**
	32	** Exit - 64 bit structure filled in.
	33	**
	34	*/
	35	ENTRY(ml_get_timebase)
	36
	37	movl S_ARG0, %ecx
	38
	39	rdtsc
	40
	41	movl %edx, 0(%ecx)
	42	movl %eax, 4(%ecx)
	43
	44	ret
43866e37 A	45
	46
	47	/* PCI config cycle probing
	48	*
	49	* boolean_t ml_probe_read(vm_offset_t paddr, unsigned int *val)
	50	*
	51	* Read the memory location at physical address paddr.
	52	* This is a part of a device probe, so there is a good chance we will
	53	* have a machine check here. So we have to be able to handle that.
	54	* We assume that machine checks are enabled both in MSR and HIDs
	55	*/
	56	ENTRY(ml_probe_read)
	57
	58	movl S_ARG0, %ecx
	59	movl S_ARG1, %eax
	60	movl 0(%ecx), %ecx
	61	movl %ecx, 0(%eax)
	62	movl $1, %eax
	63
	64	ret
	65
	66
	67	/* PCI config cycle probing - 64-bit
	68	*
	69	* boolean_t ml_probe_read_64(addr64_t paddr, unsigned int *val)
	70	*
	71	* Read the memory location at physical address paddr.
	72	* This is a part of a device probe, so there is a good chance we will
	73	* have a machine check here. So we have to be able to handle that.
	74	* We assume that machine checks are enabled both in MSR and HIDs
	75	*/
	76	ENTRY(ml_probe_read_64)
	77
	78	/* Only use lower 32 bits of address for now */
	79	movl S_ARG0, %ecx
	80	movl S_ARG2, %eax
	81	movl 0(%ecx), %ecx
	82	movl %ecx, 0(%eax)
	83	movl $1, %eax
	84
	85	ret
	86
	87
	88	/* Read physical address byte
	89	*
	90	* unsigned int ml_phys_read_byte(vm_offset_t paddr)
	91	* unsigned int ml_phys_read_byte_64(addr64_t paddr)
	92	*
	93	* Read the byte at physical address paddr. Memory should not be cache inhibited.
	94	*/
	95	ENTRY(ml_phys_read_byte_64)
	96
	97	/* Only use lower 32 bits of address for now */
	98	movl S_ARG0, %ecx
	99	xor %eax, %eax
	100	movb 0(%ecx), %eax
	101
	102	ret
	103
	104	ENTRY(ml_phys_read_byte)
	105
	106	movl S_ARG0, %ecx
	107	xor %eax, %eax
	108	movb 0(%ecx), %eax
109
110	ret
111
112
113	/* Read physical address half word
114	*
115	* unsigned int ml_phys_read_half(vm_offset_t paddr)
116	* unsigned int ml_phys_read_half_64(addr64_t paddr)
117	*
118	* Read the half word at physical address paddr. Memory should not be cache inhibited.
119	*/
120	ENTRY(ml_phys_read_half_64)
121
122	/* Only use lower 32 bits of address for now */
123	movl S_ARG0, %ecx
124	xor %eax, %eax
125	movw 0(%ecx), %eax
126
127	ret
128
129	ENTRY(ml_phys_read_half)
130
131	movl S_ARG0, %ecx
132	xor %eax, %eax
133	movw 0(%ecx), %eax
134
135	ret
136
137
138	/* Read physical address word
139	*
140	* unsigned int ml_phys_read(vm_offset_t paddr)
141	* unsigned int ml_phys_read_64(addr64_t paddr)
142	* unsigned int ml_phys_read_word(vm_offset_t paddr)
143	* unsigned int ml_phys_read_word_64(addr64_t paddr)
144	*
145	* Read the word at physical address paddr. Memory should not be cache inhibited.
146	*/
147	ENTRY(ml_phys_read_64)
148	ENTRY(ml_phys_read_word_64)
149
150	/* Only use lower 32 bits of address for now */
151	movl S_ARG0, %ecx
152	movl 0(%ecx), %eax
153
154	ret
155
156	ENTRY(ml_phys_read)
157	ENTRY(ml_phys_read_word)
158
159	movl S_ARG0, %ecx
160	movl 0(%ecx), %eax
161
162	ret
163
164
165	/* Read physical address double
166	*
167	* unsigned long long ml_phys_read_double(vm_offset_t paddr)
168	* unsigned long long ml_phys_read_double_64(addr64_t paddr)
169	*
170	* Read the double word at physical address paddr. Memory should not be cache inhibited.
171	*/
172	ENTRY(ml_phys_read_double_64)
173
174	/* Only use lower 32 bits of address for now */
175	movl S_ARG0, %ecx
176	movl 0(%ecx), %eax
177	movl 4(%ecx), %edx
178
179	ret
180
181	ENTRY(ml_phys_read_double)
182
183	movl S_ARG0, %ecx
184	movl 0(%ecx), %eax
185	movl 4(%ecx), %edx
186
187	ret
188
189
190	/* Write physical address byte
191	*
192	* void ml_phys_write_byte(vm_offset_t paddr, unsigned int data)
193	* void ml_phys_write_byte_64(addr64_t paddr, unsigned int data)
194	*
195	* Write the byte at physical address paddr. Memory should not be cache inhibited.
196	*/
197	ENTRY(ml_phys_write_byte_64)
198
199	/* Only use lower 32 bits of address for now */
200	movl S_ARG0, %ecx
201	movl S_ARG2, %eax
202	movb %eax, 0(%ecx)
203
204	ret
205
206	ENTRY(ml_phys_write_byte)
207
208	movl S_ARG0, %ecx
209	movl S_ARG1, %eax
210	movb %eax, 0(%ecx)
211
212	ret
213
214
215	/* Write physical address half word
216	*
217	* void ml_phys_write_half(vm_offset_t paddr, unsigned int data)
218	* void ml_phys_write_half_64(addr64_t paddr, unsigned int data)
219	*
220	* Write the byte at physical address paddr. Memory should not be cache inhibited.
221	*/
222	ENTRY(ml_phys_write_half_64)
223
224	/* Only use lower 32 bits of address for now */
225	movl S_ARG0, %ecx
226	movl S_ARG2, %eax
227	movw %eax, 0(%ecx)
228
229	ret
230
231	ENTRY(ml_phys_write_half)
232
233	movl S_ARG0, %ecx
234	movl S_ARG1, %eax
235	movw %eax, 0(%ecx)
236
237	ret
238
239
240	/* Write physical address word
241	*
242	* void ml_phys_write(vm_offset_t paddr, unsigned int data)
243	* void ml_phys_write_64(addr64_t paddr, unsigned int data)
244	* void ml_phys_write_word(vm_offset_t paddr, unsigned int data)
245	* void ml_phys_write_word_64(addr64_t paddr, unsigned int data)
246	*
247	* Write the word at physical address paddr. Memory should not be cache inhibited.
248	*/
249	ENTRY(ml_phys_write_64)
250	ENTRY(ml_phys_write_word_64)
251
252	/* Only use lower 32 bits of address for now */
253	movl S_ARG0, %ecx
254	movl S_ARG2, %eax
255	movl %eax, 0(%ecx)
256
257	ret
258
259	ENTRY(ml_phys_write)
260	ENTRY(ml_phys_write_word)
261
262	movl S_ARG0, %ecx
263	movl S_ARG1, %eax
264	movl %eax, 0(%ecx)
265
266	ret
267
268
269	/* Write physical address double word
270	*
271	* void ml_phys_write_double(vm_offset_t paddr, unsigned long long data)
272	* void ml_phys_write_double_64(addr64_t paddr, unsigned long long data)
273	*
274	* Write the double word at physical address paddr. Memory should not be cache inhibited.
275	*/
276	ENTRY(ml_phys_write_double_64)
277
278	/* Only use lower 32 bits of address for now */
279	movl S_ARG0, %ecx
280	movl S_ARG2, %eax
281	movl %eax, 0(%ecx)
282	movl S_ARG3, %eax
283	movl %eax, 4(%ecx)
284
285	ret
286
287	ENTRY(ml_phys_write_double)
288
289	movl S_ARG0, %ecx
290	movl S_ARG1, %eax
291	movl %eax, 0(%ecx)
292	movl S_ARG2, %eax
293	movl %eax, 4(%ecx)
294
295	ret