[apple/xnu.git] / osfmk / ppc / chud / chud_cpu_asm.s

/*
 * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_LICENSE_HEADER_START@
 * 
 * The contents of this file constitute Original Code as defined in and
 * are subject to the Apple Public Source License Version 1.1 (the
 * "License").  You may not use this file except in compliance with the
 * License.  Please obtain a copy of the License at
 * http://www.apple.com/publicsource and read it before using this file.
 * 
 * This Original Code and all software distributed under the License are
 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
 * License for the specific language governing rights and limitations
 * under the License.
 * 
 * @APPLE_LICENSE_HEADER_END@
 */
 
#define ASSEMBLER
#include <ppc/chud/chud_spr.h>
#include <ppc/asm.h>
#include <mach/kern_return.h>

/*
 * kern_return_t mfspr64(uint64_t *val, int spr);
 * 
 * r3: address to store value in
 * r4: spr to read from
 *
 */
 
;           Force a line boundry here
            .align  5
            .globl  EXT(mfspr64)

EXT(mfspr64):
            ;; generic PPC 64-bit wide SPRs
            cmpwi	r4,chud_ppc_srr0
            beq		mfspr64_srr0
            cmpwi	r4,chud_ppc_srr1
            beq		mfspr64_srr1
            cmpwi	r4,chud_ppc_dar
            beq		mfspr64_dar
            cmpwi	r4,chud_ppc_sdr1
            beq		mfspr64_sdr1
            cmpwi	r4,chud_ppc_sprg0
            beq		mfspr64_sprg0       
            cmpwi	r4,chud_ppc_sprg1
            beq		mfspr64_sprg1  
            cmpwi	r4,chud_ppc_sprg2
            beq		mfspr64_sprg2  
            cmpwi	r4,chud_ppc_sprg3
            beq		mfspr64_sprg3
            cmpwi	r4,chud_ppc64_asr
            beq		mfspr64_asr
            cmpwi	r4,chud_ppc_dabr
            beq		mfspr64_dabr
            
            ;; GPUL specific 64-bit wide SPRs
            cmpwi	r4,chud_970_hid0
            beq		mfspr64_hid0
            cmpwi	r4,chud_970_hid1
            beq		mfspr64_hid1
            cmpwi	r4,chud_970_hid4
            beq		mfspr64_hid4
            cmpwi	r4,chud_970_hid5
            beq		mfspr64_hid5       
            cmpwi	r4,chud_970_mmcr0
            beq		mfspr64_mmcr0            
            cmpwi	r4,chud_970_mmcr1
            beq		mfspr64_mmcr1
            cmpwi	r4,chud_970_mmcra
            beq		mfspr64_mmcra
            cmpwi	r4,chud_970_siar
            beq		mfspr64_siar
            cmpwi	r4,chud_970_sdar
            beq		mfspr64_sdar
            cmpwi	r4,chud_970_imc
            beq		mfspr64_imc
            cmpwi	r4,chud_970_rmor
            beq		mfspr64_rmor
            cmpwi	r4,chud_970_hrmor
            beq		mfspr64_hrmor
            cmpwi	r4,chud_970_hior
            beq		mfspr64_hior
            cmpwi	r4,chud_970_lpidr
            beq		mfspr64_lpidr
            cmpwi	r4,chud_970_lpcr
            beq		mfspr64_lpcr
            cmpwi	r4,chud_970_dabrx
            beq		mfspr64_dabrx
            cmpwi	r4,chud_970_hsprg0
            beq		mfspr64_hsprg0
            cmpwi	r4,chud_970_hsprg1
            beq		mfspr64_hsprg1
            cmpwi	r4,chud_970_hsrr0
            beq		mfspr64_hsrr0
            cmpwi	r4,chud_970_hsrr1
            beq		mfspr64_hsrr1
            cmpwi	r4,chud_970_hdec
            beq		mfspr64_hdec
            cmpwi	r4,chud_970_trig0
            beq		mfspr64_trig0
            cmpwi	r4,chud_970_trig1
            beq		mfspr64_trig1
            cmpwi	r4,chud_970_trig2
            beq		mfspr64_trig2
            cmpwi	r4,chud_ppc64_accr
            beq		mfspr64_accr
            cmpwi	r4,chud_970_scomc
            beq		mfspr64_scomc
            cmpwi	r4,chud_970_scomd
            beq		mfspr64_scomd
                                                                                                                                                            
            b		mfspr64_failure
            
mfspr64_srr0:
            mfspr	r5,chud_ppc_srr0
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_srr1:
            mfspr	r5,chud_ppc_srr1
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_dar:
            mfspr	r5,chud_ppc_dar
            std		r5,0(r3)
            b		mfspr64_success          
mfspr64_sdr1:
            mfspr	r5,chud_ppc_sdr1
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_sprg0:
            mfspr	r5,chud_ppc_sprg0
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_sprg1:
            mfspr	r5,chud_ppc_sprg1
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_sprg2:
            mfspr	r5,chud_ppc_sprg2
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_sprg3:
            mfspr	r5,chud_ppc_sprg3
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_asr:
            mfspr	r5,chud_ppc64_asr
            std		r5,0(r3)
            b		mfspr64_success             
mfspr64_dabr:
            mfspr	r5,chud_ppc_dabr
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_hid0:
            mfspr	r5,chud_970_hid0
            std		r5,0(r3)
            b		mfspr64_success            
mfspr64_hid1:
            mfspr	r5,chud_970_hid1
            std		r5,0(r3)
            b		mfspr64_success     
mfspr64_hid4:
            mfspr	r5,chud_970_hid4
            std		r5,0(r3)
            b		mfspr64_success             
mfspr64_hid5:
            mfspr	r5,chud_970_hid5
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_mmcr0:
            mfspr	r5,chud_970_mmcr0
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_mmcr1:
            mfspr	r5,chud_970_mmcr1
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_mmcra:
            mfspr	r5,chud_970_mmcra
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_siar:
            mfspr	r5,chud_970_siar
            std		r5,0(r3)
            b		mfspr64_success            
mfspr64_sdar:
            mfspr	r5,chud_970_sdar
            std		r5,0(r3)
            b		mfspr64_success              
mfspr64_imc:
            mfspr	r5,chud_970_imc
            std		r5,0(r3)
            b		mfspr64_success                          
mfspr64_rmor:
            mfspr	r5,chud_970_rmor
            std		r5,0(r3)
            b		mfspr64_success              
mfspr64_hrmor:
            mfspr	r5,chud_970_hrmor
            std		r5,0(r3)
            b		mfspr64_success  
mfspr64_hior:
            mfspr	r5,chud_970_hior
            std		r5,0(r3)
            b		mfspr64_success  
mfspr64_lpidr:
            mfspr	r5,chud_970_lpidr
            std		r5,0(r3)
            b		mfspr64_success   
mfspr64_lpcr:
            mfspr	r5,chud_970_lpcr
            std		r5,0(r3)
            b		mfspr64_success  
mfspr64_dabrx:
            mfspr	r5,chud_970_dabrx
            std		r5,0(r3)
            b		mfspr64_success  
mfspr64_hsprg0:
            mfspr	r5,chud_970_hsprg0
            std		r5,0(r3)
            b		mfspr64_success   
mfspr64_hsprg1:
            mfspr	r5,chud_970_hsprg1
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_hsrr0:
            mfspr	r5,chud_970_hsrr0
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_hsrr1:
            mfspr	r5,chud_970_hsrr1
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_hdec:
            mfspr	r5,chud_970_hdec
            std		r5,0(r3)
            b		mfspr64_success             
mfspr64_trig0:
            mfspr	r5,chud_970_trig0
            std		r5,0(r3)
            b		mfspr64_success 
mfspr64_trig1:
            mfspr	r5,chud_970_trig1
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_trig2:
            mfspr	r5,chud_970_trig2
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_accr:
            mfspr	r5,chud_ppc64_accr
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_scomc:
            mfspr	r5,chud_970_scomc
            std		r5,0(r3)
            b		mfspr64_success
mfspr64_scomd:
            mfspr	r5,chud_970_scomd
            std		r5,0(r3)
            b		mfspr64_success
            
mfspr64_failure:
            li		r3,KERN_FAILURE
            blr
            
mfspr64_success:
            li		r3,KERN_SUCCESS
            blr


/*
 * kern_return_t mtspr64(int spr, uint64_t *val);
 * 
 * r3: spr to write to
 * r4: address to get value from
 *
 */
 
;           Force a line boundry here
            .align  5
            .globl  EXT(mtspr64)

EXT(mtspr64):
            ;; generic PPC 64-bit wide SPRs
            cmpwi	r3,chud_ppc_srr0
            beq		mtspr64_srr0
            cmpwi	r3,chud_ppc_srr1
            beq		mtspr64_srr1
            cmpwi	r3,chud_ppc_dar
            beq		mtspr64_dar
            cmpwi	r3,chud_ppc_sdr1
            beq		mtspr64_sdr1
            cmpwi	r3,chud_ppc_sprg0
            beq		mtspr64_sprg0       
            cmpwi	r3,chud_ppc_sprg1
            beq		mtspr64_sprg1  
            cmpwi	r3,chud_ppc_sprg2
            beq		mtspr64_sprg2  
            cmpwi	r3,chud_ppc_sprg3
            beq		mtspr64_sprg3
            cmpwi	r3,chud_ppc64_asr
            beq		mtspr64_asr
            cmpwi	r3,chud_ppc_dabr
            beq		mtspr64_dabr
            
            ;; GPUL specific 64-bit wide SPRs
            cmpwi	r3,chud_970_hid0
            beq		mtspr64_hid0
            cmpwi	r3,chud_970_hid1
            beq		mtspr64_hid1
            cmpwi	r3,chud_970_hid4
            beq		mtspr64_hid4
            cmpwi	r3,chud_970_hid5
            beq		mtspr64_hid5       
            cmpwi	r3,chud_970_mmcr0
            beq		mtspr64_mmcr0            
            cmpwi	r3,chud_970_mmcr1
            beq		mtspr64_mmcr1
            cmpwi	r3,chud_970_mmcra
            beq		mtspr64_mmcra
            cmpwi	r3,chud_970_siar
            beq		mtspr64_siar
            cmpwi	r3,chud_970_sdar
            beq		mtspr64_sdar
            cmpwi	r3,chud_970_imc
            beq		mtspr64_imc
            cmpwi	r3,chud_970_rmor
            beq		mtspr64_rmor
            cmpwi	r3,chud_970_hrmor
            beq		mtspr64_hrmor
            cmpwi	r3,chud_970_hior
            beq		mtspr64_hior
            cmpwi	r3,chud_970_lpidr
            beq		mtspr64_lpidr
            cmpwi	r3,chud_970_lpcr
            beq		mtspr64_lpcr
            cmpwi	r3,chud_970_dabrx
            beq		mtspr64_dabrx       
            cmpwi	r3,chud_970_hsprg0
            beq		mtspr64_hsprg0
            cmpwi	r3,chud_970_hsprg1
            beq		mtspr64_hsprg1
            cmpwi	r3,chud_970_hsrr0
            beq		mtspr64_hsrr0
            cmpwi	r3,chud_970_hsrr1
            beq		mtspr64_hsrr1
            cmpwi	r3,chud_970_hdec
            beq		mtspr64_hdec
            cmpwi	r3,chud_970_trig0
            beq		mtspr64_trig0
            cmpwi	r3,chud_970_trig1
            beq		mtspr64_trig1
            cmpwi	r3,chud_970_trig2
            beq		mtspr64_trig2
            cmpwi	r3,chud_ppc64_accr
            beq		mtspr64_accr
            cmpwi	r3,chud_970_scomc
            beq		mtspr64_scomc
            cmpwi	r3,chud_970_scomd
            beq		mtspr64_scomd
                                                                                                                                                            
            b		mtspr64_failure
            
mtspr64_srr0:
            ld		r5,0(r4)
            mtspr	chud_ppc_srr0,r5
            b		mtspr64_success
mtspr64_srr1:
            ld		r5,0(r4)
            mtspr	chud_ppc_srr1,r5
            b		mtspr64_success
mtspr64_dar:
            ld		r5,0(r4)
            mtspr	chud_ppc_dar,r5
            b		mtspr64_success          
mtspr64_sdr1:
            ld		r5,0(r4)
            mtspr	chud_ppc_sdr1,r5
            b		mtspr64_success 
mtspr64_sprg0:
            ld		r5,0(r4)
            mtspr	chud_ppc_sprg0,r5
            b		mtspr64_success
mtspr64_sprg1:
            ld		r5,0(r4)
            mtspr	chud_ppc_sprg1,r5
            b		mtspr64_success 
mtspr64_sprg2:
            ld		r5,0(r4)
            mtspr	chud_ppc_sprg2,r5
            b		mtspr64_success 
mtspr64_sprg3:
            ld		r5,0(r4)
            mtspr	chud_ppc_sprg3,r5
            b		mtspr64_success 
mtspr64_asr:
            ld		r5,0(r4)
            mtspr	chud_ppc64_asr,r5
            b		mtspr64_success             
mtspr64_dabr:
            ld		r5,0(r4)
            mtspr	chud_ppc_dabr,r5
            b		mtspr64_success 
mtspr64_hid0:
            ld		r5,0(r4)
            sync
            mtspr	chud_970_hid0,r5
            mfspr	r5,chud_970_hid0	/* syncronization requirements */
            mfspr	r5,chud_970_hid0
            mfspr	r5,chud_970_hid0
            mfspr	r5,chud_970_hid0
            mfspr	r5,chud_970_hid0
            mfspr	r5,chud_970_hid0
            b		mtspr64_success            
mtspr64_hid1:
            ld		r5,0(r4)
            mtspr	chud_970_hid1,r5	/* tell you twice */
            mtspr	chud_970_hid1,r5
            isync
            b		mtspr64_success     
mtspr64_hid4:
            ld		r5,0(r4)
            sync				/* syncronization requirements */
            mtspr	chud_970_hid4,r5
            isync
            b		mtspr64_success             
mtspr64_hid5:
            ld		r5,0(r4)
            mtspr	chud_970_hid5,r5
            b		mtspr64_success
mtspr64_mmcr0:
            ld		r5,0(r4)
            mtspr	chud_970_mmcr0,r5
            b		mtspr64_success
mtspr64_mmcr1:
            ld		r5,0(r4)
            mtspr	chud_970_mmcr1,r5
            b		mtspr64_success
mtspr64_mmcra:
            ld		r5,0(r4)
            mtspr	chud_970_mmcra,r5
            b		mtspr64_success
mtspr64_siar:
            ld		r5,0(r4)
            mtspr	chud_970_siar,r5
            b		mtspr64_success            
mtspr64_sdar:
            ld		r5,0(r4)
            mtspr	chud_970_sdar,r5
            b		mtspr64_success              
mtspr64_imc:
            ld		r5,0(r4)
            mtspr	chud_970_imc,r5
            b		mtspr64_success                          
mtspr64_rmor:
            ld		r5,0(r4)
            mtspr	chud_970_rmor,r5
            b		mtspr64_success              
mtspr64_hrmor:
            ld		r5,0(r4)
            mtspr	chud_970_hrmor,r5
            b		mtspr64_success  
mtspr64_hior:
            ld		r5,0(r4)
            mtspr	chud_970_hior,r5
            b		mtspr64_success  
mtspr64_lpidr:
            ld		r5,0(r4)
            mtspr	chud_970_lpidr,r5
            b		mtspr64_success   
mtspr64_lpcr:
            ld		r5,0(r4)
            mtspr	chud_970_lpcr,r5
            b		mtspr64_success    
mtspr64_dabrx:
            ld		r5,0(r4)
            mtspr	chud_970_dabrx,r5
            b		mtspr64_success    
mtspr64_hsprg0:
            ld		r5,0(r4)
            mtspr	chud_970_hsprg0,r5
            b		mtspr64_success   
mtspr64_hsprg1:
            ld		r5,0(r4)
            mtspr	chud_970_hsprg1,r5
            b		mtspr64_success 
mtspr64_hsrr0:
            ld		r5,0(r4)
            mtspr	chud_970_hsrr0,r5
            b		mtspr64_success 
mtspr64_hsrr1:
            ld		r5,0(r4)
            mtspr	chud_970_hsrr1,r5
            b		mtspr64_success 
mtspr64_hdec:
            ld		r5,0(r4)
            mtspr	chud_970_hdec,r5
            b		mtspr64_success             
mtspr64_trig0:
            ld		r5,0(r4)
            mtspr	chud_970_trig0,r5
            b		mtspr64_success 
mtspr64_trig1:
            ld		r5,0(r4)
            mtspr	chud_970_trig1,r5
            b		mtspr64_success
mtspr64_trig2:
            ld		r5,0(r4)
            mtspr	chud_970_trig2,r5
            b		mtspr64_success
mtspr64_accr:
            ld		r5,0(r4)
            mtspr	chud_ppc64_accr,r5
            b		mtspr64_success
mtspr64_scomc:
            ld		r5,0(r4)
            mtspr	chud_970_scomc,r5
            b		mtspr64_success
mtspr64_scomd:
            ld		r5,0(r4)
            mtspr	chud_970_scomd,r5
            b		mtspr64_success
            
mtspr64_failure:
            li		r3,KERN_FAILURE
            blr
            
mtspr64_success:
            li		r3,KERN_SUCCESS
            blr


/*
 * kern_return_t mfmsr64(uint64_t *val);
 * 
 * r3: address to store value in
 *
 */
 
;           Force a line boundry here
            .align  5
            .globl  EXT(mfmsr64)

EXT(mfmsr64):            
            mfmsr	r5
            std		r5,0(r3)
mfmsr64_success:
            li		r3,KERN_SUCCESS
            blr

mfmsr64_failure:
            li		r3,KERN_FAILURE
            blr


/*
 * kern_return_t mtmsr64(uint64_t *val);
 * 
 * r3: address to load value from
 *
 */
 
;           Force a line boundry here
            .align  5
            .globl  EXT(mtmsr64)

EXT(mtmsr64):            
            ld		r5,0(r3)
            mtmsrd	r5
            b		mtmsr64_success
            
mtmsr64_success:
            li		r3,KERN_SUCCESS
            blr

mtmsr64_failure:
            li		r3,KERN_FAILURE
            blr

.L_end:
Commit	Line	Data
55e303ae A	1	/*
	2	* Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
	3	*
	4	* @APPLE_LICENSE_HEADER_START@
	5	*
37839358 A	6	* The contents of this file constitute Original Code as defined in and
	7	* are subject to the Apple Public Source License Version 1.1 (the
	8	* "License"). You may not use this file except in compliance with the
	9	* License. Please obtain a copy of the License at
	10	* http://www.apple.com/publicsource and read it before using this file.
55e303ae	11	*
37839358 A	12	* This Original Code and all software distributed under the License are
37839358 A	13	* distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
55e303ae A	14	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
55e303ae A	15	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
37839358 A	16	* FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
	17	* License for the specific language governing rights and limitations
	18	* under the License.
55e303ae A	19	*
	20	* @APPLE_LICENSE_HEADER_END@
	21	*/
	22
	23	#define ASSEMBLER
	24	#include <ppc/chud/chud_spr.h>
	25	#include <ppc/asm.h>
	26	#include <mach/kern_return.h>
	27
91447636 A	28	/*
	29	* kern_return_t mfspr64(uint64_t *val, int spr);
	30	*
	31	* r3: address to store value in
	32	* r4: spr to read from
	33	*
	34	*/
	35
	36	; Force a line boundry here
	37	.align 5
	38	.globl EXT(mfspr64)
	39
	40	EXT(mfspr64):
	41	;; generic PPC 64-bit wide SPRs
	42	cmpwi r4,chud_ppc_srr0
	43	beq mfspr64_srr0
	44	cmpwi r4,chud_ppc_srr1
	45	beq mfspr64_srr1
	46	cmpwi r4,chud_ppc_dar
	47	beq mfspr64_dar
	48	cmpwi r4,chud_ppc_sdr1
	49	beq mfspr64_sdr1
	50	cmpwi r4,chud_ppc_sprg0
	51	beq mfspr64_sprg0
	52	cmpwi r4,chud_ppc_sprg1
	53	beq mfspr64_sprg1
	54	cmpwi r4,chud_ppc_sprg2
	55	beq mfspr64_sprg2
	56	cmpwi r4,chud_ppc_sprg3
	57	beq mfspr64_sprg3
	58	cmpwi r4,chud_ppc64_asr
	59	beq mfspr64_asr
	60	cmpwi r4,chud_ppc_dabr
	61	beq mfspr64_dabr
	62
	63	;; GPUL specific 64-bit wide SPRs
	64	cmpwi r4,chud_970_hid0
	65	beq mfspr64_hid0
	66	cmpwi r4,chud_970_hid1
	67	beq mfspr64_hid1
	68	cmpwi r4,chud_970_hid4
	69	beq mfspr64_hid4
	70	cmpwi r4,chud_970_hid5
	71	beq mfspr64_hid5
	72	cmpwi r4,chud_970_mmcr0
	73	beq mfspr64_mmcr0
	74	cmpwi r4,chud_970_mmcr1
	75	beq mfspr64_mmcr1
	76	cmpwi r4,chud_970_mmcra
	77	beq mfspr64_mmcra
	78	cmpwi r4,chud_970_siar
	79	beq mfspr64_siar
	80	cmpwi r4,chud_970_sdar
	81	beq mfspr64_sdar
	82	cmpwi r4,chud_970_imc
	83	beq mfspr64_imc
	84	cmpwi r4,chud_970_rmor
	85	beq mfspr64_rmor
	86	cmpwi r4,chud_970_hrmor
	87	beq mfspr64_hrmor
	88	cmpwi r4,chud_970_hior
	89	beq mfspr64_hior
	90	cmpwi r4,chud_970_lpidr
	91	beq mfspr64_lpidr
92	cmpwi r4,chud_970_lpcr
93	beq mfspr64_lpcr
94	cmpwi r4,chud_970_dabrx
95	beq mfspr64_dabrx
96	cmpwi r4,chud_970_hsprg0
97	beq mfspr64_hsprg0
98	cmpwi r4,chud_970_hsprg1
99	beq mfspr64_hsprg1
100	cmpwi r4,chud_970_hsrr0
101	beq mfspr64_hsrr0
102	cmpwi r4,chud_970_hsrr1
103	beq mfspr64_hsrr1
104	cmpwi r4,chud_970_hdec
105	beq mfspr64_hdec
106	cmpwi r4,chud_970_trig0
107	beq mfspr64_trig0
108	cmpwi r4,chud_970_trig1
109	beq mfspr64_trig1
110	cmpwi r4,chud_970_trig2
111	beq mfspr64_trig2
112	cmpwi r4,chud_ppc64_accr
113	beq mfspr64_accr
114	cmpwi r4,chud_970_scomc
115	beq mfspr64_scomc
116	cmpwi r4,chud_970_scomd
117	beq mfspr64_scomd
118
119	b mfspr64_failure
120
121	mfspr64_srr0:
55e303ae A	122	mfspr r5,chud_ppc_srr0
55e303ae A	123	std r5,0(r3)
91447636 A	124	b mfspr64_success
91447636 A	125	mfspr64_srr1:
55e303ae A	126	mfspr r5,chud_ppc_srr1
55e303ae A	127	std r5,0(r3)
91447636 A	128	b mfspr64_success
91447636 A	129	mfspr64_dar:
55e303ae A	130	mfspr r5,chud_ppc_dar
55e303ae A	131	std r5,0(r3)
91447636 A	132	b mfspr64_success
91447636 A	133	mfspr64_sdr1:
55e303ae A	134	mfspr r5,chud_ppc_sdr1
55e303ae A	135	std r5,0(r3)
91447636 A	136	b mfspr64_success
91447636 A	137	mfspr64_sprg0:
55e303ae A	138	mfspr r5,chud_ppc_sprg0
55e303ae A	139	std r5,0(r3)
91447636 A	140	b mfspr64_success
91447636 A	141	mfspr64_sprg1:
55e303ae A	142	mfspr r5,chud_ppc_sprg1
55e303ae A	143	std r5,0(r3)
91447636 A	144	b mfspr64_success
91447636 A	145	mfspr64_sprg2:
55e303ae A	146	mfspr r5,chud_ppc_sprg2
55e303ae A	147	std r5,0(r3)
91447636 A	148	b mfspr64_success
91447636 A	149	mfspr64_sprg3:
55e303ae A	150	mfspr r5,chud_ppc_sprg3
55e303ae A	151	std r5,0(r3)
91447636 A	152	b mfspr64_success
91447636 A	153	mfspr64_asr:
55e303ae A	154	mfspr r5,chud_ppc64_asr
55e303ae A	155	std r5,0(r3)
91447636 A	156	b mfspr64_success
91447636 A	157	mfspr64_dabr:
55e303ae A	158	mfspr r5,chud_ppc_dabr
55e303ae A	159	std r5,0(r3)
91447636 A	160	b mfspr64_success
91447636 A	161	mfspr64_hid0:
55e303ae A	162	mfspr r5,chud_970_hid0
55e303ae A	163	std r5,0(r3)
91447636 A	164	b mfspr64_success
91447636 A	165	mfspr64_hid1:
55e303ae A	166	mfspr r5,chud_970_hid1
55e303ae A	167	std r5,0(r3)
91447636 A	168	b mfspr64_success
91447636 A	169	mfspr64_hid4:
55e303ae A	170	mfspr r5,chud_970_hid4
55e303ae A	171	std r5,0(r3)
91447636 A	172	b mfspr64_success
91447636 A	173	mfspr64_hid5:
55e303ae A	174	mfspr r5,chud_970_hid5
55e303ae A	175	std r5,0(r3)
91447636 A	176	b mfspr64_success
91447636 A	177	mfspr64_mmcr0:
55e303ae A	178	mfspr r5,chud_970_mmcr0
55e303ae A	179	std r5,0(r3)
91447636 A	180	b mfspr64_success
91447636 A	181	mfspr64_mmcr1:
55e303ae A	182	mfspr r5,chud_970_mmcr1
55e303ae A	183	std r5,0(r3)
91447636 A	184	b mfspr64_success
91447636 A	185	mfspr64_mmcra:
55e303ae A	186	mfspr r5,chud_970_mmcra
55e303ae A	187	std r5,0(r3)
91447636 A	188	b mfspr64_success
91447636 A	189	mfspr64_siar:
55e303ae A	190	mfspr r5,chud_970_siar
55e303ae A	191	std r5,0(r3)
91447636 A	192	b mfspr64_success
91447636 A	193	mfspr64_sdar:
55e303ae A	194	mfspr r5,chud_970_sdar
55e303ae A	195	std r5,0(r3)
91447636 A	196	b mfspr64_success
91447636 A	197	mfspr64_imc:
55e303ae A	198	mfspr r5,chud_970_imc
55e303ae A	199	std r5,0(r3)
91447636 A	200	b mfspr64_success
91447636 A	201	mfspr64_rmor:
55e303ae A	202	mfspr r5,chud_970_rmor
55e303ae A	203	std r5,0(r3)
91447636 A	204	b mfspr64_success
91447636 A	205	mfspr64_hrmor:
55e303ae A	206	mfspr r5,chud_970_hrmor
55e303ae A	207	std r5,0(r3)
91447636 A	208	b mfspr64_success
91447636 A	209	mfspr64_hior:
55e303ae A	210	mfspr r5,chud_970_hior
55e303ae A	211	std r5,0(r3)
91447636 A	212	b mfspr64_success
91447636 A	213	mfspr64_lpidr:
55e303ae A	214	mfspr r5,chud_970_lpidr
55e303ae A	215	std r5,0(r3)
91447636 A	216	b mfspr64_success
91447636 A	217	mfspr64_lpcr:
55e303ae A	218	mfspr r5,chud_970_lpcr
55e303ae A	219	std r5,0(r3)
91447636 A	220	b mfspr64_success
91447636 A	221	mfspr64_dabrx:
55e303ae A	222	mfspr r5,chud_970_dabrx
55e303ae A	223	std r5,0(r3)
91447636 A	224	b mfspr64_success
91447636 A	225	mfspr64_hsprg0:
55e303ae A	226	mfspr r5,chud_970_hsprg0
55e303ae A	227	std r5,0(r3)
91447636 A	228	b mfspr64_success
91447636 A	229	mfspr64_hsprg1:
55e303ae A	230	mfspr r5,chud_970_hsprg1
55e303ae A	231	std r5,0(r3)
91447636 A	232	b mfspr64_success
91447636 A	233	mfspr64_hsrr0:
55e303ae A	234	mfspr r5,chud_970_hsrr0
55e303ae A	235	std r5,0(r3)
91447636 A	236	b mfspr64_success
91447636 A	237	mfspr64_hsrr1:
55e303ae A	238	mfspr r5,chud_970_hsrr1
55e303ae A	239	std r5,0(r3)
91447636 A	240	b mfspr64_success
91447636 A	241	mfspr64_hdec:
55e303ae A	242	mfspr r5,chud_970_hdec
55e303ae A	243	std r5,0(r3)
91447636 A	244	b mfspr64_success
91447636 A	245	mfspr64_trig0:
55e303ae A	246	mfspr r5,chud_970_trig0
55e303ae A	247	std r5,0(r3)
91447636 A	248	b mfspr64_success
91447636 A	249	mfspr64_trig1:
55e303ae A	250	mfspr r5,chud_970_trig1
55e303ae A	251	std r5,0(r3)
91447636 A	252	b mfspr64_success
91447636 A	253	mfspr64_trig2:
55e303ae A	254	mfspr r5,chud_970_trig2
55e303ae A	255	std r5,0(r3)
91447636 A	256	b mfspr64_success
91447636 A	257	mfspr64_accr:
55e303ae A	258	mfspr r5,chud_ppc64_accr
55e303ae A	259	std r5,0(r3)
91447636 A	260	b mfspr64_success
91447636 A	261	mfspr64_scomc:
55e303ae A	262	mfspr r5,chud_970_scomc
55e303ae A	263	std r5,0(r3)
91447636 A	264	b mfspr64_success
91447636 A	265	mfspr64_scomd:
55e303ae A	266	mfspr r5,chud_970_scomd
55e303ae A	267	std r5,0(r3)
91447636 A	268	b mfspr64_success
	269
	270	mfspr64_failure:
	271	li r3,KERN_FAILURE
55e303ae A	272	blr
55e303ae A	273
91447636 A	274	mfspr64_success:
91447636 A	275	li r3,KERN_SUCCESS
55e303ae A	276	blr
55e303ae A	277
91447636 A	278
	279	/*
	280	* kern_return_t mtspr64(int spr, uint64_t *val);
	281	*
	282	* r3: spr to write to
	283	* r4: address to get value from
	284	*
	285	*/
	286
	287	; Force a line boundry here
	288	.align 5
	289	.globl EXT(mtspr64)
	290
	291	EXT(mtspr64):
	292	;; generic PPC 64-bit wide SPRs
	293	cmpwi r3,chud_ppc_srr0
	294	beq mtspr64_srr0
	295	cmpwi r3,chud_ppc_srr1
	296	beq mtspr64_srr1
	297	cmpwi r3,chud_ppc_dar
	298	beq mtspr64_dar
	299	cmpwi r3,chud_ppc_sdr1
	300	beq mtspr64_sdr1
	301	cmpwi r3,chud_ppc_sprg0
	302	beq mtspr64_sprg0
	303	cmpwi r3,chud_ppc_sprg1
	304	beq mtspr64_sprg1
	305	cmpwi r3,chud_ppc_sprg2
	306	beq mtspr64_sprg2
	307	cmpwi r3,chud_ppc_sprg3
	308	beq mtspr64_sprg3
	309	cmpwi r3,chud_ppc64_asr
	310	beq mtspr64_asr
	311	cmpwi r3,chud_ppc_dabr
	312	beq mtspr64_dabr
	313
	314	;; GPUL specific 64-bit wide SPRs
	315	cmpwi r3,chud_970_hid0
	316	beq mtspr64_hid0
	317	cmpwi r3,chud_970_hid1
	318	beq mtspr64_hid1
	319	cmpwi r3,chud_970_hid4
	320	beq mtspr64_hid4
	321	cmpwi r3,chud_970_hid5
	322	beq mtspr64_hid5
	323	cmpwi r3,chud_970_mmcr0
	324	beq mtspr64_mmcr0
	325	cmpwi r3,chud_970_mmcr1
	326	beq mtspr64_mmcr1
	327	cmpwi r3,chud_970_mmcra
	328	beq mtspr64_mmcra
	329	cmpwi r3,chud_970_siar
	330	beq mtspr64_siar
	331	cmpwi r3,chud_970_sdar
	332	beq mtspr64_sdar
	333	cmpwi r3,chud_970_imc
	334	beq mtspr64_imc
	335	cmpwi r3,chud_970_rmor
	336	beq mtspr64_rmor
	337	cmpwi r3,chud_970_hrmor
	338	beq mtspr64_hrmor
	339	cmpwi r3,chud_970_hior
	340	beq mtspr64_hior
	341	cmpwi r3,chud_970_lpidr
342	beq mtspr64_lpidr
343	cmpwi r3,chud_970_lpcr
344	beq mtspr64_lpcr
345	cmpwi r3,chud_970_dabrx
346	beq mtspr64_dabrx
347	cmpwi r3,chud_970_hsprg0
348	beq mtspr64_hsprg0
349	cmpwi r3,chud_970_hsprg1
350	beq mtspr64_hsprg1
351	cmpwi r3,chud_970_hsrr0
352	beq mtspr64_hsrr0
353	cmpwi r3,chud_970_hsrr1
354	beq mtspr64_hsrr1
355	cmpwi r3,chud_970_hdec
356	beq mtspr64_hdec
357	cmpwi r3,chud_970_trig0
358	beq mtspr64_trig0
359	cmpwi r3,chud_970_trig1
360	beq mtspr64_trig1
361	cmpwi r3,chud_970_trig2
362	beq mtspr64_trig2
363	cmpwi r3,chud_ppc64_accr
364	beq mtspr64_accr
365	cmpwi r3,chud_970_scomc
366	beq mtspr64_scomc
367	cmpwi r3,chud_970_scomd
368	beq mtspr64_scomd
369
370	b mtspr64_failure
371
372	mtspr64_srr0:
373	ld r5,0(r4)
374	mtspr chud_ppc_srr0,r5
375	b mtspr64_success
376	mtspr64_srr1:
55e303ae A	377	ld r5,0(r4)
55e303ae A	378	mtspr chud_ppc_srr1,r5
91447636 A	379	b mtspr64_success
91447636 A	380	mtspr64_dar:
55e303ae A	381	ld r5,0(r4)
55e303ae A	382	mtspr chud_ppc_dar,r5
91447636 A	383	b mtspr64_success
91447636 A	384	mtspr64_sdr1:
55e303ae A	385	ld r5,0(r4)
55e303ae A	386	mtspr chud_ppc_sdr1,r5
91447636 A	387	b mtspr64_success
91447636 A	388	mtspr64_sprg0:
55e303ae A	389	ld r5,0(r4)
55e303ae A	390	mtspr chud_ppc_sprg0,r5
91447636 A	391	b mtspr64_success
91447636 A	392	mtspr64_sprg1:
55e303ae A	393	ld r5,0(r4)
55e303ae A	394	mtspr chud_ppc_sprg1,r5
91447636 A	395	b mtspr64_success
91447636 A	396	mtspr64_sprg2:
55e303ae A	397	ld r5,0(r4)
55e303ae A	398	mtspr chud_ppc_sprg2,r5
91447636 A	399	b mtspr64_success
91447636 A	400	mtspr64_sprg3:
55e303ae A	401	ld r5,0(r4)
55e303ae A	402	mtspr chud_ppc_sprg3,r5
91447636 A	403	b mtspr64_success
91447636 A	404	mtspr64_asr:
55e303ae A	405	ld r5,0(r4)
55e303ae A	406	mtspr chud_ppc64_asr,r5
91447636 A	407	b mtspr64_success
91447636 A	408	mtspr64_dabr:
55e303ae A	409	ld r5,0(r4)
55e303ae A	410	mtspr chud_ppc_dabr,r5
91447636 A	411	b mtspr64_success
91447636 A	412	mtspr64_hid0:
55e303ae A	413	ld r5,0(r4)
	414	sync
	415	mtspr chud_970_hid0,r5
	416	mfspr r5,chud_970_hid0 /* syncronization requirements */
	417	mfspr r5,chud_970_hid0
	418	mfspr r5,chud_970_hid0
	419	mfspr r5,chud_970_hid0
	420	mfspr r5,chud_970_hid0
	421	mfspr r5,chud_970_hid0
91447636 A	422	b mtspr64_success
91447636 A	423	mtspr64_hid1:
55e303ae A	424	ld r5,0(r4)
	425	mtspr chud_970_hid1,r5 /* tell you twice */
	426	mtspr chud_970_hid1,r5
	427	isync
91447636 A	428	b mtspr64_success
91447636 A	429	mtspr64_hid4:
55e303ae A	430	ld r5,0(r4)
	431	sync /* syncronization requirements */
	432	mtspr chud_970_hid4,r5
	433	isync
91447636 A	434	b mtspr64_success
91447636 A	435	mtspr64_hid5:
55e303ae A	436	ld r5,0(r4)
55e303ae A	437	mtspr chud_970_hid5,r5
91447636 A	438	b mtspr64_success
91447636 A	439	mtspr64_mmcr0:
55e303ae A	440	ld r5,0(r4)
55e303ae A	441	mtspr chud_970_mmcr0,r5
91447636 A	442	b mtspr64_success
91447636 A	443	mtspr64_mmcr1:
55e303ae A	444	ld r5,0(r4)
55e303ae A	445	mtspr chud_970_mmcr1,r5
91447636 A	446	b mtspr64_success
91447636 A	447	mtspr64_mmcra:
55e303ae A	448	ld r5,0(r4)
55e303ae A	449	mtspr chud_970_mmcra,r5
91447636 A	450	b mtspr64_success
91447636 A	451	mtspr64_siar:
55e303ae A	452	ld r5,0(r4)
55e303ae A	453	mtspr chud_970_siar,r5
91447636 A	454	b mtspr64_success
91447636 A	455	mtspr64_sdar:
55e303ae A	456	ld r5,0(r4)
55e303ae A	457	mtspr chud_970_sdar,r5
91447636 A	458	b mtspr64_success
91447636 A	459	mtspr64_imc:
55e303ae A	460	ld r5,0(r4)
55e303ae A	461	mtspr chud_970_imc,r5
91447636 A	462	b mtspr64_success
91447636 A	463	mtspr64_rmor:
55e303ae A	464	ld r5,0(r4)
55e303ae A	465	mtspr chud_970_rmor,r5
91447636 A	466	b mtspr64_success
91447636 A	467	mtspr64_hrmor:
55e303ae A	468	ld r5,0(r4)
55e303ae A	469	mtspr chud_970_hrmor,r5
91447636 A	470	b mtspr64_success
91447636 A	471	mtspr64_hior:
55e303ae A	472	ld r5,0(r4)
55e303ae A	473	mtspr chud_970_hior,r5
91447636 A	474	b mtspr64_success
91447636 A	475	mtspr64_lpidr:
55e303ae A	476	ld r5,0(r4)
55e303ae A	477	mtspr chud_970_lpidr,r5
91447636 A	478	b mtspr64_success
91447636 A	479	mtspr64_lpcr:
55e303ae A	480	ld r5,0(r4)
55e303ae A	481	mtspr chud_970_lpcr,r5
91447636 A	482	b mtspr64_success
91447636 A	483	mtspr64_dabrx:
55e303ae	484	ld r5,0(r4)
91447636 A	485	mtspr chud_970_dabrx,r5
	486	b mtspr64_success
	487	mtspr64_hsprg0:
55e303ae A	488	ld r5,0(r4)
55e303ae A	489	mtspr chud_970_hsprg0,r5
91447636 A	490	b mtspr64_success
91447636 A	491	mtspr64_hsprg1:
55e303ae A	492	ld r5,0(r4)
55e303ae A	493	mtspr chud_970_hsprg1,r5
91447636 A	494	b mtspr64_success
91447636 A	495	mtspr64_hsrr0:
55e303ae A	496	ld r5,0(r4)
55e303ae A	497	mtspr chud_970_hsrr0,r5
91447636 A	498	b mtspr64_success
91447636 A	499	mtspr64_hsrr1:
55e303ae A	500	ld r5,0(r4)
55e303ae A	501	mtspr chud_970_hsrr1,r5
91447636 A	502	b mtspr64_success
91447636 A	503	mtspr64_hdec:
55e303ae A	504	ld r5,0(r4)
55e303ae A	505	mtspr chud_970_hdec,r5
91447636 A	506	b mtspr64_success
91447636 A	507	mtspr64_trig0:
55e303ae A	508	ld r5,0(r4)
55e303ae A	509	mtspr chud_970_trig0,r5
91447636 A	510	b mtspr64_success
91447636 A	511	mtspr64_trig1:
55e303ae A	512	ld r5,0(r4)
55e303ae A	513	mtspr chud_970_trig1,r5
91447636 A	514	b mtspr64_success
91447636 A	515	mtspr64_trig2:
55e303ae A	516	ld r5,0(r4)
55e303ae A	517	mtspr chud_970_trig2,r5
91447636 A	518	b mtspr64_success
91447636 A	519	mtspr64_accr:
55e303ae A	520	ld r5,0(r4)
55e303ae A	521	mtspr chud_ppc64_accr,r5
91447636 A	522	b mtspr64_success
91447636 A	523	mtspr64_scomc:
55e303ae A	524	ld r5,0(r4)
55e303ae A	525	mtspr chud_970_scomc,r5
91447636 A	526	b mtspr64_success
91447636 A	527	mtspr64_scomd:
55e303ae A	528	ld r5,0(r4)
55e303ae A	529	mtspr chud_970_scomd,r5
91447636 A	530	b mtspr64_success
	531
	532	mtspr64_failure:
	533	li r3,KERN_FAILURE
	534	blr
55e303ae	535
91447636 A	536	mtspr64_success:
	537	li r3,KERN_SUCCESS
	538	blr
	539
	540
	541	/*
	542	* kern_return_t mfmsr64(uint64_t *val);
	543	*
	544	* r3: address to store value in
	545	*
	546	*/
	547
	548	; Force a line boundry here
55e303ae	549	.align 5
91447636 A	550	.globl EXT(mfmsr64)
	551
	552	EXT(mfmsr64):
55e303ae A	553	mfmsr r5
55e303ae A	554	std r5,0(r3)
91447636 A	555	mfmsr64_success:
	556	li r3,KERN_SUCCESS
	557	blr
	558
	559	mfmsr64_failure:
	560	li r3,KERN_FAILURE
55e303ae A	561	blr
55e303ae A	562
91447636 A	563
	564	/*
	565	* kern_return_t mtmsr64(uint64_t *val);
	566	*
	567	* r3: address to load value from
	568	*
	569	*/
	570
	571	; Force a line boundry here
55e303ae	572	.align 5
91447636 A	573	.globl EXT(mtmsr64)
	574
	575	EXT(mtmsr64):
55e303ae A	576	ld r5,0(r3)
55e303ae A	577	mtmsrd r5
91447636 A	578	b mtmsr64_success
	579
	580	mtmsr64_success:
	581	li r3,KERN_SUCCESS
	582	blr
	583
	584	mtmsr64_failure:
	585	li r3,KERN_FAILURE
55e303ae A	586	blr
55e303ae A	587
4a249263	588	.L_end: