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1c79356b | 1 | /* |
b0d623f7 | 2 | * Copyright (c) 2000-2009 Apple Inc. All rights reserved. |
1c79356b | 3 | * |
2d21ac55 | 4 | * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ |
1c79356b | 5 | * |
2d21ac55 A |
6 | * This file contains Original Code and/or Modifications of Original Code |
7 | * as defined in and that are subject to the Apple Public Source License | |
8 | * Version 2.0 (the 'License'). You may not use this file except in | |
9 | * compliance with the License. The rights granted to you under the License | |
10 | * may not be used to create, or enable the creation or redistribution of, | |
11 | * unlawful or unlicensed copies of an Apple operating system, or to | |
12 | * circumvent, violate, or enable the circumvention or violation of, any | |
13 | * terms of an Apple operating system software license agreement. | |
8f6c56a5 | 14 | * |
2d21ac55 A |
15 | * Please obtain a copy of the License at |
16 | * http://www.opensource.apple.com/apsl/ and read it before using this file. | |
17 | * | |
18 | * The Original Code and all software distributed under the License are | |
19 | * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER | |
8f6c56a5 A |
20 | * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, |
21 | * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, | |
2d21ac55 A |
22 | * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. |
23 | * Please see the License for the specific language governing rights and | |
24 | * limitations under the License. | |
8f6c56a5 | 25 | * |
2d21ac55 | 26 | * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ |
1c79356b A |
27 | */ |
28 | /* | |
29 | * @OSF_COPYRIGHT@ | |
30 | */ | |
31 | ||
32 | #ifndef _I386_MACHINE_ROUTINES_H_ | |
33 | #define _I386_MACHINE_ROUTINES_H_ | |
34 | ||
35 | #include <mach/mach_types.h> | |
36 | #include <mach/boolean.h> | |
37 | #include <kern/kern_types.h> | |
38 | #include <pexpert/pexpert.h> | |
39 | ||
91447636 | 40 | #include <sys/cdefs.h> |
9bccf70c | 41 | #include <sys/appleapiopts.h> |
1c79356b | 42 | |
91447636 A |
43 | __BEGIN_DECLS |
44 | ||
b0d623f7 A |
45 | #ifdef XNU_KERNEL_PRIVATE |
46 | ||
0c530ab8 A |
47 | /* are we a 64 bit platform ? */ |
48 | ||
49 | boolean_t ml_is64bit(void); | |
50 | ||
51 | /* is this a 64bit thread? */ | |
52 | ||
53 | boolean_t ml_thread_is64bit(thread_t); | |
54 | ||
55 | /* is this a 64bit thread? */ | |
56 | ||
57 | boolean_t ml_state_is64bit(void *); | |
58 | ||
59 | /* set state of fpu save area for signal handling */ | |
60 | ||
61 | void ml_fp_setvalid(boolean_t); | |
62 | ||
63 | void ml_cpu_set_ldt(int); | |
64 | ||
1c79356b A |
65 | /* Interrupt handling */ |
66 | ||
55e303ae A |
67 | /* Initialize Interrupts */ |
68 | void ml_init_interrupt(void); | |
69 | ||
1c79356b A |
70 | /* Generate a fake interrupt */ |
71 | void ml_cause_interrupt(void); | |
72 | ||
b0d623f7 A |
73 | /* Initialize Interrupts */ |
74 | void ml_install_interrupt_handler( | |
75 | void *nub, | |
76 | int source, | |
77 | void *target, | |
78 | IOInterruptHandler handler, | |
79 | void *refCon); | |
80 | ||
9bccf70c | 81 | void ml_get_timebase(unsigned long long *timestamp); |
0c530ab8 | 82 | void ml_init_lock_timeout(void); |
316670eb A |
83 | void ml_init_delay_spin_threshold(void); |
84 | ||
85 | boolean_t ml_delay_should_spin(uint64_t interval); | |
d52fe63f | 86 | |
b0d623f7 A |
87 | vm_offset_t |
88 | ml_static_ptovirt( | |
89 | vm_offset_t); | |
90 | ||
91 | void ml_static_mfree( | |
92 | vm_offset_t, | |
93 | vm_size_t); | |
94 | ||
95 | /* boot memory allocation */ | |
96 | vm_offset_t ml_static_malloc( | |
97 | vm_size_t size); | |
98 | ||
99 | /* virtual to physical on wired pages */ | |
100 | vm_offset_t ml_vtophys( | |
101 | vm_offset_t vaddr); | |
102 | ||
103 | vm_size_t ml_nofault_copy( | |
104 | vm_offset_t virtsrc, vm_offset_t virtdst, vm_size_t size); | |
105 | ||
106 | /* Machine topology info */ | |
107 | uint64_t ml_cpu_cache_size(unsigned int level); | |
108 | uint64_t ml_cpu_cache_sharing(unsigned int level); | |
109 | ||
110 | /* Initialize the maximum number of CPUs */ | |
111 | void ml_init_max_cpus( | |
112 | unsigned long max_cpus); | |
113 | ||
114 | extern void ml_cpu_up(void); | |
115 | extern void ml_cpu_down(void); | |
116 | ||
117 | void bzero_phys_nc( | |
118 | addr64_t phys_address, | |
119 | uint32_t length); | |
120 | ||
121 | #if defined(PEXPERT_KERNEL_PRIVATE) || defined(MACH_KERNEL_PRIVATE) | |
122 | /* IO memory map services */ | |
123 | ||
124 | /* Map memory map IO space */ | |
125 | vm_offset_t ml_io_map( | |
126 | vm_offset_t phys_addr, | |
127 | vm_size_t size); | |
128 | ||
b0d623f7 A |
129 | |
130 | void ml_get_bouncepool_info( | |
131 | vm_offset_t *phys_addr, | |
132 | vm_size_t *size); | |
060df5ea A |
133 | /* Indicates if spinlock, IPI and other timeouts should be suspended */ |
134 | boolean_t machine_timeout_suspended(void); | |
b0d623f7 A |
135 | #endif /* PEXPERT_KERNEL_PRIVATE || MACH_KERNEL_PRIVATE */ |
136 | ||
6d2010ae A |
137 | /* Warm up a CPU to receive an interrupt */ |
138 | kern_return_t ml_interrupt_prewarm(uint64_t deadline); | |
060df5ea | 139 | |
b0d623f7 A |
140 | #endif /* XNU_KERNEL_PRIVATE */ |
141 | ||
142 | #ifdef KERNEL_PRIVATE | |
143 | ||
55e303ae A |
144 | /* Type for the Time Base Enable function */ |
145 | typedef void (*time_base_enable_t)(cpu_id_t cpu_id, boolean_t enable); | |
146 | ||
9bccf70c A |
147 | /* Type for the IPI Hander */ |
148 | typedef void (*ipi_handler_t)(void); | |
149 | ||
55e303ae A |
150 | /* Struct for ml_processor_register */ |
151 | struct ml_processor_info { | |
152 | cpu_id_t cpu_id; | |
153 | boolean_t boot_cpu; | |
154 | vm_offset_t start_paddr; | |
155 | boolean_t supports_nap; | |
156 | unsigned long l2cr_value; | |
157 | time_base_enable_t time_base_enable; | |
158 | }; | |
159 | ||
160 | typedef struct ml_processor_info ml_processor_info_t; | |
161 | ||
91447636 | 162 | |
9bccf70c | 163 | /* Register a processor */ |
b0d623f7 A |
164 | kern_return_t |
165 | ml_processor_register( | |
166 | cpu_id_t cpu_id, | |
167 | uint32_t lapic_id, | |
168 | processor_t *processor_out, | |
169 | boolean_t boot_cpu, | |
170 | boolean_t start ); | |
0c530ab8 | 171 | |
43866e37 A |
172 | /* PCI config cycle probing */ |
173 | boolean_t ml_probe_read( | |
174 | vm_offset_t paddr, | |
175 | unsigned int *val); | |
55e303ae A |
176 | boolean_t ml_probe_read_64( |
177 | addr64_t paddr, | |
178 | unsigned int *val); | |
43866e37 A |
179 | |
180 | /* Read physical address byte */ | |
181 | unsigned int ml_phys_read_byte( | |
182 | vm_offset_t paddr); | |
55e303ae A |
183 | unsigned int ml_phys_read_byte_64( |
184 | addr64_t paddr); | |
43866e37 A |
185 | |
186 | /* Read physical address half word */ | |
187 | unsigned int ml_phys_read_half( | |
188 | vm_offset_t paddr); | |
55e303ae A |
189 | unsigned int ml_phys_read_half_64( |
190 | addr64_t paddr); | |
43866e37 A |
191 | |
192 | /* Read physical address word*/ | |
193 | unsigned int ml_phys_read( | |
194 | vm_offset_t paddr); | |
55e303ae A |
195 | unsigned int ml_phys_read_64( |
196 | addr64_t paddr); | |
43866e37 A |
197 | unsigned int ml_phys_read_word( |
198 | vm_offset_t paddr); | |
55e303ae A |
199 | unsigned int ml_phys_read_word_64( |
200 | addr64_t paddr); | |
43866e37 A |
201 | |
202 | /* Read physical address double word */ | |
203 | unsigned long long ml_phys_read_double( | |
204 | vm_offset_t paddr); | |
55e303ae A |
205 | unsigned long long ml_phys_read_double_64( |
206 | addr64_t paddr); | |
43866e37 A |
207 | |
208 | /* Write physical address byte */ | |
209 | void ml_phys_write_byte( | |
210 | vm_offset_t paddr, unsigned int data); | |
55e303ae A |
211 | void ml_phys_write_byte_64( |
212 | addr64_t paddr, unsigned int data); | |
43866e37 A |
213 | |
214 | /* Write physical address half word */ | |
215 | void ml_phys_write_half( | |
216 | vm_offset_t paddr, unsigned int data); | |
55e303ae A |
217 | void ml_phys_write_half_64( |
218 | addr64_t paddr, unsigned int data); | |
43866e37 A |
219 | |
220 | /* Write physical address word */ | |
221 | void ml_phys_write( | |
222 | vm_offset_t paddr, unsigned int data); | |
55e303ae A |
223 | void ml_phys_write_64( |
224 | addr64_t paddr, unsigned int data); | |
43866e37 A |
225 | void ml_phys_write_word( |
226 | vm_offset_t paddr, unsigned int data); | |
55e303ae A |
227 | void ml_phys_write_word_64( |
228 | addr64_t paddr, unsigned int data); | |
43866e37 A |
229 | |
230 | /* Write physical address double word */ | |
231 | void ml_phys_write_double( | |
232 | vm_offset_t paddr, unsigned long long data); | |
55e303ae A |
233 | void ml_phys_write_double_64( |
234 | addr64_t paddr, unsigned long long data); | |
43866e37 | 235 | |
43866e37 A |
236 | /* Struct for ml_cpu_get_info */ |
237 | struct ml_cpu_info { | |
6d2010ae A |
238 | uint32_t vector_unit; |
239 | uint32_t cache_line_size; | |
240 | uint32_t l1_icache_size; | |
241 | uint32_t l1_dcache_size; | |
242 | uint32_t l2_settings; | |
243 | uint32_t l2_cache_size; | |
244 | uint32_t l3_settings; | |
245 | uint32_t l3_cache_size; | |
43866e37 A |
246 | }; |
247 | ||
248 | typedef struct ml_cpu_info ml_cpu_info_t; | |
249 | ||
250 | /* Get processor info */ | |
91447636 | 251 | void ml_cpu_get_info(ml_cpu_info_t *ml_cpu_info); |
43866e37 | 252 | |
9bccf70c A |
253 | void ml_thread_policy( |
254 | thread_t thread, | |
255 | unsigned policy_id, | |
256 | unsigned policy_info); | |
1c79356b | 257 | |
9bccf70c A |
258 | #define MACHINE_GROUP 0x00000001 |
259 | #define MACHINE_NETWORK_GROUP 0x10000000 | |
260 | #define MACHINE_NETWORK_WORKLOOP 0x00000001 | |
261 | #define MACHINE_NETWORK_NETISR 0x00000002 | |
1c79356b | 262 | |
43866e37 A |
263 | /* Return the maximum number of CPUs set by ml_init_max_cpus() */ |
264 | int ml_get_max_cpus( | |
265 | void); | |
266 | ||
2d21ac55 A |
267 | /* |
268 | * The following are in pmCPU.c not machine_routines.c. | |
269 | */ | |
0c530ab8 A |
270 | extern void ml_set_maxsnoop(uint32_t maxdelay); |
271 | extern unsigned ml_get_maxsnoop(void); | |
272 | extern void ml_set_maxbusdelay(uint32_t mdelay); | |
273 | extern uint32_t ml_get_maxbusdelay(void); | |
593a1d5f A |
274 | extern void ml_set_maxintdelay(uint64_t mdelay); |
275 | extern uint64_t ml_get_maxintdelay(void); | |
6d2010ae | 276 | extern boolean_t ml_get_interrupt_prewake_applicable(void); |
2d21ac55 A |
277 | |
278 | ||
0c530ab8 A |
279 | extern uint64_t tmrCvt(uint64_t time, uint64_t conversion); |
280 | ||
2d21ac55 A |
281 | extern uint64_t ml_cpu_int_event_time(void); |
282 | ||
b0d623f7 A |
283 | #endif /* KERNEL_PRIVATE */ |
284 | ||
285 | /* Get Interrupts Enabled */ | |
286 | boolean_t ml_get_interrupts_enabled(void); | |
287 | ||
288 | /* Set Interrupts Enabled */ | |
289 | boolean_t ml_set_interrupts_enabled(boolean_t enable); | |
290 | ||
291 | /* Check if running at interrupt context */ | |
292 | boolean_t ml_at_interrupt_context(void); | |
293 | ||
294 | /* Zero bytes starting at a physical address */ | |
295 | void bzero_phys( | |
296 | addr64_t phys_address, | |
297 | uint32_t length); | |
298 | ||
299 | /* Bytes available on current stack */ | |
300 | vm_offset_t ml_stack_remaining(void); | |
301 | ||
302 | #if CONFIG_COUNTERS | |
303 | void ml_get_csw_threads(thread_t * /*old*/, thread_t * /*new*/); | |
304 | #endif /* CONFIG_COUNTERS */ | |
1c79356b | 305 | |
91447636 A |
306 | __END_DECLS |
307 | ||
6d2010ae | 308 | #ifdef XNU_KERNEL_PRIVATE |
316670eb | 309 | |
6d2010ae | 310 | boolean_t ml_fpu_avx_enabled(void); |
316670eb | 311 | |
6d2010ae A |
312 | void interrupt_latency_tracker_setup(void); |
313 | void interrupt_reset_latency_stats(void); | |
314 | void interrupt_populate_latency_stats(char *, unsigned); | |
060df5ea | 315 | |
6d2010ae | 316 | #endif /* XNU_KERNEL_PRIVATE */ |
1c79356b | 317 | #endif /* _I386_MACHINE_ROUTINES_H_ */ |