[apple/xnu.git] / osfmk / i386 / mtrr.c

/*
 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
 * 
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. The rights granted to you under the License
 * may not be used to create, or enable the creation or redistribution of,
 * unlawful or unlicensed copies of an Apple operating system, or to
 * circumvent, violate, or enable the circumvention or violation of, any
 * terms of an Apple operating system software license agreement.
 * 
 * Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this file.
 * 
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 * 
 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
 */

#include <mach/kern_return.h>
#include <kern/kalloc.h>
#include <kern/cpu_number.h>
#include <kern/cpu_data.h>
#include <i386/cpuid.h>
#include <i386/mp.h>
#include <i386/proc_reg.h>
#include <i386/mtrr.h>

struct mtrr_var_range {
	uint64_t  base;		/* in IA32_MTRR_PHYSBASE format */
	uint64_t  mask;		/* in IA32_MTRR_PHYSMASK format */
	uint32_t  refcnt;	/* var ranges reference count */
};

struct mtrr_fix_range {
	uint64_t  types;	/* fixed-range type octet */
};

typedef struct mtrr_var_range mtrr_var_range_t;
typedef struct mtrr_fix_range mtrr_fix_range_t;

static struct {
	uint64_t            MTRRcap;
	uint64_t            MTRRdefType;
	mtrr_var_range_t *  var_range;
	unsigned int        var_count;
	mtrr_fix_range_t    fix_range[11];
} mtrr_state;

static boolean_t mtrr_initialized = FALSE;

decl_simple_lock_data(static, mtrr_lock);
#define MTRR_LOCK()	simple_lock(&mtrr_lock);
#define MTRR_UNLOCK()	simple_unlock(&mtrr_lock);

#if	MTRR_DEBUG
#define DBG(x...)	kprintf(x)
#else
#define DBG(x...)
#endif

/* Private functions */
static void mtrr_get_var_ranges(mtrr_var_range_t * range, int count);
static void mtrr_set_var_ranges(const mtrr_var_range_t * range, int count);
static void mtrr_get_fix_ranges(mtrr_fix_range_t * range);
static void mtrr_set_fix_ranges(const mtrr_fix_range_t * range);
static void mtrr_update_setup(void * param);
static void mtrr_update_teardown(void * param);
static void mtrr_update_action(void * param);
static void var_range_encode(mtrr_var_range_t * range, addr64_t address,
                             uint64_t length, uint32_t type, int valid);
static int  var_range_overlap(mtrr_var_range_t * range, addr64_t address,
                              uint64_t length, uint32_t type);

#define CACHE_CONTROL_MTRR		(NULL)
#define CACHE_CONTROL_PAT		((void *)1)

/*
 * MTRR MSR bit fields.
 */
#define IA32_MTRR_DEF_TYPE_MT		0x000000ff
#define IA32_MTRR_DEF_TYPE_FE		0x00000400
#define IA32_MTRR_DEF_TYPE_E		0x00000800

#define IA32_MTRRCAP_VCNT		0x000000ff
#define IA32_MTRRCAP_FIX		0x00000100
#define IA32_MTRRCAP_WC			0x00000400

/* 0 < bits <= 64 */
#define PHYS_BITS_TO_MASK(bits) \
	((((1ULL << (bits-1)) - 1) << 1) | 1)

/*
 * Default mask for 36 physical address bits, this can
 * change depending on the cpu model.
 */
static uint64_t mtrr_phys_mask = PHYS_BITS_TO_MASK(36);

#define IA32_MTRR_PHYMASK_VALID		0x0000000000000800ULL
#define IA32_MTRR_PHYSBASE_MASK		(mtrr_phys_mask & ~0x0000000000000FFFULL)
#define IA32_MTRR_PHYSBASE_TYPE		0x00000000000000FFULL

/*
 * Variable-range mask to/from length conversions.
 */
#define MASK_TO_LEN(mask) \
	((~((mask) & IA32_MTRR_PHYSBASE_MASK) & mtrr_phys_mask) + 1)

#define LEN_TO_MASK(len)  \
	(~((len) - 1) & IA32_MTRR_PHYSBASE_MASK)

#define LSB(x)		((x) & (~((x) - 1)))

/*
 * Fetch variable-range MTRR register pairs.
 */
static void
mtrr_get_var_ranges(mtrr_var_range_t * range, int count)
{
	int i;

	for (i = 0; i < count; i++) {
		range[i].base = rdmsr64(MSR_IA32_MTRR_PHYSBASE(i));
		range[i].mask = rdmsr64(MSR_IA32_MTRR_PHYSMASK(i));

		/* bump ref count for firmware configured ranges */
		if (range[i].mask & IA32_MTRR_PHYMASK_VALID)
			range[i].refcnt = 1;
		else
			range[i].refcnt = 0;
	}
}

/*
 * Update variable-range MTRR register pairs.
 */
static void
mtrr_set_var_ranges(const mtrr_var_range_t * range, int count)
{
	int i;

	for (i = 0; i < count; i++) {
		wrmsr64(MSR_IA32_MTRR_PHYSBASE(i), range[i].base);
		wrmsr64(MSR_IA32_MTRR_PHYSMASK(i), range[i].mask);
	}
}

/*
 * Fetch all fixed-range MTRR's. Note MSR offsets are not consecutive.
 */
static void
mtrr_get_fix_ranges(mtrr_fix_range_t * range)
{
	int i;

	/* assume 11 fix range registers */
	range[0].types = rdmsr64(MSR_IA32_MTRR_FIX64K_00000);
	range[1].types = rdmsr64(MSR_IA32_MTRR_FIX16K_80000);
	range[2].types = rdmsr64(MSR_IA32_MTRR_FIX16K_A0000);
	for (i = 0; i < 8; i++)
		range[3 + i].types = rdmsr64(MSR_IA32_MTRR_FIX4K_C0000 + i);
}

/*
 * Update all fixed-range MTRR's.
 */
static void
mtrr_set_fix_ranges(const struct mtrr_fix_range * range)
{
	int i;

	/* assume 11 fix range registers */
	wrmsr64(MSR_IA32_MTRR_FIX64K_00000, range[0].types);
	wrmsr64(MSR_IA32_MTRR_FIX16K_80000, range[1].types);
	wrmsr64(MSR_IA32_MTRR_FIX16K_A0000, range[2].types);
	for (i = 0; i < 8; i++)
		wrmsr64(MSR_IA32_MTRR_FIX4K_C0000 + i, range[3 + i].types);
}

static boolean_t
mtrr_check_fix_ranges(const struct mtrr_fix_range * range)
{
	int		i;
	boolean_t	match = TRUE;

	DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);

	/* assume 11 fix range registers */
	match = range[0].types == rdmsr64(MSR_IA32_MTRR_FIX64K_00000) &&
		range[1].types == rdmsr64(MSR_IA32_MTRR_FIX16K_80000) &&
		range[2].types == rdmsr64(MSR_IA32_MTRR_FIX16K_A0000);
	for (i = 0; match && i < 8; i++) {
		match = range[3 + i].types ==
			rdmsr64(MSR_IA32_MTRR_FIX4K_C0000 + i);
	}

	return match;
}

static boolean_t
mtrr_check_var_ranges(mtrr_var_range_t * range, int count)
{
	int		i;
	boolean_t	match = TRUE;
 
	DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);

	for (i = 0; match && i < count; i++) {
		match = range[i].base == rdmsr64(MSR_IA32_MTRR_PHYSBASE(i)) &&
			range[i].mask == rdmsr64(MSR_IA32_MTRR_PHYSMASK(i));
	}

	return match;
}

#if MTRR_DEBUG
static void
mtrr_msr_dump(void)
{
	int i;
	int count = rdmsr64(MSR_IA32_MTRRCAP) & IA32_MTRRCAP_VCNT;

	DBG("VAR -- BASE -------------- MASK -------------- SIZE\n");
	for (i = 0; i < count; i++) {
		DBG(" %02x    0x%016llx  0x%016llx  0x%llx\n", i,
		    rdmsr64(MSR_IA32_MTRR_PHYSBASE(i)),
		    rdmsr64(MSR_IA32_MTRR_PHYSMASK(i)),
		    MASK_TO_LEN(rdmsr64(MSR_IA32_MTRR_PHYSMASK(i))));
	}
	DBG("\n");

	DBG("FIX64K_00000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX64K_00000));
	DBG("FIX16K_80000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX16K_80000));
	DBG("FIX16K_A0000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX16K_A0000));
	DBG(" FIX4K_C0000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_C0000));
	DBG(" FIX4K_C8000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_C8000));
	DBG(" FIX4K_D0000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_D0000));
	DBG(" FIX4K_D8000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_D8000));
	DBG(" FIX4K_E0000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_E0000));
	DBG(" FIX4K_E8000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_E8000));
	DBG(" FIX4K_F0000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_F0000));
	DBG(" FIX4K_F8000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_F8000));

	DBG("\nMTRRcap = 0x%llx MTRRdefType = 0x%llx\n",
            rdmsr64(MSR_IA32_MTRRCAP), rdmsr64(MSR_IA32_MTRR_DEF_TYPE));
}
#endif /* MTRR_DEBUG */

/*
 * Called by the boot processor (BP) early during boot to initialize MTRR
 * support.  The MTRR state on the BP is saved, any additional processors
 * will have the same settings applied to ensure MTRR consistency.
 */
void
mtrr_init(void)
{
	/* no reason to init more than once */
	if (mtrr_initialized == TRUE)
		return;

	/* check for presence of MTRR feature on the processor */
	if ((cpuid_features() & CPUID_FEATURE_MTRR) == 0)
        	return;  /* no MTRR feature */

	/* use a lock to serialize MTRR changes */
	bzero((void *)&mtrr_state, sizeof(mtrr_state));
	simple_lock_init(&mtrr_lock, 0);

	mtrr_state.MTRRcap     = rdmsr64(MSR_IA32_MTRRCAP);
	mtrr_state.MTRRdefType = rdmsr64(MSR_IA32_MTRR_DEF_TYPE);
	mtrr_state.var_count   = (unsigned int)(mtrr_state.MTRRcap & IA32_MTRRCAP_VCNT);

	/* allocate storage for variable ranges (can block?) */
	if (mtrr_state.var_count) {
		mtrr_state.var_range = (mtrr_var_range_t *)
		                       kalloc(sizeof(mtrr_var_range_t) *
		                              mtrr_state.var_count);
		if (mtrr_state.var_range == NULL)
			mtrr_state.var_count = 0;
	}

	/* fetch the initial firmware configured variable ranges */
	if (mtrr_state.var_count)
		mtrr_get_var_ranges(mtrr_state.var_range,
				    mtrr_state.var_count);

	/* fetch the initial firmware configured fixed ranges */
	if (mtrr_state.MTRRcap & IA32_MTRRCAP_FIX)
		mtrr_get_fix_ranges(mtrr_state.fix_range);

	mtrr_initialized = TRUE;

#if MTRR_DEBUG
	mtrr_msr_dump();	/* dump firmware settings */
#endif

}

/*
 * Performs the Intel recommended procedure for changing the MTRR
 * in a MP system. Leverage rendezvous mechanism for the required
 * barrier synchronization among all processors. This function is
 * called from the rendezvous IPI handler, and mtrr_update_cpu().
 */
static void
mtrr_update_action(void * cache_control_type)
{
	uintptr_t cr0, cr4;
	uintptr_t tmp;

	cr0 = get_cr0();
	cr4 = get_cr4();

	/* enter no-fill cache mode */
	tmp = cr0 | CR0_CD;
	tmp &= ~CR0_NW;
	set_cr0(tmp);

	/* flush caches */
	wbinvd();

	/* clear the PGE flag in CR4 */
	if (cr4 & CR4_PGE)
		set_cr4(cr4 & ~CR4_PGE);

	/* flush TLBs */
	flush_tlb_raw();

	if (CACHE_CONTROL_PAT == cache_control_type) {
		/* Change PA6 attribute field to WC */
		uint64_t pat = rdmsr64(MSR_IA32_CR_PAT);
		DBG("CPU%d PAT: was 0x%016llx\n", get_cpu_number(), pat);
		pat &= ~(0x0FULL << 48);
		pat |=  (0x01ULL << 48);
		wrmsr64(MSR_IA32_CR_PAT, pat);
		DBG("CPU%d PAT: is  0x%016llx\n",
		    get_cpu_number(), rdmsr64(MSR_IA32_CR_PAT));
	}
	else {
		/* disable all MTRR ranges */
		wrmsr64(MSR_IA32_MTRR_DEF_TYPE,
			mtrr_state.MTRRdefType & ~IA32_MTRR_DEF_TYPE_E);

		/* apply MTRR settings */
		if (mtrr_state.var_count)
			mtrr_set_var_ranges(mtrr_state.var_range,
					mtrr_state.var_count);

		if (mtrr_state.MTRRcap & IA32_MTRRCAP_FIX)
			mtrr_set_fix_ranges(mtrr_state.fix_range);

		/* enable all MTRR range registers (what if E was not set?) */
		wrmsr64(MSR_IA32_MTRR_DEF_TYPE,
			mtrr_state.MTRRdefType | IA32_MTRR_DEF_TYPE_E);
	}

	/* flush all caches and TLBs a second time */
	wbinvd();
	flush_tlb_raw();

	/* restore normal cache mode */
	set_cr0(cr0);

	/* restore PGE flag */
	if (cr4 & CR4_PGE)
		set_cr4(cr4);

	DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);
}

static void
mtrr_update_setup(__unused void * param_not_used)
{
	/* disable interrupts before the first barrier */
	current_cpu_datap()->cpu_iflag = ml_set_interrupts_enabled(FALSE);
	DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);
}

static void
mtrr_update_teardown(__unused void * param_not_used)
{
	/* restore interrupt flag following MTRR changes */
	ml_set_interrupts_enabled(current_cpu_datap()->cpu_iflag);
	DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);
}

/*
 * Update MTRR settings on all processors.
 */
kern_return_t
mtrr_update_all_cpus(void)
{
	if (mtrr_initialized == FALSE)
		return KERN_NOT_SUPPORTED;

	MTRR_LOCK();
	mp_rendezvous(mtrr_update_setup,
		      mtrr_update_action,
		      mtrr_update_teardown, NULL);
	MTRR_UNLOCK();

	return KERN_SUCCESS;
}

/*
 * Verify that a processor has been set with the BSP's MTRR settings. Called
 * during slave processor initialization to check and set MTRR settings
 * discovered on the boot processor by mtrr_init().
 */
kern_return_t
mtrr_update_cpu(void)
{
	boolean_t	match = TRUE;

	if (mtrr_initialized == FALSE)
		return KERN_NOT_SUPPORTED;

	DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);

	MTRR_LOCK();

	/* Check MSR_IA32_MTRR_DEF_TYPE MSR */
	match = mtrr_state.MTRRdefType == rdmsr64(MSR_IA32_MTRR_DEF_TYPE);

	/* Check MSR_IA32_MTRRCAP MSR */
	if (match) {
		match = mtrr_state.MTRRcap == rdmsr64(MSR_IA32_MTRRCAP);
	}

	/* Check variable ranges */
	if (match && mtrr_state.var_count) {
		match = mtrr_check_var_ranges(mtrr_state.var_range,
					      mtrr_state.var_count);
	}

	/* Check fixed ranges */
	if (match && (mtrr_state.MTRRcap & IA32_MTRRCAP_FIX)) {
		match = mtrr_check_fix_ranges(mtrr_state.fix_range);
	}

#if MTRR_DEBUG
	if (!match)
		mtrr_msr_dump();
#endif
	if (!match) {
		DBG("mtrr_update_cpu() setting MTRR for cpu %d\n",
			get_cpu_number());
		mtrr_update_action(NULL);
	}
#if MTRR_DEBUG
	if (!match)
		mtrr_msr_dump();
#endif

	MTRR_UNLOCK();

	return KERN_SUCCESS;
}

/*
 * Add a MTRR range to associate the physical memory range specified
 * with a given memory caching type.
 */
kern_return_t
mtrr_range_add(addr64_t address, uint64_t length, uint32_t type)
{
	mtrr_var_range_t * vr;
	mtrr_var_range_t * free_range;
	kern_return_t      ret = KERN_NO_SPACE;
	int                overlap;
	unsigned int       i;

	DBG("mtrr_range_add base = 0x%llx, size = 0x%llx, type = %d\n",
            address, length, type);

	if (mtrr_initialized == FALSE) {
		return KERN_NOT_SUPPORTED;
	}

	/* check memory type (GPF exception for undefined types) */
	if ((type != MTRR_TYPE_UNCACHEABLE)  &&
	    (type != MTRR_TYPE_WRITECOMBINE) &&
	    (type != MTRR_TYPE_WRITETHROUGH) &&
	    (type != MTRR_TYPE_WRITEPROTECT) &&
	    (type != MTRR_TYPE_WRITEBACK)) {
		return KERN_INVALID_ARGUMENT;
	}

	/* check WC support if requested */
	if ((type == MTRR_TYPE_WRITECOMBINE) &&
	    (mtrr_state.MTRRcap & IA32_MTRRCAP_WC) == 0) {
		return KERN_NOT_SUPPORTED;
	}

	/* leave the fix range area below 1MB alone */
	if (address < 0x100000 || mtrr_state.var_count == 0) {
		return KERN_NOT_SUPPORTED;
	}

	/*
	 * Length must be a power of 2 given by 2^n, where n >= 12.
	 * Base address alignment must be larger than or equal to length.
	 */
	if ((length < 0x1000)       ||
	    (LSB(length) != length) ||
            (address && (length > LSB(address)))) {
		return KERN_INVALID_ARGUMENT;
	}

	MTRR_LOCK();

	/*
	 * Check for overlap and locate a free range.
	 */
	for (i = 0, free_range = NULL; i < mtrr_state.var_count; i++)
	{
		vr = &mtrr_state.var_range[i];

		if (vr->refcnt == 0) {
			/* free range candidate if no overlaps are found */
			free_range = vr;
			continue;
		}

		overlap = var_range_overlap(vr, address, length, type);
		if (overlap > 0) {
			/*
			 * identical overlap permitted, increment ref count.
			 * no hardware update required.
			 */
			free_range = vr;
			break;
		}
		if (overlap < 0) {
			/* unsupported overlapping of memory types */
			free_range = NULL;
			break;
		}
	}

	if (free_range) {
		if (free_range->refcnt++ == 0) {
			var_range_encode(free_range, address, length, type, 1);
			mp_rendezvous(mtrr_update_setup,
				      mtrr_update_action,
				      mtrr_update_teardown, NULL);
		}
		ret = KERN_SUCCESS;
	}

#if MTRR_DEBUG
	mtrr_msr_dump();
#endif

	MTRR_UNLOCK();

	return ret;
}

/*
 * Remove a previously added MTRR range. The same arguments used for adding
 * the memory range must be supplied again.
 */
kern_return_t
mtrr_range_remove(addr64_t address, uint64_t length, uint32_t type)
{
	mtrr_var_range_t * vr;
	int                result = KERN_FAILURE;
	int                cpu_update = 0;
	unsigned int       i;

	DBG("mtrr_range_remove base = 0x%llx, size = 0x%llx, type = %d\n",
            address, length, type);

	if (mtrr_initialized == FALSE) {
		return KERN_NOT_SUPPORTED;
	}

	MTRR_LOCK();

	for (i = 0; i < mtrr_state.var_count; i++) {
		vr = &mtrr_state.var_range[i];

		if (vr->refcnt &&
		    var_range_overlap(vr, address, length, type) > 0) {
			/* found specified variable range */
			if (--mtrr_state.var_range[i].refcnt == 0) {
				var_range_encode(vr, address, length, type, 0);
				cpu_update = 1;
			}
			result = KERN_SUCCESS;
			break;
		}
	}

	if (cpu_update) {
		mp_rendezvous(mtrr_update_setup,
			      mtrr_update_action,
			      mtrr_update_teardown, NULL);
		result = KERN_SUCCESS;
	}

#if MTRR_DEBUG
	mtrr_msr_dump();
#endif

	MTRR_UNLOCK();

	return result;
}

/*
 * Variable range helper routines
 */
static void
var_range_encode(mtrr_var_range_t * range, addr64_t address,
		 uint64_t length, uint32_t type, int valid)
{
	range->base = (address & IA32_MTRR_PHYSBASE_MASK) |
		      (type    & (uint32_t)IA32_MTRR_PHYSBASE_TYPE);

	range->mask = LEN_TO_MASK(length) |
		      (valid ? IA32_MTRR_PHYMASK_VALID : 0);
}

static int
var_range_overlap(mtrr_var_range_t * range, addr64_t address,
		  uint64_t length, uint32_t type)
{
	uint64_t  v_address, v_length;
	uint32_t  v_type;
	int       result = 0;  /* no overlap, or overlap ok */

	v_address = range->base & IA32_MTRR_PHYSBASE_MASK;
	v_type    = (uint32_t)(range->base & IA32_MTRR_PHYSBASE_TYPE);
	v_length  = MASK_TO_LEN(range->mask);

	/* detect range overlap */
	if ((v_address >= address && v_address < (address + length)) ||
	    (address >= v_address && address < (v_address + v_length))) {

		if (v_address == address && v_length == length && v_type == type)
			result = 1; /* identical overlap ok */
		else if ( v_type == MTRR_TYPE_UNCACHEABLE &&
			    type == MTRR_TYPE_UNCACHEABLE ) {
			/* UC ranges can overlap */
		}
		else if ((v_type == MTRR_TYPE_UNCACHEABLE &&
		            type == MTRR_TYPE_WRITEBACK)  ||
			 (v_type == MTRR_TYPE_WRITEBACK &&
			    type == MTRR_TYPE_UNCACHEABLE)) {
			/* UC/WB can overlap - effective type becomes UC */
		}
		else {
			/* anything else may cause undefined behavior */
			result = -1;
		}
	}

	return result;
}

/*
 * Initialize PAT (Page Attribute Table)
 */
void
pat_init(void)
{
	boolean_t	istate;
	uint64_t	pat;

	if (!(cpuid_features() & CPUID_FEATURE_PAT))
		return;

	istate = ml_set_interrupts_enabled(FALSE);

	pat = rdmsr64(MSR_IA32_CR_PAT);
	DBG("CPU%d PAT: was 0x%016llx\n", get_cpu_number(), pat);

	/* Change PA6 attribute field to WC if required */
	if ((pat & ~(0x0FULL << 48)) != (0x01ULL << 48)) {
		mtrr_update_action(CACHE_CONTROL_PAT);
	}
	ml_set_interrupts_enabled(istate);
}
Commit	Line	Data
91447636 A	1	/*
	2	* Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
	3	*
2d21ac55	4	* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
91447636	5	*
2d21ac55 A	6	* This file contains Original Code and/or Modifications of Original Code
	7	* as defined in and that are subject to the Apple Public Source License
	8	* Version 2.0 (the 'License'). You may not use this file except in
	9	* compliance with the License. The rights granted to you under the License
	10	* may not be used to create, or enable the creation or redistribution of,
	11	* unlawful or unlicensed copies of an Apple operating system, or to
	12	* circumvent, violate, or enable the circumvention or violation of, any
	13	* terms of an Apple operating system software license agreement.
8f6c56a5	14	*
2d21ac55 A	15	* Please obtain a copy of the License at
	16	* http://www.opensource.apple.com/apsl/ and read it before using this file.
	17	*
	18	* The Original Code and all software distributed under the License are
	19	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
8f6c56a5 A	20	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
8f6c56a5 A	21	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
2d21ac55 A	22	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	23	* Please see the License for the specific language governing rights and
	24	* limitations under the License.
8f6c56a5	25	*
2d21ac55	26	* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
91447636 A	27	*/
	28
	29	#include <mach/kern_return.h>
	30	#include <kern/kalloc.h>
	31	#include <kern/cpu_number.h>
	32	#include <kern/cpu_data.h>
91447636	33	#include <i386/cpuid.h>
b0d623f7	34	#include <i386/mp.h>
91447636 A	35	#include <i386/proc_reg.h>
	36	#include <i386/mtrr.h>
	37
	38	struct mtrr_var_range {
	39	uint64_t base; /* in IA32_MTRR_PHYSBASE format */
	40	uint64_t mask; /* in IA32_MTRR_PHYSMASK format */
	41	uint32_t refcnt; /* var ranges reference count */
	42	};
	43
	44	struct mtrr_fix_range {
	45	uint64_t types; /* fixed-range type octet */
	46	};
	47
	48	typedef struct mtrr_var_range mtrr_var_range_t;
	49	typedef struct mtrr_fix_range mtrr_fix_range_t;
	50
	51	static struct {
	52	uint64_t MTRRcap;
	53	uint64_t MTRRdefType;
	54	mtrr_var_range_t * var_range;
	55	unsigned int var_count;
	56	mtrr_fix_range_t fix_range[11];
	57	} mtrr_state;
	58
	59	static boolean_t mtrr_initialized = FALSE;
	60
	61	decl_simple_lock_data(static, mtrr_lock);
	62	#define MTRR_LOCK() simple_lock(&mtrr_lock);
	63	#define MTRR_UNLOCK() simple_unlock(&mtrr_lock);
	64
	65	#if MTRR_DEBUG
	66	#define DBG(x...) kprintf(x)
	67	#else
	68	#define DBG(x...)
	69	#endif
	70
	71	/* Private functions */
	72	static void mtrr_get_var_ranges(mtrr_var_range_t * range, int count);
	73	static void mtrr_set_var_ranges(const mtrr_var_range_t * range, int count);
	74	static void mtrr_get_fix_ranges(mtrr_fix_range_t * range);
	75	static void mtrr_set_fix_ranges(const mtrr_fix_range_t * range);
	76	static void mtrr_update_setup(void * param);
	77	static void mtrr_update_teardown(void * param);
	78	static void mtrr_update_action(void * param);
	79	static void var_range_encode(mtrr_var_range_t * range, addr64_t address,
	80	uint64_t length, uint32_t type, int valid);
	81	static int var_range_overlap(mtrr_var_range_t * range, addr64_t address,
	82	uint64_t length, uint32_t type);
	83
	84	#define CACHE_CONTROL_MTRR (NULL)
	85	#define CACHE_CONTROL_PAT ((void *)1)
	86
	87	/*
	88	* MTRR MSR bit fields.
	89	*/
	90	#define IA32_MTRR_DEF_TYPE_MT 0x000000ff
	91	#define IA32_MTRR_DEF_TYPE_FE 0x00000400
	92	#define IA32_MTRR_DEF_TYPE_E 0x00000800
	93
	94	#define IA32_MTRRCAP_VCNT 0x000000ff
	95	#define IA32_MTRRCAP_FIX 0x00000100
	96	#define IA32_MTRRCAP_WC 0x00000400
	97
	98	/* 0 < bits <= 64 */
99	#define PHYS_BITS_TO_MASK(bits) \
100	((((1ULL << (bits-1)) - 1) << 1) \| 1)
101
102	/*
103	* Default mask for 36 physical address bits, this can
104	* change depending on the cpu model.
105	*/
106	static uint64_t mtrr_phys_mask = PHYS_BITS_TO_MASK(36);
107
108	#define IA32_MTRR_PHYMASK_VALID 0x0000000000000800ULL
b0d623f7	109	#define IA32_MTRR_PHYSBASE_MASK (mtrr_phys_mask & ~0x0000000000000FFFULL)
91447636 A	110	#define IA32_MTRR_PHYSBASE_TYPE 0x00000000000000FFULL
	111
	112	/*
	113	* Variable-range mask to/from length conversions.
	114	*/
	115	#define MASK_TO_LEN(mask) \
	116	((~((mask) & IA32_MTRR_PHYSBASE_MASK) & mtrr_phys_mask) + 1)
	117
	118	#define LEN_TO_MASK(len) \
	119	(~((len) - 1) & IA32_MTRR_PHYSBASE_MASK)
	120
	121	#define LSB(x) ((x) & (~((x) - 1)))
	122
	123	/*
	124	* Fetch variable-range MTRR register pairs.
	125	*/
	126	static void
	127	mtrr_get_var_ranges(mtrr_var_range_t * range, int count)
	128	{
	129	int i;
	130
	131	for (i = 0; i < count; i++) {
	132	range[i].base = rdmsr64(MSR_IA32_MTRR_PHYSBASE(i));
	133	range[i].mask = rdmsr64(MSR_IA32_MTRR_PHYSMASK(i));
	134
	135	/* bump ref count for firmware configured ranges */
	136	if (range[i].mask & IA32_MTRR_PHYMASK_VALID)
	137	range[i].refcnt = 1;
	138	else
	139	range[i].refcnt = 0;
	140	}
	141	}
	142
	143	/*
	144	* Update variable-range MTRR register pairs.
	145	*/
	146	static void
	147	mtrr_set_var_ranges(const mtrr_var_range_t * range, int count)
	148	{
	149	int i;
	150
	151	for (i = 0; i < count; i++) {
	152	wrmsr64(MSR_IA32_MTRR_PHYSBASE(i), range[i].base);
	153	wrmsr64(MSR_IA32_MTRR_PHYSMASK(i), range[i].mask);
	154	}
	155	}
	156
	157	/*
	158	* Fetch all fixed-range MTRR's. Note MSR offsets are not consecutive.
	159	*/
	160	static void
	161	mtrr_get_fix_ranges(mtrr_fix_range_t * range)
	162	{
	163	int i;
	164
	165	/* assume 11 fix range registers */
	166	range[0].types = rdmsr64(MSR_IA32_MTRR_FIX64K_00000);
	167	range[1].types = rdmsr64(MSR_IA32_MTRR_FIX16K_80000);
	168	range[2].types = rdmsr64(MSR_IA32_MTRR_FIX16K_A0000);
	169	for (i = 0; i < 8; i++)
	170	range[3 + i].types = rdmsr64(MSR_IA32_MTRR_FIX4K_C0000 + i);
	171	}
	172
	173	/*
174	* Update all fixed-range MTRR's.
175	*/
176	static void
177	mtrr_set_fix_ranges(const struct mtrr_fix_range * range)
178	{
179	int i;
180
181	/* assume 11 fix range registers */
182	wrmsr64(MSR_IA32_MTRR_FIX64K_00000, range[0].types);
183	wrmsr64(MSR_IA32_MTRR_FIX16K_80000, range[1].types);
184	wrmsr64(MSR_IA32_MTRR_FIX16K_A0000, range[2].types);
185	for (i = 0; i < 8; i++)
186	wrmsr64(MSR_IA32_MTRR_FIX4K_C0000 + i, range[3 + i].types);
187	}
188
b0d623f7 A	189	static boolean_t
	190	mtrr_check_fix_ranges(const struct mtrr_fix_range * range)
	191	{
	192	int i;
	193	boolean_t match = TRUE;
	194
	195	DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);
	196
	197	/* assume 11 fix range registers */
	198	match = range[0].types == rdmsr64(MSR_IA32_MTRR_FIX64K_00000) &&
	199	range[1].types == rdmsr64(MSR_IA32_MTRR_FIX16K_80000) &&
	200	range[2].types == rdmsr64(MSR_IA32_MTRR_FIX16K_A0000);
	201	for (i = 0; match && i < 8; i++) {
	202	match = range[3 + i].types ==
	203	rdmsr64(MSR_IA32_MTRR_FIX4K_C0000 + i);
	204	}
	205
	206	return match;
	207	}
	208
	209	static boolean_t
	210	mtrr_check_var_ranges(mtrr_var_range_t * range, int count)
	211	{
	212	int i;
	213	boolean_t match = TRUE;
	214
	215	DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);
	216
	217	for (i = 0; match && i < count; i++) {
	218	match = range[i].base == rdmsr64(MSR_IA32_MTRR_PHYSBASE(i)) &&
	219	range[i].mask == rdmsr64(MSR_IA32_MTRR_PHYSMASK(i));
	220	}
	221
	222	return match;
	223	}
	224
91447636 A	225	#if MTRR_DEBUG
	226	static void
	227	mtrr_msr_dump(void)
	228	{
	229	int i;
	230	int count = rdmsr64(MSR_IA32_MTRRCAP) & IA32_MTRRCAP_VCNT;
	231
	232	DBG("VAR -- BASE -------------- MASK -------------- SIZE\n");
	233	for (i = 0; i < count; i++) {
	234	DBG(" %02x 0x%016llx 0x%016llx 0x%llx\n", i,
	235	rdmsr64(MSR_IA32_MTRR_PHYSBASE(i)),
	236	rdmsr64(MSR_IA32_MTRR_PHYSMASK(i)),
	237	MASK_TO_LEN(rdmsr64(MSR_IA32_MTRR_PHYSMASK(i))));
	238	}
	239	DBG("\n");
	240
	241	DBG("FIX64K_00000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX64K_00000));
	242	DBG("FIX16K_80000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX16K_80000));
	243	DBG("FIX16K_A0000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX16K_A0000));
	244	DBG(" FIX4K_C0000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_C0000));
	245	DBG(" FIX4K_C8000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_C8000));
	246	DBG(" FIX4K_D0000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_D0000));
	247	DBG(" FIX4K_D8000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_D8000));
	248	DBG(" FIX4K_E0000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_E0000));
	249	DBG(" FIX4K_E8000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_E8000));
	250	DBG(" FIX4K_F0000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_F0000));
	251	DBG(" FIX4K_F8000: 0x%016llx\n", rdmsr64(MSR_IA32_MTRR_FIX4K_F8000));
	252
	253	DBG("\nMTRRcap = 0x%llx MTRRdefType = 0x%llx\n",
	254	rdmsr64(MSR_IA32_MTRRCAP), rdmsr64(MSR_IA32_MTRR_DEF_TYPE));
	255	}
	256	#endif /* MTRR_DEBUG */
	257
	258	/*
	259	* Called by the boot processor (BP) early during boot to initialize MTRR
	260	* support. The MTRR state on the BP is saved, any additional processors
	261	* will have the same settings applied to ensure MTRR consistency.
	262	*/
	263	void
	264	mtrr_init(void)
	265	{
91447636 A	266	/* no reason to init more than once */
	267	if (mtrr_initialized == TRUE)
	268	return;
	269
	270	/* check for presence of MTRR feature on the processor */
	271	if ((cpuid_features() & CPUID_FEATURE_MTRR) == 0)
	272	return; /* no MTRR feature */
	273
91447636 A	274	/* use a lock to serialize MTRR changes */
	275	bzero((void *)&mtrr_state, sizeof(mtrr_state));
	276	simple_lock_init(&mtrr_lock, 0);
	277
	278	mtrr_state.MTRRcap = rdmsr64(MSR_IA32_MTRRCAP);
	279	mtrr_state.MTRRdefType = rdmsr64(MSR_IA32_MTRR_DEF_TYPE);
b0d623f7	280	mtrr_state.var_count = (unsigned int)(mtrr_state.MTRRcap & IA32_MTRRCAP_VCNT);
91447636 A	281
	282	/* allocate storage for variable ranges (can block?) */
	283	if (mtrr_state.var_count) {
	284	mtrr_state.var_range = (mtrr_var_range_t *)
	285	kalloc(sizeof(mtrr_var_range_t) *
	286	mtrr_state.var_count);
	287	if (mtrr_state.var_range == NULL)
	288	mtrr_state.var_count = 0;
	289	}
	290
	291	/* fetch the initial firmware configured variable ranges */
	292	if (mtrr_state.var_count)
	293	mtrr_get_var_ranges(mtrr_state.var_range,
	294	mtrr_state.var_count);
	295
	296	/* fetch the initial firmware configured fixed ranges */
	297	if (mtrr_state.MTRRcap & IA32_MTRRCAP_FIX)
	298	mtrr_get_fix_ranges(mtrr_state.fix_range);
	299
	300	mtrr_initialized = TRUE;
	301
	302	#if MTRR_DEBUG
	303	mtrr_msr_dump(); /* dump firmware settings */
	304	#endif
b0d623f7	305
91447636 A	306	}
	307
	308	/*
	309	* Performs the Intel recommended procedure for changing the MTRR
	310	* in a MP system. Leverage rendezvous mechanism for the required
	311	* barrier synchronization among all processors. This function is
	312	* called from the rendezvous IPI handler, and mtrr_update_cpu().
	313	*/
	314	static void
	315	mtrr_update_action(void * cache_control_type)
	316	{
b0d623f7 A	317	uintptr_t cr0, cr4;
b0d623f7 A	318	uintptr_t tmp;
91447636 A	319
	320	cr0 = get_cr0();
	321	cr4 = get_cr4();
	322
	323	/* enter no-fill cache mode */
	324	tmp = cr0 \| CR0_CD;
	325	tmp &= ~CR0_NW;
	326	set_cr0(tmp);
	327
	328	/* flush caches */
	329	wbinvd();
	330
	331	/* clear the PGE flag in CR4 */
	332	if (cr4 & CR4_PGE)
	333	set_cr4(cr4 & ~CR4_PGE);
	334
	335	/* flush TLBs */
6d2010ae	336	flush_tlb_raw();
91447636 A	337
	338	if (CACHE_CONTROL_PAT == cache_control_type) {
	339	/* Change PA6 attribute field to WC */
	340	uint64_t pat = rdmsr64(MSR_IA32_CR_PAT);
	341	DBG("CPU%d PAT: was 0x%016llx\n", get_cpu_number(), pat);
	342	pat &= ~(0x0FULL << 48);
	343	pat \|= (0x01ULL << 48);
	344	wrmsr64(MSR_IA32_CR_PAT, pat);
	345	DBG("CPU%d PAT: is 0x%016llx\n",
	346	get_cpu_number(), rdmsr64(MSR_IA32_CR_PAT));
	347	}
	348	else {
	349	/* disable all MTRR ranges */
	350	wrmsr64(MSR_IA32_MTRR_DEF_TYPE,
	351	mtrr_state.MTRRdefType & ~IA32_MTRR_DEF_TYPE_E);
	352
	353	/* apply MTRR settings */
	354	if (mtrr_state.var_count)
	355	mtrr_set_var_ranges(mtrr_state.var_range,
	356	mtrr_state.var_count);
	357
	358	if (mtrr_state.MTRRcap & IA32_MTRRCAP_FIX)
	359	mtrr_set_fix_ranges(mtrr_state.fix_range);
	360
	361	/* enable all MTRR range registers (what if E was not set?) */
	362	wrmsr64(MSR_IA32_MTRR_DEF_TYPE,
	363	mtrr_state.MTRRdefType \| IA32_MTRR_DEF_TYPE_E);
	364	}
	365
	366	/* flush all caches and TLBs a second time */
	367	wbinvd();
6d2010ae	368	flush_tlb_raw();
91447636 A	369
	370	/* restore normal cache mode */
	371	set_cr0(cr0);
	372
	373	/* restore PGE flag */
	374	if (cr4 & CR4_PGE)
	375	set_cr4(cr4);
	376
	377	DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);
	378	}
	379
	380	static void
	381	mtrr_update_setup(__unused void * param_not_used)
	382	{
	383	/* disable interrupts before the first barrier */
	384	current_cpu_datap()->cpu_iflag = ml_set_interrupts_enabled(FALSE);
	385	DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);
	386	}
	387
	388	static void
	389	mtrr_update_teardown(__unused void * param_not_used)
	390	{
	391	/* restore interrupt flag following MTRR changes */
	392	ml_set_interrupts_enabled(current_cpu_datap()->cpu_iflag);
	393	DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);
	394	}
	395
	396	/*
	397	* Update MTRR settings on all processors.
	398	*/
	399	kern_return_t
	400	mtrr_update_all_cpus(void)
	401	{
	402	if (mtrr_initialized == FALSE)
	403	return KERN_NOT_SUPPORTED;
	404
	405	MTRR_LOCK();
	406	mp_rendezvous(mtrr_update_setup,
	407	mtrr_update_action,
	408	mtrr_update_teardown, NULL);
	409	MTRR_UNLOCK();
	410
	411	return KERN_SUCCESS;
	412	}
	413
	414	/*
b0d623f7 A	415	* Verify that a processor has been set with the BSP's MTRR settings. Called
b0d623f7 A	416	* during slave processor initialization to check and set MTRR settings
91447636 A	417	* discovered on the boot processor by mtrr_init().
	418	*/
	419	kern_return_t
	420	mtrr_update_cpu(void)
	421	{
b0d623f7 A	422	boolean_t match = TRUE;
b0d623f7 A	423
91447636 A	424	if (mtrr_initialized == FALSE)
	425	return KERN_NOT_SUPPORTED;
	426
b0d623f7 A	427	DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);
b0d623f7 A	428
91447636	429	MTRR_LOCK();
b0d623f7 A	430
	431	/* Check MSR_IA32_MTRR_DEF_TYPE MSR */
	432	match = mtrr_state.MTRRdefType == rdmsr64(MSR_IA32_MTRR_DEF_TYPE);
	433
	434	/* Check MSR_IA32_MTRRCAP MSR */
	435	if (match) {
	436	match = mtrr_state.MTRRcap == rdmsr64(MSR_IA32_MTRRCAP);
	437	}
	438
	439	/* Check variable ranges */
	440	if (match && mtrr_state.var_count) {
	441	match = mtrr_check_var_ranges(mtrr_state.var_range,
	442	mtrr_state.var_count);
	443	}
	444
	445	/* Check fixed ranges */
	446	if (match && (mtrr_state.MTRRcap & IA32_MTRRCAP_FIX)) {
	447	match = mtrr_check_fix_ranges(mtrr_state.fix_range);
	448	}
	449
	450	#if MTRR_DEBUG
	451	if (!match)
	452	mtrr_msr_dump();
	453	#endif
	454	if (!match) {
	455	DBG("mtrr_update_cpu() setting MTRR for cpu %d\n",
	456	get_cpu_number());
	457	mtrr_update_action(NULL);
	458	}
	459	#if MTRR_DEBUG
	460	if (!match)
	461	mtrr_msr_dump();
	462	#endif
	463
91447636 A	464	MTRR_UNLOCK();
	465
	466	return KERN_SUCCESS;
	467	}
	468
	469	/*
	470	* Add a MTRR range to associate the physical memory range specified
	471	* with a given memory caching type.
	472	*/
	473	kern_return_t
	474	mtrr_range_add(addr64_t address, uint64_t length, uint32_t type)
	475	{
	476	mtrr_var_range_t * vr;
	477	mtrr_var_range_t * free_range;
	478	kern_return_t ret = KERN_NO_SPACE;
	479	int overlap;
	480	unsigned int i;
	481
	482	DBG("mtrr_range_add base = 0x%llx, size = 0x%llx, type = %d\n",
	483	address, length, type);
	484
	485	if (mtrr_initialized == FALSE) {
	486	return KERN_NOT_SUPPORTED;
	487	}
	488
	489	/* check memory type (GPF exception for undefined types) */
	490	if ((type != MTRR_TYPE_UNCACHEABLE) &&
	491	(type != MTRR_TYPE_WRITECOMBINE) &&
	492	(type != MTRR_TYPE_WRITETHROUGH) &&
	493	(type != MTRR_TYPE_WRITEPROTECT) &&
	494	(type != MTRR_TYPE_WRITEBACK)) {
	495	return KERN_INVALID_ARGUMENT;
	496	}
	497
	498	/* check WC support if requested */
	499	if ((type == MTRR_TYPE_WRITECOMBINE) &&
	500	(mtrr_state.MTRRcap & IA32_MTRRCAP_WC) == 0) {
	501	return KERN_NOT_SUPPORTED;
	502	}
	503
	504	/* leave the fix range area below 1MB alone */
	505	if (address < 0x100000 \|\| mtrr_state.var_count == 0) {
	506	return KERN_NOT_SUPPORTED;
	507	}
	508
	509	/*
	510	* Length must be a power of 2 given by 2^n, where n >= 12.
	511	* Base address alignment must be larger than or equal to length.
	512	*/
	513	if ((length < 0x1000) \|\|
	514	(LSB(length) != length) \|\|
	515	(address && (length > LSB(address)))) {
	516	return KERN_INVALID_ARGUMENT;
	517	}
	518
	519	MTRR_LOCK();
	520
	521	/*
	522	* Check for overlap and locate a free range.
	523	*/
	524	for (i = 0, free_range = NULL; i < mtrr_state.var_count; i++)
	525	{
	526	vr = &mtrr_state.var_range[i];
	527
528	if (vr->refcnt == 0) {
529	/* free range candidate if no overlaps are found */
530	free_range = vr;
531	continue;
532	}
533
534	overlap = var_range_overlap(vr, address, length, type);
535	if (overlap > 0) {
536	/*
537	* identical overlap permitted, increment ref count.
538	* no hardware update required.
539	*/
540	free_range = vr;
541	break;
542	}
543	if (overlap < 0) {
544	/* unsupported overlapping of memory types */
545	free_range = NULL;
546	break;
547	}
548	}
549
550	if (free_range) {
551	if (free_range->refcnt++ == 0) {
552	var_range_encode(free_range, address, length, type, 1);
553	mp_rendezvous(mtrr_update_setup,
554	mtrr_update_action,
555	mtrr_update_teardown, NULL);
556	}
557	ret = KERN_SUCCESS;
558	}
559
560	#if MTRR_DEBUG
561	mtrr_msr_dump();
562	#endif
563
564	MTRR_UNLOCK();
565
566	return ret;
567	}
568
569	/*
570	* Remove a previously added MTRR range. The same arguments used for adding
571	* the memory range must be supplied again.
572	*/
573	kern_return_t
574	mtrr_range_remove(addr64_t address, uint64_t length, uint32_t type)
575	{
576	mtrr_var_range_t * vr;
577	int result = KERN_FAILURE;
578	int cpu_update = 0;
579	unsigned int i;
580
581	DBG("mtrr_range_remove base = 0x%llx, size = 0x%llx, type = %d\n",
582	address, length, type);
583
584	if (mtrr_initialized == FALSE) {
585	return KERN_NOT_SUPPORTED;
586	}
587
588	MTRR_LOCK();
589
590	for (i = 0; i < mtrr_state.var_count; i++) {
591	vr = &mtrr_state.var_range[i];
592
593	if (vr->refcnt &&
594	var_range_overlap(vr, address, length, type) > 0) {
595	/* found specified variable range */
596	if (--mtrr_state.var_range[i].refcnt == 0) {
597	var_range_encode(vr, address, length, type, 0);
598	cpu_update = 1;
599	}
600	result = KERN_SUCCESS;
601	break;
602	}
603	}
604
605	if (cpu_update) {
606	mp_rendezvous(mtrr_update_setup,
607	mtrr_update_action,
608	mtrr_update_teardown, NULL);
609	result = KERN_SUCCESS;
610	}
611
612	#if MTRR_DEBUG
613	mtrr_msr_dump();
614	#endif
615
616	MTRR_UNLOCK();
617
618	return result;
619	}
620
621	/*
622	* Variable range helper routines
623	*/
624	static void
625	var_range_encode(mtrr_var_range_t * range, addr64_t address,
626	uint64_t length, uint32_t type, int valid)
627	{
628	range->base = (address & IA32_MTRR_PHYSBASE_MASK) \|
b0d623f7	629	(type & (uint32_t)IA32_MTRR_PHYSBASE_TYPE);
91447636 A	630
	631	range->mask = LEN_TO_MASK(length) \|
	632	(valid ? IA32_MTRR_PHYMASK_VALID : 0);
	633	}
	634
	635	static int
	636	var_range_overlap(mtrr_var_range_t * range, addr64_t address,
	637	uint64_t length, uint32_t type)
	638	{
	639	uint64_t v_address, v_length;
	640	uint32_t v_type;
	641	int result = 0; /* no overlap, or overlap ok */
	642
	643	v_address = range->base & IA32_MTRR_PHYSBASE_MASK;
b0d623f7	644	v_type = (uint32_t)(range->base & IA32_MTRR_PHYSBASE_TYPE);
91447636 A	645	v_length = MASK_TO_LEN(range->mask);
	646
	647	/* detect range overlap */
	648	if ((v_address >= address && v_address < (address + length)) \|\|
	649	(address >= v_address && address < (v_address + v_length))) {
	650
	651	if (v_address == address && v_length == length && v_type == type)
	652	result = 1; /* identical overlap ok */
	653	else if ( v_type == MTRR_TYPE_UNCACHEABLE &&
	654	type == MTRR_TYPE_UNCACHEABLE ) {
	655	/* UC ranges can overlap */
	656	}
	657	else if ((v_type == MTRR_TYPE_UNCACHEABLE &&
	658	type == MTRR_TYPE_WRITEBACK) \|\|
	659	(v_type == MTRR_TYPE_WRITEBACK &&
	660	type == MTRR_TYPE_UNCACHEABLE)) {
	661	/* UC/WB can overlap - effective type becomes UC */
	662	}
	663	else {
	664	/* anything else may cause undefined behavior */
	665	result = -1;
	666	}
	667	}
	668
	669	return result;
	670	}
	671
	672	/*
	673	* Initialize PAT (Page Attribute Table)
	674	*/
	675	void
	676	pat_init(void)
	677	{
b0d623f7 A	678	boolean_t istate;
	679	uint64_t pat;
	680
	681	if (!(cpuid_features() & CPUID_FEATURE_PAT))
	682	return;
	683
	684	istate = ml_set_interrupts_enabled(FALSE);
	685
	686	pat = rdmsr64(MSR_IA32_CR_PAT);
	687	DBG("CPU%d PAT: was 0x%016llx\n", get_cpu_number(), pat);
	688
	689	/* Change PA6 attribute field to WC if required */
	690	if ((pat & ~(0x0FULL << 48)) != (0x01ULL << 48)) {
91447636	691	mtrr_update_action(CACHE_CONTROL_PAT);
91447636	692	}
b0d623f7	693	ml_set_interrupts_enabled(istate);
91447636	694	}