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55e303ae 1/*
91447636 2 * Copyright (c) 2003-2004 Apple Computer, Inc. All rights reserved.
55e303ae 3 *
6601e61a
A		 4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
8f6c56a5
A		 14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
6601e61a
A		 16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
55e303ae 21 */
91447636
A		 22#include <mach/mach_types.h>
23#include <mach/mach_host.h>
24
25#include <kern/host.h>
26#include <kern/processor.h>
55e303ae 27
0c530ab8
A		 28#include <chud/chud_xnu.h>
29#include <chud/ppc/chud_spr.h>
30#include <chud/ppc/chud_cpu_asm.h>
55e303ae
A		 31#include <ppc/machine_routines.h>
32#include <ppc/exception.h>
91447636 33#include <ppc/hw_perfmon.h>
55e303ae
A		 34#include <ppc/Diagnostics.h>
35
91447636
A		 36// the macros in proc_reg.h fail with "expression must be absolute"
37
38#undef mtsprg
39#undef mfsprg
40#define mtsprg(n, reg) __asm__ volatile("mtsprg " # n ", %0" : : "r" (reg))
41#define mfsprg(reg, n) __asm__ volatile("mfsprg %0, " # n : "=r" (reg))
42
43#undef mtspr
44#undef mfspr
45#define mtspr(spr, reg) __asm__ volatile ("mtspr %0, %1" : : "n" (spr), "r" (reg))
46#define mfspr(reg, spr) __asm__ volatile("mfspr %0, %1" : "=r" (reg) : "n" (spr));
47
48#undef mtsr
49#undef mfsr
50#define mtsr(sr, reg) __asm__ volatile("sync" "@" "mtsr sr%0, %1 " "@" "isync" : : "i" (sr), "r" (reg));
51#define mfsr(reg, sr) __asm__ volatile("mfsr %0, sr%1" : "=r" (reg) : "i" (sr));
52
91447636
A		 53#pragma mark **** cpu enable/disable ****
54
55extern kern_return_t processor_start(processor_t processor); // osfmk/kern/processor.c
56extern kern_return_t processor_exit(processor_t processor); // osfmk/kern/processor.c
57
55e303ae
A		 58__private_extern__
59kern_return_t chudxnu_enable_cpu(int cpu, boolean_t enable)
60{
91447636 61 chudxnu_unbind_thread(current_thread());
55e303ae
A		 62
63 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
64 return KERN_FAILURE;
65 }
66
91447636
A		 67 if((PerProcTable[cpu].ppe_vaddr != (struct per_proc_info *)NULL)
68 && cpu != master_cpu) {
69 processor_t processor = cpu_to_processor(cpu);
70
55e303ae 71 if(enable) {
91447636 72 return processor_start(processor);
55e303ae 73 } else {
91447636 74 return processor_exit(processor);
55e303ae
A		 75 }
76 }
77 return KERN_FAILURE;
78}
79
91447636
A		 80#pragma mark **** nap ****
81
55e303ae
A		 82__private_extern__
83kern_return_t chudxnu_enable_cpu_nap(int cpu, boolean_t enable)
84{
85 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
86 return KERN_FAILURE;
87 }
88
91447636 89 if(PerProcTable[cpu].ppe_vaddr != (struct per_proc_info *)NULL) {
55e303ae
A		 90 ml_enable_nap(cpu, enable);
91 return KERN_SUCCESS;
92 }
93
94 return KERN_FAILURE;
95}
96
97__private_extern__
98boolean_t chudxnu_cpu_nap_enabled(int cpu)
99{
100 boolean_t prev;
101
102 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
103 cpu = 0;
104 }
105
106 prev = ml_enable_nap(cpu, TRUE);
107 ml_enable_nap(cpu, prev);
108
109 return prev;
110}
111
91447636
A		 112#pragma mark **** shadowed spr ****
113
55e303ae
A		 114__private_extern__
115kern_return_t chudxnu_set_shadowed_spr(int cpu, int spr, uint32_t val)
116{
91447636 117 cpu_subtype_t target_cpu_subtype;
55e303ae
A		 118 uint32_t available;
119 kern_return_t retval = KERN_FAILURE;
91447636
A		 120 struct per_proc_info *per_proc;
121 boolean_t didBind = FALSE;
55e303ae 122
91447636 123 if(cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
55e303ae
A		 124 return KERN_FAILURE;
125 }
126
91447636
A		 127 if(cpu<0) { // cpu<0 means don't bind (current cpu)
128 cpu = chudxnu_cpu_number();
129 didBind = FALSE;
130 } else {
131 chudxnu_bind_thread(current_thread(), cpu);
132 didBind = TRUE;
133 }
55e303ae 134
91447636
A		 135 per_proc = PerProcTable[cpu].ppe_vaddr;
136 available = per_proc->pf.Available;
137 target_cpu_subtype = per_proc->cpu_subtype;
55e303ae
A		 138
139 if(spr==chud_750_l2cr) {
91447636 140 switch(target_cpu_subtype) {
55e303ae
A		 141 case CPU_SUBTYPE_POWERPC_750:
142 case CPU_SUBTYPE_POWERPC_7400:
143 case CPU_SUBTYPE_POWERPC_7450:
144 if(available & pfL2) {
145// int enable = (val & 0x80000000) ? TRUE : FALSE;
146// if(enable) {
91447636 147// per_proc->pf.l2cr = val;
55e303ae 148// } else {
91447636 149// per_proc->pf.l2cr = 0;
55e303ae 150// }
91447636 151 per_proc->pf.l2cr = val;
55e303ae 152 cacheInit();
91447636 153 // mtspr(l2cr, per_proc->pf.l2cr); // XXXXXXX why is this necessary? XXXXXXX
55e303ae
A		 154 retval = KERN_SUCCESS;
155 } else {
156 retval = KERN_FAILURE;
157 }
158 break;
159 default:
160 retval = KERN_INVALID_ARGUMENT;
161 break;
162 }
163 }
164 else if(spr==chud_7450_l3cr) {
91447636 165 switch(target_cpu_subtype) {
55e303ae
A		 166 case CPU_SUBTYPE_POWERPC_7450:
167 if(available & pfL3) {
168 int enable = (val & 0x80000000) ? TRUE : FALSE;
169 if(enable) {
91447636 170 per_proc->pf.l3cr = val;
55e303ae 171 } else {
91447636 172 per_proc->pf.l3cr = 0;
55e303ae
A		 173 }
174 cacheInit();
175 retval = KERN_SUCCESS;
176 } else {
177 retval = KERN_FAILURE;
178 }
179 break;
180 default:
181 retval = KERN_INVALID_ARGUMENT;
182 break;
183 }
184 }
185 else if(spr==chud_750_hid0) {
91447636 186 switch(target_cpu_subtype) {
55e303ae
A		 187 case CPU_SUBTYPE_POWERPC_750:
188 cacheInit();
189 cacheDisable(); /* disable caches */
91447636
A		 190 mtspr(chud_750_hid0, val);
191 per_proc->pf.pfHID0 = val;
55e303ae
A		 192 cacheInit(); /* reenable caches */
193 retval = KERN_SUCCESS;
194 break;
195 case CPU_SUBTYPE_POWERPC_7400:
196 case CPU_SUBTYPE_POWERPC_7450:
91447636
A		 197 mtspr(chud_750_hid0, val);
198 per_proc->pf.pfHID0 = val;
55e303ae
A		 199 retval = KERN_SUCCESS;
200 break;
201 default:
202 retval = KERN_INVALID_ARGUMENT;
203 break;
204 }
205 }
206 else if(spr==chud_750_hid1) {
91447636 207 switch(target_cpu_subtype) {
55e303ae
A		 208 case CPU_SUBTYPE_POWERPC_750:
209 case CPU_SUBTYPE_POWERPC_7400:
210 case CPU_SUBTYPE_POWERPC_7450:
91447636
A		 211 mtspr(chud_750_hid1, val);
212 per_proc->pf.pfHID1 = val;
55e303ae
A		 213 retval = KERN_SUCCESS;
214 break;
215 default:
216 retval = KERN_INVALID_ARGUMENT;
217 break;
218 }
219 }
91447636
A		 220 else if(spr==chud_750fx_hid2 && target_cpu_subtype==CPU_SUBTYPE_POWERPC_750) {
221 mtspr(chud_750fx_hid2, val);
222 per_proc->pf.pfHID2 = val;
55e303ae
A		 223 retval = KERN_SUCCESS;
224 }
91447636
A		 225 else if(spr==chud_7400_msscr0 && (target_cpu_subtype==CPU_SUBTYPE_POWERPC_7400 || target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450)) {
226 mtspr(chud_7400_msscr0, val);
227 per_proc->pf.pfMSSCR0 = val;
55e303ae
A		 228 retval = KERN_SUCCESS;
229 }
91447636
A		 230 else if(spr==chud_7400_msscr1 && (target_cpu_subtype==CPU_SUBTYPE_POWERPC_7400 || target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450)) { // called msssr0 on 7450
231 mtspr(chud_7400_msscr1, val);
232 per_proc->pf.pfMSSCR1 = val;
55e303ae
A		 233 retval = KERN_SUCCESS;
234 }
91447636
A		 235 else if(spr==chud_7450_ldstcr && target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450) {
236 mtspr(chud_7450_ldstcr, val);
237 per_proc->pf.pfLDSTCR = val;
55e303ae
A		 238 retval = KERN_SUCCESS;
239 }
91447636
A		 240 else if(spr==chud_7450_ictrl && target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450) {
241 mtspr(chud_7450_ictrl, val);
242 per_proc->pf.pfICTRL = val;
55e303ae
A		 243 retval = KERN_SUCCESS;
244 } else {
245 retval = KERN_INVALID_ARGUMENT;
246 }
247
91447636
A		 248 if(didBind) {
249 chudxnu_unbind_thread(current_thread());
250 }
251
55e303ae
A		 252 return retval;
253}
254
255__private_extern__
256kern_return_t chudxnu_set_shadowed_spr64(int cpu, int spr, uint64_t val)
257{
91447636 258 cpu_subtype_t target_cpu_subtype;
55e303ae 259 kern_return_t retval = KERN_FAILURE;
91447636
A		 260 struct per_proc_info *per_proc;
261 boolean_t didBind = FALSE;
55e303ae 262
91447636 263 if(cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
55e303ae
A		 264 return KERN_FAILURE;
265 }
266
91447636
A		 267 if(cpu<0) { // cpu<0 means don't bind (current cpu)
268 cpu = chudxnu_cpu_number();
269 didBind = FALSE;
270 } else {
271 chudxnu_bind_thread(current_thread(), cpu);
272 didBind = TRUE;
273 }
55e303ae 274
91447636
A		 275 per_proc = PerProcTable[cpu].ppe_vaddr;
276 target_cpu_subtype = per_proc->cpu_subtype;
55e303ae
A		 277
278 if(spr==chud_970_hid0) {
91447636 279 switch(target_cpu_subtype) {
55e303ae 280 case CPU_SUBTYPE_POWERPC_970:
91447636
A		 281 mtspr64(chud_970_hid0, &val);
282 per_proc->pf.pfHID0 = val;
55e303ae
A		 283 retval = KERN_SUCCESS;
284 break;
285 default:
286 retval = KERN_INVALID_ARGUMENT;
287 break;
288 }
289 }
290 else if(spr==chud_970_hid1) {
91447636 291 switch(target_cpu_subtype) {
55e303ae 292 case CPU_SUBTYPE_POWERPC_970:
91447636
A		 293 mtspr64(chud_970_hid1, &val);
294 per_proc->pf.pfHID1 = val;
55e303ae
A		 295 retval = KERN_SUCCESS;
296 break;
297 default:
298 retval = KERN_INVALID_ARGUMENT;
299 break;
300 }
301 }
302 else if(spr==chud_970_hid4) {
91447636 303 switch(target_cpu_subtype) {
55e303ae 304 case CPU_SUBTYPE_POWERPC_970:
91447636
A		 305 mtspr64(chud_970_hid4, &val);
306 per_proc->pf.pfHID4 = val;
55e303ae
A		 307 retval = KERN_SUCCESS;
308 break;
309 default:
310 retval = KERN_INVALID_ARGUMENT;
311 break;
312 }
313 }
314 else if(spr==chud_970_hid5) {
91447636 315 switch(target_cpu_subtype) {
55e303ae 316 case CPU_SUBTYPE_POWERPC_970:
91447636
A		 317 mtspr64(chud_970_hid5, &val);
318 per_proc->pf.pfHID5 = val;
55e303ae
A		 319 retval = KERN_SUCCESS;
320 break;
321 default:
322 retval = KERN_INVALID_ARGUMENT;
323 break;
324 }
325 } else {
326 retval = KERN_INVALID_ARGUMENT;
327 }
328
91447636
A		 329 if(didBind) {
330 chudxnu_unbind_thread(current_thread());
331 }
55e303ae
A		 332
333 return retval;
334}
335
336__private_extern__
337uint32_t chudxnu_get_orig_cpu_l2cr(int cpu)
338{
339 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
340 cpu = 0;
341 }
91447636 342 return PerProcTable[cpu].ppe_vaddr->pf.l2crOriginal;
55e303ae
A		 343}
344
345__private_extern__
346uint32_t chudxnu_get_orig_cpu_l3cr(int cpu)
347{
348 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
349 cpu = 0;
350 }
91447636
A		 351 return PerProcTable[cpu].ppe_vaddr->pf.l3crOriginal;
352}
353
354#pragma mark **** spr ****
355
356__private_extern__
357kern_return_t chudxnu_read_spr(int cpu, int spr, uint32_t *val_p)
358{
359 kern_return_t retval = KERN_SUCCESS;
360 boolean_t oldlevel;
361 uint32_t val = 0xFFFFFFFF;
362
363 /* bind to requested CPU */
364 if(cpu>=0) { // cpu<0 means don't bind
365 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
366 return KERN_INVALID_ARGUMENT;
367 }
368 }
369
370 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
371
372 do {
373 /* PPC SPRs - 32-bit and 64-bit implementations */
374 if(spr==chud_ppc_srr0) { mfspr(val, chud_ppc_srr0); break; }
375 if(spr==chud_ppc_srr1) { mfspr(val, chud_ppc_srr1); break; }
376 if(spr==chud_ppc_dsisr) { mfspr(val, chud_ppc_dsisr); break; }
377 if(spr==chud_ppc_dar) { mfspr(val, chud_ppc_dar); break; }
378 if(spr==chud_ppc_dec) { mfspr(val, chud_ppc_dec); break; }
379 if(spr==chud_ppc_sdr1) { mfspr(val, chud_ppc_sdr1); break; }
380 if(spr==chud_ppc_sprg0) { mfspr(val, chud_ppc_sprg0); break; }
381 if(spr==chud_ppc_sprg1) { mfspr(val, chud_ppc_sprg1); break; }
382 if(spr==chud_ppc_sprg2) { mfspr(val, chud_ppc_sprg2); break; }
383 if(spr==chud_ppc_sprg3) { mfspr(val, chud_ppc_sprg3); break; }
384 if(spr==chud_ppc_ear) { mfspr(val, chud_ppc_ear); break; }
385 if(spr==chud_ppc_tbl) { mfspr(val, 268); break; } /* timebase consists of read registers and write registers */
386 if(spr==chud_ppc_tbu) { mfspr(val, 269); break; }
387 if(spr==chud_ppc_pvr) { mfspr(val, chud_ppc_pvr); break; }
388 if(spr==chud_ppc_ibat0u) { mfspr(val, chud_ppc_ibat0u); break; }
389 if(spr==chud_ppc_ibat0l) { mfspr(val, chud_ppc_ibat0l); break; }
390 if(spr==chud_ppc_ibat1u) { mfspr(val, chud_ppc_ibat1u); break; }
391 if(spr==chud_ppc_ibat1l) { mfspr(val, chud_ppc_ibat1l); break; }
392 if(spr==chud_ppc_ibat2u) { mfspr(val, chud_ppc_ibat2u); break; }
393 if(spr==chud_ppc_ibat2l) { mfspr(val, chud_ppc_ibat2l); break; }
394 if(spr==chud_ppc_ibat3u) { mfspr(val, chud_ppc_ibat3u); break; }
395 if(spr==chud_ppc_ibat3l) { mfspr(val, chud_ppc_ibat3l); break; }
396 if(spr==chud_ppc_dbat0u) { mfspr(val, chud_ppc_dbat0u); break; }
397 if(spr==chud_ppc_dbat0l) { mfspr(val, chud_ppc_dbat0l); break; }
398 if(spr==chud_ppc_dbat1u) { mfspr(val, chud_ppc_dbat1u); break; }
399 if(spr==chud_ppc_dbat1l) { mfspr(val, chud_ppc_dbat1l); break; }
400 if(spr==chud_ppc_dbat2u) { mfspr(val, chud_ppc_dbat2u); break; }
401 if(spr==chud_ppc_dbat2l) { mfspr(val, chud_ppc_dbat2l); break; }
402 if(spr==chud_ppc_dbat3u) { mfspr(val, chud_ppc_dbat3u); break; }
403 if(spr==chud_ppc_dbat3l) { mfspr(val, chud_ppc_dbat3l); break; }
404 if(spr==chud_ppc_dabr) { mfspr(val, chud_ppc_dabr); break; }
405 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
406 struct ppc_thread_state64 state;
407 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
408 kern_return_t kr;
409 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
410 if(KERN_SUCCESS==kr) {
411 val = state.srr1;
412 } else {
413 retval = KERN_FAILURE;
414 }
415 break;
416 }
417
418 /* PPC SPRs - 32-bit implementations */
419 if(spr==chud_ppc32_sr0) { mfsr(val, 0); break; }
420 if(spr==chud_ppc32_sr1) { mfsr(val, 1); break; }
421 if(spr==chud_ppc32_sr2) { mfsr(val, 2); break; }
422 if(spr==chud_ppc32_sr3) { mfsr(val, 3); break; }
423 if(spr==chud_ppc32_sr4) { mfsr(val, 4); break; }
424 if(spr==chud_ppc32_sr5) { mfsr(val, 5); break; }
425 if(spr==chud_ppc32_sr6) { mfsr(val, 6); break; }
426 if(spr==chud_ppc32_sr7) { mfsr(val, 7); break; }
427 if(spr==chud_ppc32_sr8) { mfsr(val, 8); break; }
428 if(spr==chud_ppc32_sr9) { mfsr(val, 9); break; }
429 if(spr==chud_ppc32_sr10) { mfsr(val, 10); break; }
430 if(spr==chud_ppc32_sr11) { mfsr(val, 11); break; }
431 if(spr==chud_ppc32_sr12) { mfsr(val, 12); break; }
432 if(spr==chud_ppc32_sr13) { mfsr(val, 13); break; }
433 if(spr==chud_ppc32_sr14) { mfsr(val, 14); break; }
434 if(spr==chud_ppc32_sr15) { mfsr(val, 15); break; }
435
436 /* PPC SPRs - 64-bit implementations */
437 if(spr==chud_ppc64_ctrl) { mfspr(val, chud_ppc64_ctrl); break; }
438
439 /* Implementation Specific SPRs */
440 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_750) {
441 if(spr==chud_750_mmcr0) { mfspr(val, chud_750_mmcr0); break; }
442 if(spr==chud_750_pmc1) { mfspr(val, chud_750_pmc1); break; }
443 if(spr==chud_750_pmc2) { mfspr(val, chud_750_pmc2); break; }
444 if(spr==chud_750_sia) { mfspr(val, chud_750_sia); break; }
445 if(spr==chud_750_mmcr1) { mfspr(val, chud_750_mmcr1); break; }
446 if(spr==chud_750_pmc3) { mfspr(val, chud_750_pmc3); break; }
447 if(spr==chud_750_pmc4) { mfspr(val, chud_750_pmc4); break; }
448 if(spr==chud_750_hid0) { mfspr(val, chud_750_hid0); break; }
449 if(spr==chud_750_hid1) { mfspr(val, chud_750_hid1); break; }
450 if(spr==chud_750_iabr) { mfspr(val, chud_750_iabr); break; }
451 if(spr==chud_750_ictc) { mfspr(val, chud_750_ictc); break; }
452 if(spr==chud_750_thrm1) { mfspr(val, chud_750_thrm1); break; }
453 if(spr==chud_750_thrm2) { mfspr(val, chud_750_thrm2); break; }
454 if(spr==chud_750_thrm3) { mfspr(val, chud_750_thrm3); break; }
455 if(spr==chud_750_l2cr) { mfspr(val, chud_750_l2cr); break; }
456
457 // 750FX only
458 if(spr==chud_750fx_ibat4u) { mfspr(val, chud_750fx_ibat4u); break; }
459 if(spr==chud_750fx_ibat4l) { mfspr(val, chud_750fx_ibat4l); break; }
460 if(spr==chud_750fx_ibat5u) { mfspr(val, chud_750fx_ibat5u); break; }
461 if(spr==chud_750fx_ibat5l) { mfspr(val, chud_750fx_ibat5l); break; }
462 if(spr==chud_750fx_ibat6u) { mfspr(val, chud_750fx_ibat6u); break; }
463 if(spr==chud_750fx_ibat6l) { mfspr(val, chud_750fx_ibat6l); break; }
464 if(spr==chud_750fx_ibat7u) { mfspr(val, chud_750fx_ibat7u); break; }
465 if(spr==chud_750fx_ibat7l) { mfspr(val, chud_750fx_ibat7l); break; }
466 if(spr==chud_750fx_dbat4u) { mfspr(val, chud_750fx_dbat4u); break; }
467 if(spr==chud_750fx_dbat4l) { mfspr(val, chud_750fx_dbat4l); break; }
468 if(spr==chud_750fx_dbat5u) { mfspr(val, chud_750fx_dbat5u); break; }
469 if(spr==chud_750fx_dbat5l) { mfspr(val, chud_750fx_dbat5l); break; }
470 if(spr==chud_750fx_dbat6u) { mfspr(val, chud_750fx_dbat6u); break; }
471 if(spr==chud_750fx_dbat6l) { mfspr(val, chud_750fx_dbat6l); break; }
472 if(spr==chud_750fx_dbat7u) { mfspr(val, chud_750fx_dbat7u); break; }
473 if(spr==chud_750fx_dbat7l) { mfspr(val, chud_750fx_dbat7l); break; }
474
475 // 750FX >= DDR2.x only
476 if(spr==chud_750fx_hid2) { mfspr(val, chud_750fx_hid2); break; }
477 }
478
479 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7400) {
480 if(spr==chud_7400_mmcr2) { mfspr(val, chud_7400_mmcr2); break; }
481 if(spr==chud_7400_bamr) { mfspr(val, chud_7400_bamr); break; }
482 if(spr==chud_7400_mmcr0) { mfspr(val, chud_7400_mmcr0); break; }
483 if(spr==chud_7400_pmc1) { mfspr(val, chud_7400_pmc1); break; }
484 if(spr==chud_7400_pmc2) { mfspr(val, chud_7400_pmc2); break; }
485 if(spr==chud_7400_siar) { mfspr(val, chud_7400_siar); break; }
486 if(spr==chud_7400_mmcr1) { mfspr(val, chud_7400_mmcr1); break; }
487 if(spr==chud_7400_pmc3) { mfspr(val, chud_7400_pmc3); break; }
488 if(spr==chud_7400_pmc4) { mfspr(val, chud_7400_pmc4); break; }
489 if(spr==chud_7400_hid0) { mfspr(val, chud_7400_hid0); break; }
490 if(spr==chud_7400_hid1) { mfspr(val, chud_7400_hid1); break; }
491 if(spr==chud_7400_iabr) { mfspr(val, chud_7400_iabr); break; }
492 if(spr==chud_7400_msscr0) { mfspr(val, chud_7400_msscr0); break; }
493 if(spr==chud_7400_msscr1) { mfspr(val, chud_7400_msscr1); break; } /* private */
494 if(spr==chud_7400_ictc) { mfspr(val, chud_7400_ictc); break; }
495 if(spr==chud_7400_thrm1) { mfspr(val, chud_7400_thrm1); break; }
496 if(spr==chud_7400_thrm2) { mfspr(val, chud_7400_thrm2); break; }
497 if(spr==chud_7400_thrm3) { mfspr(val, chud_7400_thrm3); break; }
498 if(spr==chud_7400_pir) { mfspr(val, chud_7400_pir); break; }
499 if(spr==chud_7400_l2cr) { mfspr(val, chud_7400_l2cr); break; }
500
501 // 7410 only
502 if(spr==chud_7410_l2pmcr) { mfspr(val, chud_7410_l2pmcr); break; }
503 }
504
505 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7450) {
506 if(spr==chud_7450_mmcr2) { mfspr(val, chud_7450_mmcr2); break; }
507 if(spr==chud_7450_pmc5) { mfspr(val, chud_7450_pmc5); break; }
508 if(spr==chud_7450_pmc6) { mfspr(val, chud_7450_pmc6); break; }
509 if(spr==chud_7450_bamr) { mfspr(val, chud_7450_bamr); break; }
510 if(spr==chud_7450_mmcr0) { mfspr(val, chud_7450_mmcr0); break; }
511 if(spr==chud_7450_pmc1) { mfspr(val, chud_7450_pmc1); break; }
512 if(spr==chud_7450_pmc2) { mfspr(val, chud_7450_pmc2); break; }
513 if(spr==chud_7450_siar) { mfspr(val, chud_7450_siar); break; }
514 if(spr==chud_7450_mmcr1) { mfspr(val, chud_7450_mmcr1); break; }
515 if(spr==chud_7450_pmc3) { mfspr(val, chud_7450_pmc3); break; }
516 if(spr==chud_7450_pmc4) { mfspr(val, chud_7450_pmc4); break; }
517 if(spr==chud_7450_tlbmiss) { mfspr(val, chud_7450_tlbmiss); break; }
518 if(spr==chud_7450_ptehi) { mfspr(val, chud_7450_ptehi); break; }
519 if(spr==chud_7450_ptelo) { mfspr(val, chud_7450_ptelo); break; }
520 if(spr==chud_7450_l3pm) { mfspr(val, chud_7450_l3pm); break; }
521 if(spr==chud_7450_hid0) { mfspr(val, chud_7450_hid0); break; }
522 if(spr==chud_7450_hid1) { mfspr(val, chud_7450_hid1); break; }
523 if(spr==chud_7450_iabr) { mfspr(val, chud_7450_iabr); break; }
524 if(spr==chud_7450_ldstdb) { mfspr(val, chud_7450_ldstdb); break; }
525 if(spr==chud_7450_msscr0) { mfspr(val, chud_7450_msscr0); break; }
526 if(spr==chud_7450_msssr0) { mfspr(val, chud_7450_msssr0); break; }
527 if(spr==chud_7450_ldstcr) { mfspr(val, chud_7450_ldstcr); break; }
528 if(spr==chud_7450_ictc) { mfspr(val, chud_7450_ictc); break; }
529 if(spr==chud_7450_ictrl) { mfspr(val, chud_7450_ictrl); break; }
530 if(spr==chud_7450_thrm1) { mfspr(val, chud_7450_thrm1); break; }
531 if(spr==chud_7450_thrm2) { mfspr(val, chud_7450_thrm2); break; }
532 if(spr==chud_7450_thrm3) { mfspr(val, chud_7450_thrm3); break; }
533 if(spr==chud_7450_pir) { mfspr(val, chud_7450_pir); break; }
534 if(spr==chud_7450_l2cr) { mfspr(val, chud_7450_l2cr); break; }
535 if(spr==chud_7450_l3cr) { mfspr(val, chud_7450_l3cr); break; }
536
537 // 7455/7457 only
538 if(spr==chud_7455_sprg4) { mfspr(val, chud_7455_sprg4); break; }
539 if(spr==chud_7455_sprg5) { mfspr(val, chud_7455_sprg5); break; }
540 if(spr==chud_7455_sprg6) { mfspr(val, chud_7455_sprg6); break; }
541 if(spr==chud_7455_sprg7) { mfspr(val, chud_7455_sprg7); break; }
542 if(spr==chud_7455_ibat4u) { mfspr(val, chud_7455_ibat4u); break; }
543 if(spr==chud_7455_ibat4l) { mfspr(val, chud_7455_ibat4l); break; }
544 if(spr==chud_7455_ibat5u) { mfspr(val, chud_7455_ibat5u); break; }
545 if(spr==chud_7455_ibat5l) { mfspr(val, chud_7455_ibat5l); break; }
546 if(spr==chud_7455_ibat6u) { mfspr(val, chud_7455_ibat6u); break; }
547 if(spr==chud_7455_ibat6l) { mfspr(val, chud_7455_ibat6l); break; }
548 if(spr==chud_7455_ibat7u) { mfspr(val, chud_7455_ibat7u); break; }
549 if(spr==chud_7455_ibat7l) { mfspr(val, chud_7455_ibat7l); break; }
550 if(spr==chud_7455_dbat4u) { mfspr(val, chud_7455_dbat4u); break; }
551 if(spr==chud_7455_dbat4l) { mfspr(val, chud_7455_dbat4l); break; }
552 if(spr==chud_7455_dbat5u) { mfspr(val, chud_7455_dbat5u); break; }
553 if(spr==chud_7455_dbat5l) { mfspr(val, chud_7455_dbat5l); break; }
554 if(spr==chud_7455_dbat6u) { mfspr(val, chud_7455_dbat6u); break; }
555 if(spr==chud_7455_dbat6l) { mfspr(val, chud_7455_dbat6l); break; }
556 if(spr==chud_7455_dbat7u) { mfspr(val, chud_7455_dbat7u); break; }
557 if(spr==chud_7455_dbat7l) { mfspr(val, chud_7455_dbat7l); break; }
558 }
559
560 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
561 if(spr==chud_970_pir) { mfspr(val, chud_970_pir); break; }
562 if(spr==chud_970_pmc1) { mfspr(val, chud_970_pmc1); break; }
563 if(spr==chud_970_pmc2) { mfspr(val, chud_970_pmc2); break; }
564 if(spr==chud_970_pmc3) { mfspr(val, chud_970_pmc3); break; }
565 if(spr==chud_970_pmc4) { mfspr(val, chud_970_pmc4); break; }
566 if(spr==chud_970_pmc5) { mfspr(val, chud_970_pmc5); break; }
567 if(spr==chud_970_pmc6) { mfspr(val, chud_970_pmc6); break; }
568 if(spr==chud_970_pmc7) { mfspr(val, chud_970_pmc7); break; }
569 if(spr==chud_970_pmc8) { mfspr(val, chud_970_pmc8); break; }
570 if(spr==chud_970_hdec) { mfspr(val, chud_970_hdec); break; }
571 }
572
573 /* we only get here if none of the above cases qualify */
574 retval = KERN_INVALID_ARGUMENT;
575 } while(0);
576
577 chudxnu_set_interrupts_enabled(oldlevel); /* enable interrupts */
578
579 if(cpu>=0) { // cpu<0 means don't bind
580 chudxnu_unbind_thread(current_thread());
581 }
582
583 *val_p = val;
584
585 return retval;
586}
587
588__private_extern__
589kern_return_t chudxnu_read_spr64(int cpu, int spr, uint64_t *val_p)
590{
591 kern_return_t retval = KERN_SUCCESS;
592 boolean_t oldlevel;
593
594 /* bind to requested CPU */
595 if(cpu>=0) { // cpu<0 means don't bind
596 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
597 return KERN_INVALID_ARGUMENT;
598 }
599 }
600
601 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
602
603 do {
604 /* PPC SPRs - 32-bit and 64-bit implementations */
605 if(spr==chud_ppc_srr0) { retval = mfspr64(val_p, chud_ppc_srr0); break; }
606 if(spr==chud_ppc_srr1) { retval = mfspr64(val_p, chud_ppc_srr1); break; }
607 if(spr==chud_ppc_dar) { retval = mfspr64(val_p, chud_ppc_dar); break; }
608 if(spr==chud_ppc_dsisr) { retval = mfspr64(val_p, chud_ppc_dsisr); break; }
609 if(spr==chud_ppc_sdr1) { retval = mfspr64(val_p, chud_ppc_sdr1); break; }
610 if(spr==chud_ppc_sprg0) { retval = mfspr64(val_p, chud_ppc_sprg0); break; }
611 if(spr==chud_ppc_sprg1) { retval = mfspr64(val_p, chud_ppc_sprg1); break; }
612 if(spr==chud_ppc_sprg2) { retval = mfspr64(val_p, chud_ppc_sprg2); break; }
613 if(spr==chud_ppc_sprg3) { retval = mfspr64(val_p, chud_ppc_sprg3); break; }
614 if(spr==chud_ppc_dabr) { retval = mfspr64(val_p, chud_ppc_dabr); break; }
615 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
616 struct ppc_thread_state64 state;
617 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
618 kern_return_t kr;
619 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
620 if(KERN_SUCCESS==kr) {
621 *val_p = state.srr1;
622 } else {
623 retval = KERN_FAILURE;
624 }
625 break;
626 }
627
628 /* PPC SPRs - 64-bit implementations */
629 if(spr==chud_ppc64_asr) { retval = mfspr64(val_p, chud_ppc64_asr); break; }
630 if(spr==chud_ppc64_accr) { retval = mfspr64(val_p, chud_ppc64_accr); break; }
631
632 /* Implementation Specific SPRs */
633 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
634 if(spr==chud_970_hid0) { retval = mfspr64(val_p, chud_970_hid0); break; }
635 if(spr==chud_970_hid1) { retval = mfspr64(val_p, chud_970_hid1); break; }
636 if(spr==chud_970_hid4) { retval = mfspr64(val_p, chud_970_hid4); break; }
637 if(spr==chud_970_hid5) { retval = mfspr64(val_p, chud_970_hid5); break; }
638 if(spr==chud_970_mmcr0) { retval = mfspr64(val_p, chud_970_mmcr0); break; }
639 if(spr==chud_970_mmcr1) { retval = mfspr64(val_p, chud_970_mmcr1); break; }
640 if(spr==chud_970_mmcra) { retval = mfspr64(val_p, chud_970_mmcra); break; }
641 if(spr==chud_970_siar) { retval = mfspr64(val_p, chud_970_siar); break; }
642 if(spr==chud_970_sdar) { retval = mfspr64(val_p, chud_970_sdar); break; }
643 if(spr==chud_970_imc) { retval = mfspr64(val_p, chud_970_imc); break; }
644 if(spr==chud_970_rmor) { retval = mfspr64(val_p, chud_970_rmor); break; }
645 if(spr==chud_970_hrmor) { retval = mfspr64(val_p, chud_970_hrmor); break; }
646 if(spr==chud_970_hior) { retval = mfspr64(val_p, chud_970_hior); break; }
647 if(spr==chud_970_lpidr) { retval = mfspr64(val_p, chud_970_lpidr); break; }
648 if(spr==chud_970_lpcr) { retval = mfspr64(val_p, chud_970_lpcr); break; }
649 if(spr==chud_970_dabrx) { retval = mfspr64(val_p, chud_970_dabrx); break; }
650 if(spr==chud_970_hsprg0) { retval = mfspr64(val_p, chud_970_hsprg0); break; }
651 if(spr==chud_970_hsprg1) { retval = mfspr64(val_p, chud_970_hsprg1); break; }
652 if(spr==chud_970_hsrr0) { retval = mfspr64(val_p, chud_970_hsrr0); break; }
653 if(spr==chud_970_hsrr1) { retval = mfspr64(val_p, chud_970_hsrr1); break; }
654 if(spr==chud_970_hdec) { retval = mfspr64(val_p, chud_970_hdec); break; }
655 if(spr==chud_970_trig0) { retval = mfspr64(val_p, chud_970_trig0); break; }
656 if(spr==chud_970_trig1) { retval = mfspr64(val_p, chud_970_trig1); break; }
657 if(spr==chud_970_trig2) { retval = mfspr64(val_p, chud_970_trig2); break; }
658 if(spr==chud_970_scomc) { retval = mfspr64(val_p, chud_970_scomc); break; }
659 if(spr==chud_970_scomd) { retval = mfspr64(val_p, chud_970_scomd); break; }
660 }
661
662 /* we only get here if none of the above cases qualify */
663 *val_p = 0xFFFFFFFFFFFFFFFFLL;
664 retval = KERN_INVALID_ARGUMENT;
665 } while(0);
666
667 chudxnu_set_interrupts_enabled(oldlevel); /* enable interrupts */
668
669 if(cpu>=0) { // cpu<0 means don't bind
670 chudxnu_unbind_thread(current_thread());
671 }
672
673 return retval;
55e303ae
A		 674}
675
91447636
A		 676__private_extern__
677kern_return_t chudxnu_write_spr(int cpu, int spr, uint32_t val)
678{
679 kern_return_t retval = KERN_SUCCESS;
680 boolean_t oldlevel;
681
682 /* bind to requested CPU */
683 if(cpu>=0) { // cpu<0 means don't bind
684 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
685 return KERN_INVALID_ARGUMENT;
686 }
687 }
688
689 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
690
691 do {
692 /* PPC SPRs - 32-bit and 64-bit implementations */
693 if(spr==chud_ppc_srr0) { mtspr(chud_ppc_srr0, val); break; }
694 if(spr==chud_ppc_srr1) { mtspr(chud_ppc_srr1, val); break; }
695 if(spr==chud_ppc_dsisr) { mtspr(chud_ppc_dsisr, val); break; }
696 if(spr==chud_ppc_dar) { mtspr(chud_ppc_dar, val); break; }
697 if(spr==chud_ppc_dec) { mtspr(chud_ppc_dec, val); break; }
698 if(spr==chud_ppc_sdr1) { mtspr(chud_ppc_sdr1, val); break; }
699 if(spr==chud_ppc_sprg0) { mtspr(chud_ppc_sprg0, val); break; }
700 if(spr==chud_ppc_sprg1) { mtspr(chud_ppc_sprg1, val); break; }
701 if(spr==chud_ppc_sprg2) { mtspr(chud_ppc_sprg2, val); break; }
702 if(spr==chud_ppc_sprg3) { mtspr(chud_ppc_sprg3, val); break; }
703 if(spr==chud_ppc_ear) { mtspr(chud_ppc_ear, val); break; }
704 if(spr==chud_ppc_tbl) { mtspr(284, val); break; } /* timebase consists of read registers and write registers */
705 if(spr==chud_ppc_tbu) { mtspr(285, val); break; }
706 if(spr==chud_ppc_pvr) { mtspr(chud_ppc_pvr, val); break; }
707 if(spr==chud_ppc_ibat0u) { mtspr(chud_ppc_ibat0u, val); break; }
708 if(spr==chud_ppc_ibat0l) { mtspr(chud_ppc_ibat0l, val); break; }
709 if(spr==chud_ppc_ibat1u) { mtspr(chud_ppc_ibat1u, val); break; }
710 if(spr==chud_ppc_ibat1l) { mtspr(chud_ppc_ibat1l, val); break; }
711 if(spr==chud_ppc_ibat2u) { mtspr(chud_ppc_ibat2u, val); break; }
712 if(spr==chud_ppc_ibat2l) { mtspr(chud_ppc_ibat2l, val); break; }
713 if(spr==chud_ppc_ibat3u) { mtspr(chud_ppc_ibat3u, val); break; }
714 if(spr==chud_ppc_ibat3l) { mtspr(chud_ppc_ibat3l, val); break; }
715 if(spr==chud_ppc_dbat0u) { mtspr(chud_ppc_dbat0u, val); break; }
716 if(spr==chud_ppc_dbat0l) { mtspr(chud_ppc_dbat0l, val); break; }
717 if(spr==chud_ppc_dbat1u) { mtspr(chud_ppc_dbat1u, val); break; }
718 if(spr==chud_ppc_dbat1l) { mtspr(chud_ppc_dbat1l, val); break; }
719 if(spr==chud_ppc_dbat2u) { mtspr(chud_ppc_dbat2u, val); break; }
720 if(spr==chud_ppc_dbat2l) { mtspr(chud_ppc_dbat2l, val); break; }
721 if(spr==chud_ppc_dbat3u) { mtspr(chud_ppc_dbat3u, val); break; }
722 if(spr==chud_ppc_dbat3l) { mtspr(chud_ppc_dbat3l, val); break; }
723 if(spr==chud_ppc_dabr) { mtspr(chud_ppc_dabr, val); break; }
724 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
725 struct ppc_thread_state64 state;
726 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
727 kern_return_t kr;
728 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
729 if(KERN_SUCCESS==kr) {
730 state.srr1 = val;
731 kr = chudxnu_thread_set_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, count, TRUE /* user only */);
732 if(KERN_SUCCESS!=kr) {
733 retval = KERN_FAILURE;
734 }
735 } else {
736 retval = KERN_FAILURE;
737 }
738 break;
739 }
740
741 /* PPC SPRs - 32-bit implementations */
742 if(spr==chud_ppc32_sr0) { mtsr(0, val); break; }
743 if(spr==chud_ppc32_sr1) { mtsr(1, val); break; }
744 if(spr==chud_ppc32_sr2) { mtsr(2, val); break; }
745 if(spr==chud_ppc32_sr3) { mtsr(3, val); break; }
746 if(spr==chud_ppc32_sr4) { mtsr(4, val); break; }
747 if(spr==chud_ppc32_sr5) { mtsr(5, val); break; }
748 if(spr==chud_ppc32_sr6) { mtsr(6, val); break; }
749 if(spr==chud_ppc32_sr7) { mtsr(7, val); break; }
750 if(spr==chud_ppc32_sr8) { mtsr(8, val); break; }
751 if(spr==chud_ppc32_sr9) { mtsr(9, val); break; }
752 if(spr==chud_ppc32_sr10) { mtsr(10, val); break; }
753 if(spr==chud_ppc32_sr11) { mtsr(11, val); break; }
754 if(spr==chud_ppc32_sr12) { mtsr(12, val); break; }
755 if(spr==chud_ppc32_sr13) { mtsr(13, val); break; }
756 if(spr==chud_ppc32_sr14) { mtsr(14, val); break; }
757 if(spr==chud_ppc32_sr15) { mtsr(15, val); break; }
758
759 /* Implementation Specific SPRs */
760 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_750) {
761 if(spr==chud_750_mmcr0) { mtspr(chud_750_mmcr0, val); break; }
762 if(spr==chud_750_pmc1) { mtspr(chud_750_pmc1, val); break; }
763 if(spr==chud_750_pmc2) { mtspr(chud_750_pmc2, val); break; }
764 if(spr==chud_750_sia) { mtspr(chud_750_sia, val); break; }
765 if(spr==chud_750_mmcr1) { mtspr(chud_750_mmcr1, val); break; }
766 if(spr==chud_750_pmc3) { mtspr(chud_750_pmc3, val); break; }
767 if(spr==chud_750_pmc4) { mtspr(chud_750_pmc4, val); break; }
768 if(spr==chud_750_iabr) { mtspr(chud_750_iabr, val); break; }
769 if(spr==chud_750_ictc) { mtspr(chud_750_ictc, val); break; }
770 if(spr==chud_750_thrm1) { mtspr(chud_750_thrm1, val); break; }
771 if(spr==chud_750_thrm2) { mtspr(chud_750_thrm2, val); break; }
772 if(spr==chud_750_thrm3) { mtspr(chud_750_thrm3, val); break; }
773 if(spr==chud_750_l2cr) {
774 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
775 break;
776 }
777 if(spr==chud_750_hid0) {
778 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
779 break;
780 }
781 if(spr==chud_750_hid1) {
782 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
783 break;
784 }
785
786 // 750FX only
787 if(spr==chud_750fx_ibat4u) { mtspr(chud_750fx_ibat4u, val); break; }
788 if(spr==chud_750fx_ibat4l) { mtspr(chud_750fx_ibat4l, val); break; }
789 if(spr==chud_750fx_ibat5u) { mtspr(chud_750fx_ibat5u, val); break; }
790 if(spr==chud_750fx_ibat5l) { mtspr(chud_750fx_ibat5l, val); break; }
791 if(spr==chud_750fx_ibat6u) { mtspr(chud_750fx_ibat6u, val); break; }
792 if(spr==chud_750fx_ibat6l) { mtspr(chud_750fx_ibat6l, val); break; }
793 if(spr==chud_750fx_ibat7u) { mtspr(chud_750fx_ibat7u, val); break; }
794 if(spr==chud_750fx_ibat7l) { mtspr(chud_750fx_ibat7l, val); break; }
795 if(spr==chud_750fx_dbat4u) { mtspr(chud_750fx_dbat4u, val); break; }
796 if(spr==chud_750fx_dbat4l) { mtspr(chud_750fx_dbat4l, val); break; }
797 if(spr==chud_750fx_dbat5u) { mtspr(chud_750fx_dbat5u, val); break; }
798 if(spr==chud_750fx_dbat5l) { mtspr(chud_750fx_dbat5l, val); break; }
799 if(spr==chud_750fx_dbat6u) { mtspr(chud_750fx_dbat6u, val); break; }
800 if(spr==chud_750fx_dbat6l) { mtspr(chud_750fx_dbat6l, val); break; }
801 if(spr==chud_750fx_dbat7u) { mtspr(chud_750fx_dbat7u, val); break; }
802 if(spr==chud_750fx_dbat7l) { mtspr(chud_750fx_dbat7l, val); break; }
803
804 // 750FX >= DDR2.x
805 if(spr==chud_750fx_hid2) { mtspr(chud_750fx_hid2, val); break; }
806 }
807
808 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7400) {
809 if(spr==chud_7400_mmcr2) { mtspr(chud_7400_mmcr2, val); break; }
810 if(spr==chud_7400_bamr) { mtspr(chud_7400_bamr, val); break; }
811 if(spr==chud_7400_mmcr0) { mtspr(chud_7400_mmcr0, val); break; }
812 if(spr==chud_7400_pmc1) { mtspr(chud_7400_pmc1, val); break; }
813 if(spr==chud_7400_pmc2) { mtspr(chud_7400_pmc2, val); break; }
814 if(spr==chud_7400_siar) { mtspr(chud_7400_siar, val); break; }
815 if(spr==chud_7400_mmcr1) { mtspr(chud_7400_mmcr1, val); break; }
816 if(spr==chud_7400_pmc3) { mtspr(chud_7400_pmc3, val); break; }
817 if(spr==chud_7400_pmc4) { mtspr(chud_7400_pmc4, val); break; }
818 if(spr==chud_7400_iabr) { mtspr(chud_7400_iabr, val); break; }
819 if(spr==chud_7400_ictc) { mtspr(chud_7400_ictc, val); break; }
820 if(spr==chud_7400_thrm1) { mtspr(chud_7400_thrm1, val); break; }
821 if(spr==chud_7400_thrm2) { mtspr(chud_7400_thrm2, val); break; }
822 if(spr==chud_7400_thrm3) { mtspr(chud_7400_thrm3, val); break; }
823 if(spr==chud_7400_pir) { mtspr(chud_7400_pir, val); break; }
824
825 if(spr==chud_7400_l2cr) {
826 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
827 break;
828 }
829 if(spr==chud_7400_hid0) {
830 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
831 break;
832 }
833 if(spr==chud_7400_hid1) {
834 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
835 break;
836 }
837 if(spr==chud_7400_msscr0) {
838 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
839 break;
840 }
841 if(spr==chud_7400_msscr1) { /* private */
842 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
843 break;
844 }
845
846 // 7410 only
847 if(spr==chud_7410_l2pmcr) { mtspr(chud_7410_l2pmcr, val); break; }
848 }
849
850 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7450) {
851 if(spr==chud_7450_mmcr2) { mtspr(chud_7450_mmcr2, val); break; }
852 if(spr==chud_7450_pmc5) { mtspr(chud_7450_pmc5, val); break; }
853 if(spr==chud_7450_pmc6) { mtspr(chud_7450_pmc6, val); break; }
854 if(spr==chud_7450_bamr) { mtspr(chud_7450_bamr, val); break; }
855 if(spr==chud_7450_mmcr0) { mtspr(chud_7450_mmcr0, val); break; }
856 if(spr==chud_7450_pmc1) { mtspr(chud_7450_pmc1, val); break; }
857 if(spr==chud_7450_pmc2) { mtspr(chud_7450_pmc2, val); break; }
858 if(spr==chud_7450_siar) { mtspr(chud_7450_siar, val); break; }
859 if(spr==chud_7450_mmcr1) { mtspr(chud_7450_mmcr1, val); break; }
860 if(spr==chud_7450_pmc3) { mtspr(chud_7450_pmc3, val); break; }
861 if(spr==chud_7450_pmc4) { mtspr(chud_7450_pmc4, val); break; }
862 if(spr==chud_7450_tlbmiss) { mtspr(chud_7450_tlbmiss, val); break; }
863 if(spr==chud_7450_ptehi) { mtspr(chud_7450_ptehi, val); break; }
864 if(spr==chud_7450_ptelo) { mtspr(chud_7450_ptelo, val); break; }
865 if(spr==chud_7450_l3pm) { mtspr(chud_7450_l3pm, val); break; }
866 if(spr==chud_7450_iabr) { mtspr(chud_7450_iabr, val); break; }
867 if(spr==chud_7450_ldstdb) { mtspr(chud_7450_ldstdb, val); break; }
868 if(spr==chud_7450_ictc) { mtspr(chud_7450_ictc, val); break; }
869 if(spr==chud_7450_thrm1) { mtspr(chud_7450_thrm1, val); break; }
870 if(spr==chud_7450_thrm2) { mtspr(chud_7450_thrm2, val); break; }
871 if(spr==chud_7450_thrm3) { mtspr(chud_7450_thrm3, val); break; }
872 if(spr==chud_7450_pir) { mtspr(chud_7450_pir, val); break; }
873
874 if(spr==chud_7450_l2cr) {
875 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
876 break;
877 }
878
879 if(spr==chud_7450_l3cr) {
880 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
881 break;
882 }
883 if(spr==chud_7450_ldstcr) {
884 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
885 break;
886 }
887 if(spr==chud_7450_hid0) {
888 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
889 break;
890 }
891 if(spr==chud_7450_hid1) {
892 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
893 break;
894 }
895 if(spr==chud_7450_msscr0) {
896 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
897 break;
898 }
899 if(spr==chud_7450_msssr0) {
900 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
901 break;
902 }
903 if(spr==chud_7450_ictrl) {
904 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
905 break;
906 }
907
908 // 7455/7457 only
909 if(spr==chud_7455_sprg4) { mtspr(chud_7455_sprg4, val); break; }
910 if(spr==chud_7455_sprg5) { mtspr(chud_7455_sprg5, val); break; }
911 if(spr==chud_7455_sprg6) { mtspr(chud_7455_sprg6, val); break; }
912 if(spr==chud_7455_sprg7) { mtspr(chud_7455_sprg7, val); break; }
913 if(spr==chud_7455_ibat4u) { mtspr(chud_7455_ibat4u, val); break; }
914 if(spr==chud_7455_ibat4l) { mtspr(chud_7455_ibat4l, val); break; }
915 if(spr==chud_7455_ibat5u) { mtspr(chud_7455_ibat5u, val); break; }
916 if(spr==chud_7455_ibat5l) { mtspr(chud_7455_ibat5l, val); break; }
917 if(spr==chud_7455_ibat6u) { mtspr(chud_7455_ibat6u, val); break; }
918 if(spr==chud_7455_ibat6l) { mtspr(chud_7455_ibat6l, val); break; }
919 if(spr==chud_7455_ibat7u) { mtspr(chud_7455_ibat7u, val); break; }
920 if(spr==chud_7455_ibat7l) { mtspr(chud_7455_ibat7l, val); break; }
921 if(spr==chud_7455_dbat4u) { mtspr(chud_7455_dbat4u, val); break; }
922 if(spr==chud_7455_dbat4l) { mtspr(chud_7455_dbat4l, val); break; }
923 if(spr==chud_7455_dbat5u) { mtspr(chud_7455_dbat5u, val); break; }
924 if(spr==chud_7455_dbat5l) { mtspr(chud_7455_dbat5l, val); break; }
925 if(spr==chud_7455_dbat6u) { mtspr(chud_7455_dbat6u, val); break; }
926 if(spr==chud_7455_dbat6l) { mtspr(chud_7455_dbat6l, val); break; }
927 if(spr==chud_7455_dbat7u) { mtspr(chud_7455_dbat7u, val); break; }
928 if(spr==chud_7455_dbat7l) { mtspr(chud_7455_dbat7l, val); break; }
929 }
930
931 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
932 if(spr==chud_970_pir) { mtspr(chud_970_pir, val); break; }
933 if(spr==chud_970_pmc1) { mtspr(chud_970_pmc1, val); break; }
934 if(spr==chud_970_pmc2) { mtspr(chud_970_pmc2, val); break; }
935 if(spr==chud_970_pmc3) { mtspr(chud_970_pmc3, val); break; }
936 if(spr==chud_970_pmc4) { mtspr(chud_970_pmc4, val); break; }
937 if(spr==chud_970_pmc5) { mtspr(chud_970_pmc5, val); break; }
938 if(spr==chud_970_pmc6) { mtspr(chud_970_pmc6, val); break; }
939 if(spr==chud_970_pmc7) { mtspr(chud_970_pmc7, val); break; }
940 if(spr==chud_970_pmc8) { mtspr(chud_970_pmc8, val); break; }
941 if(spr==chud_970_hdec) { mtspr(chud_970_hdec, val); break; }
942 }
943
944 /* we only get here if none of the above cases qualify */
945 retval = KERN_INVALID_ARGUMENT;
946 } while(0);
947
948 chudxnu_set_interrupts_enabled(oldlevel); /* re-enable interrupts */
949
950 if(cpu>=0) { // cpu<0 means don't bind
951 chudxnu_unbind_thread(current_thread());
952 }
953
954 return retval;
955}
956
957__private_extern__
958kern_return_t chudxnu_write_spr64(int cpu, int spr, uint64_t val)
959{
960 kern_return_t retval = KERN_SUCCESS;
961 boolean_t oldlevel;
962 uint64_t *val_p = &val;
963
964 /* bind to requested CPU */
965 if(cpu>=0) { // cpu<0 means don't bind
966 if(chudxnu_bind_thread(current_thread(), cpu)!=KERN_SUCCESS) {
967 return KERN_INVALID_ARGUMENT;
968 }
969 }
970
971 oldlevel = ml_set_interrupts_enabled(FALSE); /* disable interrupts */
972
973 do {
974 /* PPC SPRs - 32-bit and 64-bit implementations */
975 if(spr==chud_ppc_srr0) { retval = mtspr64(chud_ppc_srr0, val_p); break; }
976 if(spr==chud_ppc_srr1) { retval = mtspr64(chud_ppc_srr1, val_p); break; }
977 if(spr==chud_ppc_dar) { retval = mtspr64(chud_ppc_dar, val_p); break; }
978 if(spr==chud_ppc_dsisr) { retval = mtspr64(chud_ppc_dsisr, val_p); break; }
979 if(spr==chud_ppc_sdr1) { retval = mtspr64(chud_ppc_sdr1, val_p); break; }
980 if(spr==chud_ppc_sprg0) { retval = mtspr64(chud_ppc_sprg0, val_p); break; }
981 if(spr==chud_ppc_sprg1) { retval = mtspr64(chud_ppc_sprg1, val_p); break; }
982 if(spr==chud_ppc_sprg2) { retval = mtspr64(chud_ppc_sprg2, val_p); break; }
983 if(spr==chud_ppc_sprg3) { retval = mtspr64(chud_ppc_sprg3, val_p); break; }
984 if(spr==chud_ppc_dabr) { retval = mtspr64(chud_ppc_dabr, val_p); break; }
985 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
986 struct ppc_thread_state64 state;
987 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
988 kern_return_t kr;
989 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
990 if(KERN_SUCCESS==kr) {
991 state.srr1 = val;
992 kr = chudxnu_thread_set_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, count, TRUE /* user only */);
993 if(KERN_SUCCESS!=kr) {
994 retval = KERN_FAILURE;
995 }
996 } else {
997 retval = KERN_FAILURE;
998 }
999 break;
1000 }
1001
1002 /* PPC SPRs - 64-bit implementations */
1003 if(spr==chud_ppc64_asr) { retval = mtspr64(chud_ppc64_asr, val_p); break; }
1004 if(spr==chud_ppc64_accr) { retval = mtspr64(chud_ppc64_accr, val_p); break; }
1005 if(spr==chud_ppc64_ctrl) { retval = mtspr64(chud_ppc64_ctrl, val_p); break; }
1006
1007 /* Implementation Specific SPRs */
1008 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
1009 if(spr==chud_970_hid0) { retval = mtspr64(chud_970_hid0, val_p); break; }
1010 if(spr==chud_970_hid1) { retval = mtspr64(chud_970_hid1, val_p); break; }
1011 if(spr==chud_970_hid4) { retval = mtspr64(chud_970_hid4, val_p); break; }
1012 if(spr==chud_970_hid5) { retval = mtspr64(chud_970_hid5, val_p); break; }
1013 if(spr==chud_970_mmcr0) { retval = mtspr64(chud_970_mmcr0, val_p); break; }
1014 if(spr==chud_970_mmcr1) { retval = mtspr64(chud_970_mmcr1, val_p); break; }
1015 if(spr==chud_970_mmcra) { retval = mtspr64(chud_970_mmcra, val_p); break; }
1016 if(spr==chud_970_siar) { retval = mtspr64(chud_970_siar, val_p); break; }
1017 if(spr==chud_970_sdar) { retval = mtspr64(chud_970_sdar, val_p); break; }
1018 if(spr==chud_970_imc) { retval = mtspr64(chud_970_imc, val_p); break; }
1019
1020 if(spr==chud_970_rmor) { retval = mtspr64(chud_970_rmor, val_p); break; }
1021 if(spr==chud_970_hrmor) { retval = mtspr64(chud_970_hrmor, val_p); break; }
1022 if(spr==chud_970_hior) { retval = mtspr64(chud_970_hior, val_p); break; }
1023 if(spr==chud_970_lpidr) { retval = mtspr64(chud_970_lpidr, val_p); break; }
1024 if(spr==chud_970_lpcr) { retval = mtspr64(chud_970_lpcr, val_p); break; }
1025 if(spr==chud_970_dabrx) { retval = mtspr64(chud_970_dabrx, val_p); break; }
1026
1027 if(spr==chud_970_hsprg0) { retval = mtspr64(chud_970_hsprg0, val_p); break; }
1028 if(spr==chud_970_hsprg1) { retval = mtspr64(chud_970_hsprg1, val_p); break; }
1029 if(spr==chud_970_hsrr0) { retval = mtspr64(chud_970_hsrr0, val_p); break; }
1030 if(spr==chud_970_hsrr1) { retval = mtspr64(chud_970_hsrr1, val_p); break; }
1031 if(spr==chud_970_hdec) { retval = mtspr64(chud_970_hdec, val_p); break; }
1032 if(spr==chud_970_trig0) { retval = mtspr64(chud_970_trig0, val_p); break; }
1033 if(spr==chud_970_trig1) { retval = mtspr64(chud_970_trig1, val_p); break; }
1034 if(spr==chud_970_trig2) { retval = mtspr64(chud_970_trig2, val_p); break; }
1035 if(spr==chud_970_scomc) { retval = mtspr64(chud_970_scomc, val_p); break; }
1036 if(spr==chud_970_scomd) { retval = mtspr64(chud_970_scomd, val_p); break; }
1037
1038 if(spr==chud_970_hid0) {
1039 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1040 break;
1041 }
1042
1043 if(spr==chud_970_hid1) {
1044 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1045 break;
1046 }
1047
1048 if(spr==chud_970_hid4) {
1049 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1050 break;
1051 }
1052
1053 if(spr==chud_970_hid5) {
1054 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1055 break;
1056 }
1057
1058 }
1059
1060 /* we only get here if none of the above cases qualify */
1061 retval = KERN_INVALID_ARGUMENT;
1062 } while(0);
1063
1064 chudxnu_set_interrupts_enabled(oldlevel); /* re-enable interrupts */
1065
1066 if(cpu>=0) { // cpu<0 means don't bind
1067 chudxnu_unbind_thread(current_thread());
1068 }
1069
1070 return retval;
1071}
1072
1073#pragma mark **** cache flush ****
1074
55e303ae
A		 1075__private_extern__
1076void chudxnu_flush_caches(void)
1077{
1078 cacheInit();
1079}
1080
1081__private_extern__
1082void chudxnu_enable_caches(boolean_t enable)
1083{
1084 if(!enable) {
1085 cacheInit();
1086 cacheDisable();
1087 } else {
1088 cacheInit();
1089 }
1090}
1091
91447636
A		 1092#pragma mark **** perfmon facility ****
1093
55e303ae
A		 1094__private_extern__
1095kern_return_t chudxnu_perfmon_acquire_facility(task_t task)
1096{
1097 return perfmon_acquire_facility(task);
1098}
1099
1100__private_extern__
1101kern_return_t chudxnu_perfmon_release_facility(task_t task)
1102{
1103 return perfmon_release_facility(task);
1104}
1105
91447636
A		 1106#pragma mark **** rupt counters ****
1107
55e303ae
A		 1108__private_extern__
1109kern_return_t chudxnu_get_cpu_rupt_counters(int cpu, rupt_counters_t *rupts)
1110{
1111 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
1112 return KERN_FAILURE;
1113 }
1114
1115 if(rupts) {
1116 boolean_t oldlevel = ml_set_interrupts_enabled(FALSE);
91447636 1117 struct per_proc_info *per_proc;
55e303ae 1118
91447636
A		 1119 per_proc = PerProcTable[cpu].ppe_vaddr;
1120 rupts->hwResets = per_proc->hwCtr.hwResets;
1121 rupts->hwMachineChecks = per_proc->hwCtr.hwMachineChecks;
1122 rupts->hwDSIs = per_proc->hwCtr.hwDSIs;
1123 rupts->hwISIs = per_proc->hwCtr.hwISIs;
1124 rupts->hwExternals = per_proc->hwCtr.hwExternals;
1125 rupts->hwAlignments = per_proc->hwCtr.hwAlignments;
1126 rupts->hwPrograms = per_proc->hwCtr.hwPrograms;
1127 rupts->hwFloatPointUnavailable = per_proc->hwCtr.hwFloatPointUnavailable;
1128 rupts->hwDecrementers = per_proc->hwCtr.hwDecrementers;
1129 rupts->hwIOErrors = per_proc->hwCtr.hwIOErrors;
1130 rupts->hwSystemCalls = per_proc->hwCtr.hwSystemCalls;
1131 rupts->hwTraces = per_proc->hwCtr.hwTraces;
1132 rupts->hwFloatingPointAssists = per_proc->hwCtr.hwFloatingPointAssists;
1133 rupts->hwPerformanceMonitors = per_proc->hwCtr.hwPerformanceMonitors;
1134 rupts->hwAltivecs = per_proc->hwCtr.hwAltivecs;
1135 rupts->hwInstBreakpoints = per_proc->hwCtr.hwInstBreakpoints;
1136 rupts->hwSystemManagements = per_proc->hwCtr.hwSystemManagements;
1137 rupts->hwAltivecAssists = per_proc->hwCtr.hwAltivecAssists;
1138 rupts->hwThermal = per_proc->hwCtr.hwThermal;
1139 rupts->hwSoftPatches = per_proc->hwCtr.hwSoftPatches;
1140 rupts->hwMaintenances = per_proc->hwCtr.hwMaintenances;
1141 rupts->hwInstrumentations = per_proc->hwCtr.hwInstrumentations;
55e303ae
A		 1142
1143 ml_set_interrupts_enabled(oldlevel);
1144 return KERN_SUCCESS;
1145 } else {
1146 return KERN_FAILURE;
1147 }
1148}
1149
1150__private_extern__
1151kern_return_t chudxnu_clear_cpu_rupt_counters(int cpu)
1152{
1153 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
1154 return KERN_FAILURE;
1155 }
1156
91447636 1157 bzero((char *)&(PerProcTable[cpu].ppe_vaddr->hwCtr), sizeof(struct hwCtrs));
55e303ae
A		 1158 return KERN_SUCCESS;
1159}
1160
91447636
A		 1161#pragma mark **** alignment exceptions ****
1162
55e303ae
A		 1163__private_extern__
1164kern_return_t chudxnu_passup_alignment_exceptions(boolean_t enable)
1165{
1166 if(enable) {
1167 dgWork.dgFlags |= enaNotifyEM;
1168 } else {
1169 dgWork.dgFlags &= ~enaNotifyEM;
1170 }
91447636
A		 1171 return KERN_SUCCESS;
1172}
1173
1174#pragma mark **** scom ****
1175kern_return_t chudxnu_scom_read(uint32_t reg, uint64_t *data)
1176{
1177 ml_scom_read(reg, data);
1178 return KERN_SUCCESS;
1179}
1180
1181kern_return_t chudxnu_scom_write(uint32_t reg, uint64_t data)
1182{
1183 ml_scom_write(reg, data);
1184 return KERN_SUCCESS;
55e303ae 1185}
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