[apple/xnu.git] / osfmk / arm / trap.h

/*
 * Copyright (c) 2007 Apple Inc. All rights reserved.
 *
 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
 *
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. The rights granted to you under the License
 * may not be used to create, or enable the creation or redistribution of,
 * unlawful or unlicensed copies of an Apple operating system, or to
 * circumvent, violate, or enable the circumvention or violation of, any
 * terms of an Apple operating system software license agreement.
 *
 * Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this file.
 *
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 *
 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
 */
/*
 * @OSF_COPYRIGHT@
 */
/*
 * Mach Operating System
 * Copyright (c) 1991,1990 Carnegie Mellon University
 * All Rights Reserved.
 *
 * Permission to use, copy, modify and distribute this software and its
 * documentation is hereby granted, provided that both the copyright
 * notice and this permission notice appear in all copies of the
 * software, derivative works or modified versions, and any portions
 * thereof, and that both notices appear in supporting documentation.
 *
 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
 *
 * Carnegie Mellon requests users of this software to return to
 *
 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
 *  School of Computer Science
 *  Carnegie Mellon University
 *  Pittsburgh PA 15213-3890
 *
 * any improvements or extensions that they make and grant Carnegie Mellon
 * the rights to redistribute these changes.
 */
/*
 */

#ifndef _ARM_TRAP_H_
#define _ARM_TRAP_H_

/*
 * Hardware trap vectors for ARM.
 */

#define T_RESET                 0
#define T_UNDEF                 1
#define T_SWI                   2
#define T_PREFETCH_ABT          3
#define T_DATA_ABT              4
#define T_IRQ                   6
#define T_FIQ                   7
#define T_PMU                   8


#define TRAP_NAMES "reset", "undefined instruction", "software interrupt", \
	           "prefetch abort", "data abort", "irq interrupt", \
	           "fast interrupt", "perfmon"

/*
 * Page-fault trap codes.
 */
#define T_PF_PROT               0x1             /* protection violation */
#define T_PF_WRITE              0x2             /* write access */
#define T_PF_USER               0x4             /* from user state */

#if !defined(ASSEMBLER) && defined(MACH_KERNEL)

#include <arm/thread.h>

#define GDB_TRAP_INSTR1 0xe7ffdefe
#define GDB_TRAP_INSTR2 0xe7ffdeff

#define ARM_GDB_INSTR1  GDB_TRAP_INSTR1
#define ARM_GDB_INSTR2  GDB_TRAP_INSTR2

#define IS_ARM_GDB_TRAP(op)     \
	(((op) == ARM_GDB_INSTR1) || ((op) == ARM_GDB_INSTR2))

#define THUMB_GDB_INSTR1        (GDB_TRAP_INSTR1 & 0xFFFF)
#define THUMB_GDB_INSTR2        (GDB_TRAP_INSTR2 & 0xFFFF)

#define IS_THUMB_GDB_TRAP(op)   \
	(((op) == THUMB_GDB_INSTR1) || ((op) == THUMB_GDB_INSTR2))


#define ARM_STR                 0x04000000      /* STR */
#define ARM_STRH                0x000000B0      /* STRH */
#define ARM_STRH_MASK           0x0E1000F0      /* STRH MASK */
#define ARM_SDX_MASK            0x0C100000      /* SINGLE DATA TRANSFER */
#define ARM_SNGL_DX_MASK        0x0C000000      /* SINGLE DATA TRANSFER MASK */
#define ARM_SDX                 0x04000000

#define ARM_STM                 0x08000000      /* STM */
#define ARM_BDX_MASK            0x0E100000      /* BLOCK DATA TRANSFER */
#define ARM_BLK_MASK            0x0E000000      /* BLOCK DATA TRANSFER */
#define ARM_BDX                 0x08000000      /* BLOCK DATA TRANSFER */

#define ARM_WRITE_BACK          0x00200000
#define ARM_BASE_REG            0x000F0000
#define ARM_INCREMENT           0x00800000

#define ARM_STC                 0x0C000000      /* STC */
#define ARM_CDX_MASK            ARM_BDX_MASK    /* COPROCESSOR DATA TRANSFER */
#define ARM_CBLK_MASK           ARM_BLK_MASK
#define ARM_CDX                 0x0C000000      /* COPROCESSOR DATA TRANSFER */

#define ARM_SWP                 0x01000090      /* SWP */
#define ARM_SWP_MASK            0x0FB00FF0      /* SWP */

#define ARM_POST_INDEXING       0x01000000
#define ARM_IMMEDIATE           0x02000000
#define ARM_LSL                 0
#define ARM_LSR                 1
#define ARM_ASR                 2
#define ARM_ROR                 3

#define MCR_MASK        0x0F100F10
#define MCR_CP15        0x0E000F10
#define MCRR_MASK       0x0FF00F00
#define MCRR_CP15       0x0C400F00

#define arm_mcr_cp15(op)        (((op)&MCR_MASK) == 0x0E000F10)
#define arm_mcrr_cp15(op)       (((op)&0x0FF00F00) == 0x0C400F00)

#define IS_THUMB32(op)  (       \
	(((op) & 0xE000) == 0xE000) && (((op) & 0x1800) != 0x0000))

#define THUMB_LDR_1_MASK        0x8800          /* (1) forms of LD* instructions */
#define THUMB_STR_1_MASK        0xF800          /* (1) forms of ST* instructions */
#define THUMB_STR_2_MASK        0xFE00          /* (2) forms of ST* instructions */
#define THUMB_STR_3_MASK        0xF800          /* (3) forms of ST* instructions */
#define THUMB_PUSH_MASK         0xFE00          /* PUSH instruction */

#define THUMB_LDRH_1            0x8800          /* LDRH(1) */
#define THUMB_STMIA             0xC000          /* STMIA */
#define THUMB_STR_1             0x6000          /* STR(1) */
#define THUMB_STR_2             0x5000          /* STR(2) */
#define THUMB_STR_3             0x9000          /* STR(3) */
#define THUMB_STRB_1            0x7000          /* STRB(1) */
#define THUMB_STRB_2            0x5400          /* STRB(2) */
#define THUMB_STRH_1            0x8000          /* STRH(1) */
#define THUMB_STRH_2            0x5200          /* STRH(2) */
#define THUMB_PUSH              0xB400          /* PUSH */
#define THUMB_LDMIA             0xC800          /* LDMIA */
#define THUMB_POP               0xBC00          /* POP */


/*
 * Shifts, masks, and other values for load/store multiple decoding; largely needed for
 * supporting misaligned accesses.
 */
#define THUMB_STR_1_BASE_OFFSET 8               /* Offset of the base register field */
#define THUMB_PUSH_EXTRA_OFFSET 8               /* Offset of the "extra" register field */
#define ARM_STM_BASE_OFFSET     16              /* Offset of the base register field */
#define ARM_STM_LOAD_OFFSET     20              /* Offset of the load flag */
#define ARM_STM_WBACK_OFFSET    21              /* Offset of the writeback flag */
#define ARM_STM_INCR_OFFSET     23              /* Offset of the increment flag */
#define ARM_STM_BEFORE_OFFSET   24              /* Offset of the pre-index flag */
#define ARM_REG_LIST_LR_OFFSET  14              /* Offset of LR in the register list */
#define ARM_REG_LIST_PC_OFFSET  15              /* Offset of PC in the register list */

#define THUMB_STR_REG_LIST_MASK 0x000000FF      /* Offset of the reg list is 0 */
#define THUMB_STR_1_BASE_MASK   0x00000700
#define THUMB_PUSH_EXTRA_MASK   0x00000100
#define ARM_STM_REG_LIST_MASK   0x0000FFFF      /* Offset of the reg list is 0 */
#define ARM_STM_BASE_MASK       0x000F0000
#define ARM_STM_LOAD_MASK       0x00100000
#define ARM_STM_WBACK_MASK      0x00200000
#define ARM_STM_INCR_MASK       0x00800000
#define ARM_STM_BEFORE_MASK     0x01000000
#define ARM_COND_MASK           0xF0000000      /* Mask for the condition code */

#define ARM_COND_UNCOND         0xF0000000      /* Instruction does not support condition codes */

#define ARM_SIMD_MASK0          0xFE000000
#define ARM_SIMD_CODE0          0xF2000000

#define ARM_VFP_MASK0           0x0F000E10
#define ARM_VFP_CODE0           0x0E000A00

#define ARM_SIMD_VFP_MASK0      0x0E000E00
#define ARM_SIMD_VFP_CODE0      0x0C000A00
#define ARM_SIMD_VFP_MASK1      0xFF100000
#define ARM_SIMD_VFP_CODE1      0xF4000000
#define ARM_SIMD_VFP_MASK2      0x0F000E10
#define ARM_SIMD_VFP_CODE2      0x0E000A10
#define ARM_SIMD_VFP_MASK3      0x0FE00E00
#define ARM_SIMD_VFP_CODE3      0x0C400A00

#define IS_ARM_VFP(op)  (       \
	(((op) & ARM_SIMD_MASK0) == ARM_SIMD_CODE0)     \
	 ||(((op) & ARM_VFP_MASK0) == ARM_VFP_CODE0)    \
	 ||(((op) & ARM_SIMD_VFP_MASK0) == ARM_SIMD_VFP_CODE0)  \
	 ||(((op) & ARM_SIMD_VFP_MASK1) == ARM_SIMD_VFP_CODE1)  \
	 ||(((op) & ARM_SIMD_VFP_MASK2) == ARM_SIMD_VFP_CODE2)  \
	 || (((op) & ARM_SIMD_VFP_MASK3) == ARM_SIMD_VFP_CODE3))

#define THUMB_SIMD_MASK0        0xEF000000
#define THUMB_SIMD_CODE0        0xEF000000

#define THUMB_VFP_MASK0         0xEF000E10
#define THUMB_VFP_CODE0         0xEE000A00

#define THUMB_SIMD_VFP_MASK0    0xEE000E00
#define THUMB_SIMD_VFP_CODE0    0xEC000A00
#define THUMB_SIMD_VFP_MASK1    0xFF100000
#define THUMB_SIMD_VFP_CODE1    0xF9000000
#define THUMB_SIMD_VFP_MASK2    0xEF000E10
#define THUMB_SIMD_VFP_CODE2    0xEE000A10
#define THUMB_SIMD_VFP_MASK3    0xEFE00E00
#define THUMB_SIMD_VFP_CODE3    0xEC400A00

#define IS_THUMB_VFP(op)        (       \
	(((op) & THUMB_SIMD_MASK0) == THUMB_SIMD_CODE0 )        \
	 || (((op) & THUMB_VFP_MASK0) == THUMB_VFP_CODE0 )      \
	 || (((op) & THUMB_SIMD_VFP_MASK0) == THUMB_SIMD_VFP_CODE0 )    \
	 || (((op) & THUMB_SIMD_VFP_MASK1) == THUMB_SIMD_VFP_CODE1 )    \
	 || (((op) & THUMB_SIMD_VFP_MASK2) == THUMB_SIMD_VFP_CODE2 )    \
	 || (((op) & THUMB_SIMD_VFP_MASK3) == THUMB_SIMD_VFP_CODE3))

extern boolean_t arm_force_fast_fault(ppnum_t, vm_prot_t, int, void *);
extern kern_return_t arm_fast_fault(pmap_t, vm_map_address_t, vm_prot_t, boolean_t);

/*
 * Determines if the aborted instruction is read or write operation
 */
#define arm_fault_type(op, spsr, vaddr) \
       (((((op)&ARM_CDX_MASK) == ARM_STC) || \
	 (((op)&ARM_STRH_MASK) == ARM_STRH) || \
	 (((op)&ARM_BDX_MASK) == ARM_STM) || \
	 (((op)&ARM_SDX_MASK) == ARM_STR)) ?  \
	                (VM_PROT_WRITE|VM_PROT_READ) : (VM_PROT_READ))

#define thumb_fault_type(op, spsr, vaddr) \
	(((((op)&THUMB_STR_1_MASK) == THUMB_STMIA) || \
	  (((op)&THUMB_STR_1_MASK) == THUMB_STR_1) || \
	  (((op)&THUMB_STR_2_MASK) == THUMB_STR_2) || \
	  (((op)&THUMB_STR_3_MASK) == THUMB_STR_3) || \
	  (((op)&THUMB_STR_1_MASK) == THUMB_STRB_1) || \
	  (((op)&THUMB_STR_2_MASK) == THUMB_STRB_2) || \
	  (((op)&THUMB_STR_1_MASK) == THUMB_STRH_1) || \
	  (((op)&THUMB_STR_2_MASK) == THUMB_STRH_2) || \
	  (((op)&THUMB_PUSH_MASK) == THUMB_PUSH)) ? \
	        (VM_PROT_WRITE|VM_PROT_READ) : (VM_PROT_READ))

typedef kern_return_t (*perfCallback)(
	int                     trapno,
	struct arm_saved_state  *ss,
	uintptr_t *,
	int);

#endif  /* !ASSEMBLER && MACH_KERNEL */

#endif  /* _ARM_TRAP_H_ */
Commit	Line	Data
5ba3f43e A	1	/*
	2	* Copyright (c) 2007 Apple Inc. All rights reserved.
	3	*
	4	* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
	5	*
	6	* This file contains Original Code and/or Modifications of Original Code
	7	* as defined in and that are subject to the Apple Public Source License
	8	* Version 2.0 (the 'License'). You may not use this file except in
	9	* compliance with the License. The rights granted to you under the License
	10	* may not be used to create, or enable the creation or redistribution of,
	11	* unlawful or unlicensed copies of an Apple operating system, or to
	12	* circumvent, violate, or enable the circumvention or violation of, any
	13	* terms of an Apple operating system software license agreement.
	14	*
	15	* Please obtain a copy of the License at
	16	* http://www.opensource.apple.com/apsl/ and read it before using this file.
	17	*
	18	* The Original Code and all software distributed under the License are
	19	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
	20	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
	21	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
	22	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	23	* Please see the License for the specific language governing rights and
	24	* limitations under the License.
	25	*
	26	* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
	27	*/
	28	/*
	29	* @OSF_COPYRIGHT@
	30	*/
0a7de745	31	/*
5ba3f43e A	32	* Mach Operating System
	33	* Copyright (c) 1991,1990 Carnegie Mellon University
	34	* All Rights Reserved.
0a7de745	35	*
5ba3f43e A	36	* Permission to use, copy, modify and distribute this software and its
	37	* documentation is hereby granted, provided that both the copyright
	38	* notice and this permission notice appear in all copies of the
	39	* software, derivative works or modified versions, and any portions
	40	* thereof, and that both notices appear in supporting documentation.
0a7de745	41	*
5ba3f43e A	42	* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
	43	* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
	44	* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
0a7de745	45	*
5ba3f43e	46	* Carnegie Mellon requests users of this software to return to
0a7de745	47	*
5ba3f43e A	48	* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
	49	* School of Computer Science
	50	* Carnegie Mellon University
	51	* Pittsburgh PA 15213-3890
0a7de745	52	*
5ba3f43e A	53	* any improvements or extensions that they make and grant Carnegie Mellon
	54	* the rights to redistribute these changes.
	55	*/
	56	/*
	57	*/
	58
0a7de745 A	59	#ifndef _ARM_TRAP_H_
0a7de745 A	60	#define _ARM_TRAP_H_
5ba3f43e A	61
	62	/*
	63	* Hardware trap vectors for ARM.
	64	*/
	65
	66	#define T_RESET 0
	67	#define T_UNDEF 1
	68	#define T_SWI 2
	69	#define T_PREFETCH_ABT 3
	70	#define T_DATA_ABT 4
	71	#define T_IRQ 6
	72	#define T_FIQ 7
0a7de745	73	#define T_PMU 8
5ba3f43e A	74
	75
	76	#define TRAP_NAMES "reset", "undefined instruction", "software interrupt", \
0a7de745 A	77	"prefetch abort", "data abort", "irq interrupt", \
0a7de745 A	78	"fast interrupt", "perfmon"
5ba3f43e A	79
	80	/*
	81	* Page-fault trap codes.
	82	*/
0a7de745 A	83	#define T_PF_PROT 0x1 /* protection violation */
	84	#define T_PF_WRITE 0x2 /* write access */
	85	#define T_PF_USER 0x4 /* from user state */
5ba3f43e A	86
	87	#if !defined(ASSEMBLER) && defined(MACH_KERNEL)
	88
	89	#include <arm/thread.h>
	90
0a7de745 A	91	#define GDB_TRAP_INSTR1 0xe7ffdefe
0a7de745 A	92	#define GDB_TRAP_INSTR2 0xe7ffdeff
5ba3f43e	93
0a7de745 A	94	#define ARM_GDB_INSTR1 GDB_TRAP_INSTR1
0a7de745 A	95	#define ARM_GDB_INSTR2 GDB_TRAP_INSTR2
5ba3f43e	96
0a7de745	97	#define IS_ARM_GDB_TRAP(op) \
5ba3f43e A	98	(((op) == ARM_GDB_INSTR1) \|\| ((op) == ARM_GDB_INSTR2))
5ba3f43e A	99
0a7de745 A	100	#define THUMB_GDB_INSTR1 (GDB_TRAP_INSTR1 & 0xFFFF)
0a7de745 A	101	#define THUMB_GDB_INSTR2 (GDB_TRAP_INSTR2 & 0xFFFF)
5ba3f43e	102
0a7de745	103	#define IS_THUMB_GDB_TRAP(op) \
5ba3f43e A	104	(((op) == THUMB_GDB_INSTR1) \|\| ((op) == THUMB_GDB_INSTR2))
	105
	106
0a7de745 A	107	#define ARM_STR 0x04000000 /* STR */
	108	#define ARM_STRH 0x000000B0 /* STRH */
	109	#define ARM_STRH_MASK 0x0E1000F0 /* STRH MASK */
	110	#define ARM_SDX_MASK 0x0C100000 /* SINGLE DATA TRANSFER */
	111	#define ARM_SNGL_DX_MASK 0x0C000000 /* SINGLE DATA TRANSFER MASK */
	112	#define ARM_SDX 0x04000000
5ba3f43e	113
0a7de745 A	114	#define ARM_STM 0x08000000 /* STM */
	115	#define ARM_BDX_MASK 0x0E100000 /* BLOCK DATA TRANSFER */
	116	#define ARM_BLK_MASK 0x0E000000 /* BLOCK DATA TRANSFER */
	117	#define ARM_BDX 0x08000000 /* BLOCK DATA TRANSFER */
5ba3f43e	118
0a7de745 A	119	#define ARM_WRITE_BACK 0x00200000
	120	#define ARM_BASE_REG 0x000F0000
	121	#define ARM_INCREMENT 0x00800000
5ba3f43e	122
0a7de745 A	123	#define ARM_STC 0x0C000000 /* STC */
	124	#define ARM_CDX_MASK ARM_BDX_MASK /* COPROCESSOR DATA TRANSFER */
	125	#define ARM_CBLK_MASK ARM_BLK_MASK
	126	#define ARM_CDX 0x0C000000 /* COPROCESSOR DATA TRANSFER */
5ba3f43e	127
0a7de745 A	128	#define ARM_SWP 0x01000090 /* SWP */
0a7de745 A	129	#define ARM_SWP_MASK 0x0FB00FF0 /* SWP */
5ba3f43e A	130
	131	#define ARM_POST_INDEXING 0x01000000
	132	#define ARM_IMMEDIATE 0x02000000
	133	#define ARM_LSL 0
	134	#define ARM_LSR 1
	135	#define ARM_ASR 2
	136	#define ARM_ROR 3
	137
0a7de745 A	138	#define MCR_MASK 0x0F100F10
	139	#define MCR_CP15 0x0E000F10
	140	#define MCRR_MASK 0x0FF00F00
	141	#define MCRR_CP15 0x0C400F00
5ba3f43e	142
0a7de745 A	143	#define arm_mcr_cp15(op) (((op)&MCR_MASK) == 0x0E000F10)
0a7de745 A	144	#define arm_mcrr_cp15(op) (((op)&0x0FF00F00) == 0x0C400F00)
5ba3f43e	145
0a7de745	146	#define IS_THUMB32(op) ( \
5ba3f43e A	147	(((op) & 0xE000) == 0xE000) && (((op) & 0x1800) != 0x0000))
5ba3f43e A	148
0a7de745 A	149	#define THUMB_LDR_1_MASK 0x8800 /* (1) forms of LD* instructions */
	150	#define THUMB_STR_1_MASK 0xF800 /* (1) forms of ST* instructions */
	151	#define THUMB_STR_2_MASK 0xFE00 /* (2) forms of ST* instructions */
	152	#define THUMB_STR_3_MASK 0xF800 /* (3) forms of ST* instructions */
	153	#define THUMB_PUSH_MASK 0xFE00 /* PUSH instruction */
	154
	155	#define THUMB_LDRH_1 0x8800 /* LDRH(1) */
	156	#define THUMB_STMIA 0xC000 /* STMIA */
	157	#define THUMB_STR_1 0x6000 /* STR(1) */
	158	#define THUMB_STR_2 0x5000 /* STR(2) */
	159	#define THUMB_STR_3 0x9000 /* STR(3) */
	160	#define THUMB_STRB_1 0x7000 /* STRB(1) */
	161	#define THUMB_STRB_2 0x5400 /* STRB(2) */
	162	#define THUMB_STRH_1 0x8000 /* STRH(1) */
	163	#define THUMB_STRH_2 0x5200 /* STRH(2) */
	164	#define THUMB_PUSH 0xB400 /* PUSH */
	165	#define THUMB_LDMIA 0xC800 /* LDMIA */
	166	#define THUMB_POP 0xBC00 /* POP */
5ba3f43e A	167
	168
	169	/*
	170	* Shifts, masks, and other values for load/store multiple decoding; largely needed for
	171	* supporting misaligned accesses.
	172	*/
0a7de745 A	173	#define THUMB_STR_1_BASE_OFFSET 8 /* Offset of the base register field */
	174	#define THUMB_PUSH_EXTRA_OFFSET 8 /* Offset of the "extra" register field */
	175	#define ARM_STM_BASE_OFFSET 16 /* Offset of the base register field */
	176	#define ARM_STM_LOAD_OFFSET 20 /* Offset of the load flag */
	177	#define ARM_STM_WBACK_OFFSET 21 /* Offset of the writeback flag */
	178	#define ARM_STM_INCR_OFFSET 23 /* Offset of the increment flag */
	179	#define ARM_STM_BEFORE_OFFSET 24 /* Offset of the pre-index flag */
	180	#define ARM_REG_LIST_LR_OFFSET 14 /* Offset of LR in the register list */
	181	#define ARM_REG_LIST_PC_OFFSET 15 /* Offset of PC in the register list */
	182
	183	#define THUMB_STR_REG_LIST_MASK 0x000000FF /* Offset of the reg list is 0 */
	184	#define THUMB_STR_1_BASE_MASK 0x00000700
	185	#define THUMB_PUSH_EXTRA_MASK 0x00000100
	186	#define ARM_STM_REG_LIST_MASK 0x0000FFFF /* Offset of the reg list is 0 */
	187	#define ARM_STM_BASE_MASK 0x000F0000
	188	#define ARM_STM_LOAD_MASK 0x00100000
	189	#define ARM_STM_WBACK_MASK 0x00200000
	190	#define ARM_STM_INCR_MASK 0x00800000
	191	#define ARM_STM_BEFORE_MASK 0x01000000
	192	#define ARM_COND_MASK 0xF0000000 /* Mask for the condition code */
	193
	194	#define ARM_COND_UNCOND 0xF0000000 /* Instruction does not support condition codes */
	195
	196	#define ARM_SIMD_MASK0 0xFE000000
	197	#define ARM_SIMD_CODE0 0xF2000000
	198
	199	#define ARM_VFP_MASK0 0x0F000E10
	200	#define ARM_VFP_CODE0 0x0E000A00
	201
	202	#define ARM_SIMD_VFP_MASK0 0x0E000E00
	203	#define ARM_SIMD_VFP_CODE0 0x0C000A00
	204	#define ARM_SIMD_VFP_MASK1 0xFF100000
	205	#define ARM_SIMD_VFP_CODE1 0xF4000000
	206	#define ARM_SIMD_VFP_MASK2 0x0F000E10
	207	#define ARM_SIMD_VFP_CODE2 0x0E000A10
	208	#define ARM_SIMD_VFP_MASK3 0x0FE00E00
	209	#define ARM_SIMD_VFP_CODE3 0x0C400A00
	210
	211	#define IS_ARM_VFP(op) ( \
	212	(((op) & ARM_SIMD_MASK0) == ARM_SIMD_CODE0) \
	213	\|\|(((op) & ARM_VFP_MASK0) == ARM_VFP_CODE0) \
	214	\|\|(((op) & ARM_SIMD_VFP_MASK0) == ARM_SIMD_VFP_CODE0) \
	215	\|\|(((op) & ARM_SIMD_VFP_MASK1) == ARM_SIMD_VFP_CODE1) \
	216	\|\|(((op) & ARM_SIMD_VFP_MASK2) == ARM_SIMD_VFP_CODE2) \
5ba3f43e A	217	\|\| (((op) & ARM_SIMD_VFP_MASK3) == ARM_SIMD_VFP_CODE3))
5ba3f43e A	218
0a7de745 A	219	#define THUMB_SIMD_MASK0 0xEF000000
	220	#define THUMB_SIMD_CODE0 0xEF000000
	221
	222	#define THUMB_VFP_MASK0 0xEF000E10
	223	#define THUMB_VFP_CODE0 0xEE000A00
	224
	225	#define THUMB_SIMD_VFP_MASK0 0xEE000E00
	226	#define THUMB_SIMD_VFP_CODE0 0xEC000A00
	227	#define THUMB_SIMD_VFP_MASK1 0xFF100000
	228	#define THUMB_SIMD_VFP_CODE1 0xF9000000
	229	#define THUMB_SIMD_VFP_MASK2 0xEF000E10
	230	#define THUMB_SIMD_VFP_CODE2 0xEE000A10
	231	#define THUMB_SIMD_VFP_MASK3 0xEFE00E00
	232	#define THUMB_SIMD_VFP_CODE3 0xEC400A00
	233
	234	#define IS_THUMB_VFP(op) ( \
	235	(((op) & THUMB_SIMD_MASK0) == THUMB_SIMD_CODE0 ) \
	236	\|\| (((op) & THUMB_VFP_MASK0) == THUMB_VFP_CODE0 ) \
	237	\|\| (((op) & THUMB_SIMD_VFP_MASK0) == THUMB_SIMD_VFP_CODE0 ) \
	238	\|\| (((op) & THUMB_SIMD_VFP_MASK1) == THUMB_SIMD_VFP_CODE1 ) \
	239	\|\| (((op) & THUMB_SIMD_VFP_MASK2) == THUMB_SIMD_VFP_CODE2 ) \
5ba3f43e A	240	\|\| (((op) & THUMB_SIMD_VFP_MASK3) == THUMB_SIMD_VFP_CODE3))
5ba3f43e A	241
5ba3f43e A	242	extern boolean_t arm_force_fast_fault(ppnum_t, vm_prot_t, int, void *);
	243	extern kern_return_t arm_fast_fault(pmap_t, vm_map_address_t, vm_prot_t, boolean_t);
	244
	245	/*
	246	* Determines if the aborted instruction is read or write operation
	247	*/
0a7de745	248	#define arm_fault_type(op, spsr, vaddr) \
5ba3f43e A	249	(((((op)&ARM_CDX_MASK) == ARM_STC) \|\| \
	250	(((op)&ARM_STRH_MASK) == ARM_STRH) \|\| \
	251	(((op)&ARM_BDX_MASK) == ARM_STM) \|\| \
d9a64523	252	(((op)&ARM_SDX_MASK) == ARM_STR)) ? \
0a7de745 A	253	(VM_PROT_WRITE\|VM_PROT_READ) : (VM_PROT_READ))
	254
	255	#define thumb_fault_type(op, spsr, vaddr) \
5ba3f43e A	256	(((((op)&THUMB_STR_1_MASK) == THUMB_STMIA) \|\| \
	257	(((op)&THUMB_STR_1_MASK) == THUMB_STR_1) \|\| \
	258	(((op)&THUMB_STR_2_MASK) == THUMB_STR_2) \|\| \
	259	(((op)&THUMB_STR_3_MASK) == THUMB_STR_3) \|\| \
	260	(((op)&THUMB_STR_1_MASK) == THUMB_STRB_1) \|\| \
	261	(((op)&THUMB_STR_2_MASK) == THUMB_STRB_2) \|\| \
	262	(((op)&THUMB_STR_1_MASK) == THUMB_STRH_1) \|\| \
	263	(((op)&THUMB_STR_2_MASK) == THUMB_STRH_2) \|\| \
	264	(((op)&THUMB_PUSH_MASK) == THUMB_PUSH)) ? \
0a7de745	265	(VM_PROT_WRITE\|VM_PROT_READ) : (VM_PROT_READ))
5ba3f43e A	266
5ba3f43e A	267	typedef kern_return_t (*perfCallback)(
0a7de745 A	268	int trapno,
	269	struct arm_saved_state *ss,
	270	uintptr_t *,
	271	int);
5ba3f43e	272
0a7de745	273	#endif /* !ASSEMBLER && MACH_KERNEL */
5ba3f43e	274
0a7de745	275	#endif /* _ARM_TRAP_H_ */