#include <mach/arm64/asm.h>
#include <machine/cpu_capabilities.h>
+
#define MMU_I_CLINE 6 // cache line size as 1<<MMU_I_CLINE (64)
/* void sys_icache_invalidate(void *start, size_t length) */
_sys_icache_invalidate:
// see InvalidatePoU_IcacheRegion() in xnu/osfmk/arm64/caches_asm.s
cbz x1, 2f // length > 0 ?
- MOV64 x8, _COMM_PAGE_CPU_CAPABILITIES
- ldr w8, [x8]
and x9, x0, #~((1<<MMU_I_CLINE)-1) // cacheline align address
and x10, x0, #((1<<MMU_I_CLINE)-1) // extend length by alignment
add x10, x1, x10
adds x10, x10, #1 // decrement cacheline counter
b.ne 1b
dsb ish
- tbnz w8, kHasICDSBShift, 2f
isb
2:
ret