x86_64/gen/icacheinval.s

   1 /*
   2  * Copyright (c) 2007 Apple Inc. All rights reserved.
   3  * Copyright (c) 2003-2006 Apple Computer, Inc. All rights reserved.
   4  *
   5  * @APPLE_LICENSE_HEADER_START@
   6  *
   7  * This file contains Original Code and/or Modifications of Original Code
   8  * as defined in and that are subject to the Apple Public Source License
   9  * Version 2.0 (the 'License'). You may not use this file except in
  10  * compliance with the License. Please obtain a copy of the License at
  11  * http://www.opensource.apple.com/apsl/ and read it before using this
  12  * file.
  13  *
  14  * The Original Code and all software distributed under the License are
  15  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  16  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  17  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  19  * Please see the License for the specific language governing rights and
  20  * limitations under the License.
  21  *
  22  * @APPLE_LICENSE_HEADER_END@
  23  */
  24
  25
  26  #include <machine/cpu_capabilities.h>
  27
  28
  29     .text
  30     .align 4, 0x00
  31
  32 /* void sys_icache_invalidate(addr_t start, int length) */
  33
  34         .globl  _sys_icache_invalidate
  35 _sys_icache_invalidate:
  36         // This is a NOP on intel processors, since the intent of the API
  37         // is to make data executable, and Intel L1Is are coherent with L1D.
  38         ret
  39
  40
  41 /* void sys_dcache_flush(addr_t start, int length)  */
  42
  43         .globl  _sys_dcache_flush
  44 _sys_dcache_flush:
  45         testq   %rsi,%rsi               // length 0?
  46         jz      2f                      // yes
  47         mfence                          // ensure previous stores make it to memory
  48         clflush -1(%rdi,%rsi)           // make sure last line is flushed
  49 1:
  50         clflush (%rdi)                  // flush a line
  51         addq    $64,%rdi
  52         subq    $64,%rsi
  53         ja      1b
  54         mfence                          // make sure memory is updated before we return
  55 2:
  56         ret