JavaScriptCore-1097.13.tar.gz

[apple/javascriptcore.git] / assembler / MacroAssemblerX86Common.h

diff --git a/assembler/MacroAssemblerX86Common.h b/assembler/MacroAssemblerX86Common.h
index 449df86c6673790f8a7f6e0b17a699c0ab646c9c..e398dcdad29901b8e495262dee06015a55a6ff38 100644 (file)
--- a/assembler/MacroAssemblerX86Common.h
+++ b/assembler/MacroAssemblerX86Common.h
@@ -26,8 +26,6 @@
 #ifndef MacroAssemblerX86Common_h
 #define MacroAssemblerX86Common_h
 
 #ifndef MacroAssemblerX86Common_h
 #define MacroAssemblerX86Common_h
 

-#include <wtf/Platform.h>
-

 #if ENABLE(ASSEMBLER)
 
 #include "X86Assembler.h"
 #if ENABLE(ASSEMBLER)
 
 #include "X86Assembler.h"


@@ -36,13 +34,22 @@
 namespace JSC {
 
 class MacroAssemblerX86Common : public AbstractMacroAssembler<X86Assembler> {
 namespace JSC {
 
 class MacroAssemblerX86Common : public AbstractMacroAssembler<X86Assembler> {

+protected:
+#if CPU(X86_64)
+    static const X86Registers::RegisterID scratchRegister = X86Registers::r11;
+#endif
+

     static const int DoubleConditionBitInvert = 0x10;
     static const int DoubleConditionBitSpecial = 0x20;
     static const int DoubleConditionBits = DoubleConditionBitInvert | DoubleConditionBitSpecial;
 
 public:
     static const int DoubleConditionBitInvert = 0x10;
     static const int DoubleConditionBitSpecial = 0x20;
     static const int DoubleConditionBits = DoubleConditionBitInvert | DoubleConditionBitSpecial;
 
 public:

+    typedef X86Assembler::FPRegisterID FPRegisterID;
+    typedef X86Assembler::XMMRegisterID XMMRegisterID;
+    
+    static const int MaximumCompactPtrAlignedAddressOffset = 127;

 
 

-    enum Condition {
+    enum RelationalCondition {

         Equal = X86Assembler::ConditionE,
         NotEqual = X86Assembler::ConditionNE,
         Above = X86Assembler::ConditionA,
         Equal = X86Assembler::ConditionE,
         NotEqual = X86Assembler::ConditionNE,
         Above = X86Assembler::ConditionA,


@@ -52,7 +59,10 @@ public:
         GreaterThan = X86Assembler::ConditionG,
         GreaterThanOrEqual = X86Assembler::ConditionGE,
         LessThan = X86Assembler::ConditionL,
         GreaterThan = X86Assembler::ConditionG,
         GreaterThanOrEqual = X86Assembler::ConditionGE,
         LessThan = X86Assembler::ConditionL,

-        LessThanOrEqual = X86Assembler::ConditionLE,
+        LessThanOrEqual = X86Assembler::ConditionLE
+    };
+
+    enum ResultCondition {

         Overflow = X86Assembler::ConditionO,
         Signed = X86Assembler::ConditionS,
         Zero = X86Assembler::ConditionE,
         Overflow = X86Assembler::ConditionO,
         Signed = X86Assembler::ConditionS,
         Zero = X86Assembler::ConditionE,


@@ -81,10 +91,17 @@ public:
 
     static const RegisterID stackPointerRegister = X86Registers::esp;
 
 
     static const RegisterID stackPointerRegister = X86Registers::esp;
 

+#if ENABLE(JIT_CONSTANT_BLINDING)
+    static bool shouldBlindForSpecificArch(uint32_t value) { return value >= 0x00ffffff; }
+#if CPU(X86_64)
+    static bool shouldBlindForSpecificArch(uintptr_t value) { return value >= 0x00ffffff; }
+#endif
+#endif
+

     // Integer arithmetic operations:
     //
     // Operations are typically two operand - operation(source, srcDst)
     // Integer arithmetic operations:
     //
     // Operations are typically two operand - operation(source, srcDst)

-    // For many operations the source may be an Imm32, the srcDst operand
+    // For many operations the source may be an TrustedImm32, the srcDst operand

     // may often be a memory location (explictly described using an Address
     // object).
 
     // may often be a memory location (explictly described using an Address
     // object).
 


@@ -93,12 +110,12 @@ public:
         m_assembler.addl_rr(src, dest);
     }
 
         m_assembler.addl_rr(src, dest);
     }
 

-    void add32(Imm32 imm, Address address)
+    void add32(TrustedImm32 imm, Address address)

     {
         m_assembler.addl_im(imm.m_value, address.offset, address.base);
     }
 
     {
         m_assembler.addl_im(imm.m_value, address.offset, address.base);
     }
 

-    void add32(Imm32 imm, RegisterID dest)
+    void add32(TrustedImm32 imm, RegisterID dest)

     {
         m_assembler.addl_ir(imm.m_value, dest);
     }
     {
         m_assembler.addl_ir(imm.m_value, dest);
     }


@@ -112,13 +129,18 @@ public:
     {
         m_assembler.addl_rm(src, dest.offset, dest.base);
     }
     {
         m_assembler.addl_rm(src, dest.offset, dest.base);
     }

+
+    void add32(TrustedImm32 imm, RegisterID src, RegisterID dest)
+    {
+        m_assembler.leal_mr(imm.m_value, src, dest);
+    }

     
     void and32(RegisterID src, RegisterID dest)
     {
         m_assembler.andl_rr(src, dest);
     }
 
     
     void and32(RegisterID src, RegisterID dest)
     {
         m_assembler.andl_rr(src, dest);
     }
 

-    void and32(Imm32 imm, RegisterID dest)
+    void and32(TrustedImm32 imm, RegisterID dest)

     {
         m_assembler.andl_ir(imm.m_value, dest);
     }
     {
         m_assembler.andl_ir(imm.m_value, dest);
     }


@@ -133,36 +155,64 @@ public:
         m_assembler.andl_mr(src.offset, src.base, dest);
     }
 
         m_assembler.andl_mr(src.offset, src.base, dest);
     }
 

-    void and32(Imm32 imm, Address address)
+    void and32(TrustedImm32 imm, Address address)

     {
         m_assembler.andl_im(imm.m_value, address.offset, address.base);
     }
 
     {
         m_assembler.andl_im(imm.m_value, address.offset, address.base);
     }
 

-    void lshift32(Imm32 imm, RegisterID dest)
+    void and32(RegisterID op1, RegisterID op2, RegisterID dest)

     {
     {

-        m_assembler.shll_i8r(imm.m_value, dest);
+        if (op1 == op2)
+            zeroExtend32ToPtr(op1, dest);
+        else if (op1 == dest)
+            and32(op2, dest);
+        else {
+            move(op2, dest);
+            and32(op1, dest);
+        }

     }
     }

-    
+
+    void and32(TrustedImm32 imm, RegisterID src, RegisterID dest)
+    {
+        move(src, dest);
+        and32(imm, dest);
+    }
+

     void lshift32(RegisterID shift_amount, RegisterID dest)
     {
     void lshift32(RegisterID shift_amount, RegisterID dest)
     {

-        // On x86 we can only shift by ecx; if asked to shift by another register we'll
-        // need rejig the shift amount into ecx first, and restore the registers afterwards.
-        if (shift_amount != X86Registers::ecx) {
-            swap(shift_amount, X86Registers::ecx);
+        ASSERT(shift_amount != dest);

 
 

-            // E.g. transform "shll %eax, %eax" -> "xchgl %eax, %ecx; shll %ecx, %ecx; xchgl %eax, %ecx"
-            if (dest == shift_amount)
-                m_assembler.shll_CLr(X86Registers::ecx);
-            // E.g. transform "shll %eax, %ecx" -> "xchgl %eax, %ecx; shll %ecx, %eax; xchgl %eax, %ecx"
-            else if (dest == X86Registers::ecx)
-                m_assembler.shll_CLr(shift_amount);
-            // E.g. transform "shll %eax, %ebx" -> "xchgl %eax, %ecx; shll %ecx, %ebx; xchgl %eax, %ecx"
-            else
-                m_assembler.shll_CLr(dest);
-        
-            swap(shift_amount, X86Registers::ecx);
-        } else
+        if (shift_amount == X86Registers::ecx)

             m_assembler.shll_CLr(dest);
             m_assembler.shll_CLr(dest);

+        else {
+            // On x86 we can only shift by ecx; if asked to shift by another register we'll
+            // need rejig the shift amount into ecx first, and restore the registers afterwards.
+            // If we dest is ecx, then shift the swapped register!
+            swap(shift_amount, X86Registers::ecx);
+            m_assembler.shll_CLr(dest == X86Registers::ecx ? shift_amount : dest);
+            swap(shift_amount, X86Registers::ecx);
+        }
+    }
+
+    void lshift32(RegisterID src, RegisterID shift_amount, RegisterID dest)
+    {
+        ASSERT(shift_amount != dest);
+
+        if (src != dest)
+            move(src, dest);
+        lshift32(shift_amount, dest);
+    }
+
+    void lshift32(TrustedImm32 imm, RegisterID dest)
+    {
+        m_assembler.shll_i8r(imm.m_value, dest);
+    }
+    
+    void lshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
+    {
+        if (src != dest)
+            move(src, dest);
+        lshift32(imm, dest);

     }
     
     void mul32(RegisterID src, RegisterID dest)
     }
     
     void mul32(RegisterID src, RegisterID dest)


@@ -175,7 +225,7 @@ public:
         m_assembler.imull_mr(src.offset, src.base, dest);
     }
     
         m_assembler.imull_mr(src.offset, src.base, dest);
     }
     

-    void mul32(Imm32 imm, RegisterID src, RegisterID dest)
+    void mul32(TrustedImm32 imm, RegisterID src, RegisterID dest)

     {
         m_assembler.imull_i32r(src, imm.m_value, dest);
     }
     {
         m_assembler.imull_i32r(src, imm.m_value, dest);
     }


@@ -190,22 +240,12 @@ public:
         m_assembler.negl_m(srcDest.offset, srcDest.base);
     }
 
         m_assembler.negl_m(srcDest.offset, srcDest.base);
     }
 

-    void not32(RegisterID srcDest)
-    {
-        m_assembler.notl_r(srcDest);
-    }
-
-    void not32(Address srcDest)
-    {
-        m_assembler.notl_m(srcDest.offset, srcDest.base);
-    }
-    

     void or32(RegisterID src, RegisterID dest)
     {
         m_assembler.orl_rr(src, dest);
     }
 
     void or32(RegisterID src, RegisterID dest)
     {
         m_assembler.orl_rr(src, dest);
     }
 

-    void or32(Imm32 imm, RegisterID dest)
+    void or32(TrustedImm32 imm, RegisterID dest)

     {
         m_assembler.orl_ir(imm.m_value, dest);
     }
     {
         m_assembler.orl_ir(imm.m_value, dest);
     }


@@ -220,49 +260,114 @@ public:
         m_assembler.orl_mr(src.offset, src.base, dest);
     }
 
         m_assembler.orl_mr(src.offset, src.base, dest);
     }
 

-    void or32(Imm32 imm, Address address)
+    void or32(TrustedImm32 imm, Address address)

     {
         m_assembler.orl_im(imm.m_value, address.offset, address.base);
     }
 
     {
         m_assembler.orl_im(imm.m_value, address.offset, address.base);
     }
 

+    void or32(RegisterID op1, RegisterID op2, RegisterID dest)
+    {
+        if (op1 == op2)
+            zeroExtend32ToPtr(op1, dest);
+        else if (op1 == dest)
+            or32(op2, dest);
+        else {
+            move(op2, dest);
+            or32(op1, dest);
+        }
+    }
+
+    void or32(TrustedImm32 imm, RegisterID src, RegisterID dest)
+    {
+        move(src, dest);
+        or32(imm, dest);
+    }
+

     void rshift32(RegisterID shift_amount, RegisterID dest)
     {
     void rshift32(RegisterID shift_amount, RegisterID dest)
     {

-        // On x86 we can only shift by ecx; if asked to shift by another register we'll
-        // need rejig the shift amount into ecx first, and restore the registers afterwards.
-        if (shift_amount != X86Registers::ecx) {
-            swap(shift_amount, X86Registers::ecx);
+        ASSERT(shift_amount != dest);

 
 

-            // E.g. transform "shll %eax, %eax" -> "xchgl %eax, %ecx; shll %ecx, %ecx; xchgl %eax, %ecx"
-            if (dest == shift_amount)
-                m_assembler.sarl_CLr(X86Registers::ecx);
-            // E.g. transform "shll %eax, %ecx" -> "xchgl %eax, %ecx; shll %ecx, %eax; xchgl %eax, %ecx"
-            else if (dest == X86Registers::ecx)
-                m_assembler.sarl_CLr(shift_amount);
-            // E.g. transform "shll %eax, %ebx" -> "xchgl %eax, %ecx; shll %ecx, %ebx; xchgl %eax, %ecx"
-            else
-                m_assembler.sarl_CLr(dest);
-        
-            swap(shift_amount, X86Registers::ecx);
-        } else
+        if (shift_amount == X86Registers::ecx)

             m_assembler.sarl_CLr(dest);
             m_assembler.sarl_CLr(dest);

+        else {
+            // On x86 we can only shift by ecx; if asked to shift by another register we'll
+            // need rejig the shift amount into ecx first, and restore the registers afterwards.
+            // If we dest is ecx, then shift the swapped register!
+            swap(shift_amount, X86Registers::ecx);
+            m_assembler.sarl_CLr(dest == X86Registers::ecx ? shift_amount : dest);
+            swap(shift_amount, X86Registers::ecx);
+        }
+    }
+
+    void rshift32(RegisterID src, RegisterID shift_amount, RegisterID dest)
+    {
+        ASSERT(shift_amount != dest);
+
+        if (src != dest)
+            move(src, dest);
+        rshift32(shift_amount, dest);

     }
 
     }
 

-    void rshift32(Imm32 imm, RegisterID dest)
+    void rshift32(TrustedImm32 imm, RegisterID dest)

     {
         m_assembler.sarl_i8r(imm.m_value, dest);
     }
     {
         m_assembler.sarl_i8r(imm.m_value, dest);
     }

+    
+    void rshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
+    {
+        if (src != dest)
+            move(src, dest);
+        rshift32(imm, dest);
+    }
+    
+    void urshift32(RegisterID shift_amount, RegisterID dest)
+    {
+        ASSERT(shift_amount != dest);
+
+        if (shift_amount == X86Registers::ecx)
+            m_assembler.shrl_CLr(dest);
+        else {
+            // On x86 we can only shift by ecx; if asked to shift by another register we'll
+            // need rejig the shift amount into ecx first, and restore the registers afterwards.
+            // If we dest is ecx, then shift the swapped register!
+            swap(shift_amount, X86Registers::ecx);
+            m_assembler.shrl_CLr(dest == X86Registers::ecx ? shift_amount : dest);
+            swap(shift_amount, X86Registers::ecx);
+        }
+    }

 
 

+    void urshift32(RegisterID src, RegisterID shift_amount, RegisterID dest)
+    {
+        ASSERT(shift_amount != dest);
+
+        if (src != dest)
+            move(src, dest);
+        urshift32(shift_amount, dest);
+    }
+
+    void urshift32(TrustedImm32 imm, RegisterID dest)
+    {
+        m_assembler.shrl_i8r(imm.m_value, dest);
+    }
+    
+    void urshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
+    {
+        if (src != dest)
+            move(src, dest);
+        urshift32(imm, dest);
+    }
+    

     void sub32(RegisterID src, RegisterID dest)
     {
         m_assembler.subl_rr(src, dest);
     }
     
     void sub32(RegisterID src, RegisterID dest)
     {
         m_assembler.subl_rr(src, dest);
     }
     

-    void sub32(Imm32 imm, RegisterID dest)
+    void sub32(TrustedImm32 imm, RegisterID dest)

     {
         m_assembler.subl_ir(imm.m_value, dest);
     }
     
     {
         m_assembler.subl_ir(imm.m_value, dest);
     }
     

-    void sub32(Imm32 imm, Address address)
+    void sub32(TrustedImm32 imm, Address address)

     {
         m_assembler.subl_im(imm.m_value, address.offset, address.base);
     }
     {
         m_assembler.subl_im(imm.m_value, address.offset, address.base);
     }


@@ -277,19 +382,24 @@ public:
         m_assembler.subl_rm(src, dest.offset, dest.base);
     }
 
         m_assembler.subl_rm(src, dest.offset, dest.base);
     }
 

-

     void xor32(RegisterID src, RegisterID dest)
     {
         m_assembler.xorl_rr(src, dest);
     }
 
     void xor32(RegisterID src, RegisterID dest)
     {
         m_assembler.xorl_rr(src, dest);
     }
 

-    void xor32(Imm32 imm, Address dest)
+    void xor32(TrustedImm32 imm, Address dest)

     {
     {

-        m_assembler.xorl_im(imm.m_value, dest.offset, dest.base);
+        if (imm.m_value == -1)
+            m_assembler.notl_m(dest.offset, dest.base);
+        else
+            m_assembler.xorl_im(imm.m_value, dest.offset, dest.base);

     }
 
     }
 

-    void xor32(Imm32 imm, RegisterID dest)
+    void xor32(TrustedImm32 imm, RegisterID dest)

     {
     {

+        if (imm.m_value == -1)
+        m_assembler.notl_r(dest);
+        else

         m_assembler.xorl_ir(imm.m_value, dest);
     }
 
         m_assembler.xorl_ir(imm.m_value, dest);
     }
 


@@ -303,11 +413,50 @@ public:
         m_assembler.xorl_mr(src.offset, src.base, dest);
     }
     
         m_assembler.xorl_mr(src.offset, src.base, dest);
     }
     

+    void xor32(RegisterID op1, RegisterID op2, RegisterID dest)
+    {
+        if (op1 == op2)
+            move(TrustedImm32(0), dest);
+        else if (op1 == dest)
+            xor32(op2, dest);
+        else {
+            move(op2, dest);
+            xor32(op1, dest);
+        }
+    }
+
+    void xor32(TrustedImm32 imm, RegisterID src, RegisterID dest)
+    {
+        move(src, dest);
+        xor32(imm, dest);
+    }
+
+    void sqrtDouble(FPRegisterID src, FPRegisterID dst)
+    {
+        m_assembler.sqrtsd_rr(src, dst);
+    }
+
+    void absDouble(FPRegisterID src, FPRegisterID dst)
+    {
+        ASSERT(src != dst);
+        static const double negativeZeroConstant = -0.0;
+        loadDouble(&negativeZeroConstant, dst);
+        m_assembler.andnpd_rr(src, dst);
+    }
+
+    void negateDouble(FPRegisterID src, FPRegisterID dst)
+    {
+        ASSERT(src != dst);
+        static const double negativeZeroConstant = -0.0;
+        loadDouble(&negativeZeroConstant, dst);
+        m_assembler.xorpd_rr(src, dst);
+    }
+

 
     // Memory access operations:
     //
     // Loads are of the form load(address, destination) and stores of the form
 
     // Memory access operations:
     //
     // Loads are of the form load(address, destination) and stores of the form

-    // store(source, address).  The source for a store may be an Imm32.  Address
+    // store(source, address).  The source for a store may be an TrustedImm32.  Address

     // operand objects to loads and store will be implicitly constructed if a
     // register is passed.
 
     // operand objects to loads and store will be implicitly constructed if a
     // register is passed.
 


@@ -326,16 +475,75 @@ public:
         load32(address, dest);
     }
 
         load32(address, dest);
     }
 

+    void load16Unaligned(BaseIndex address, RegisterID dest)
+    {
+        load16(address, dest);
+    }
+

     DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest)
     {
         m_assembler.movl_mr_disp32(address.offset, address.base, dest);
         return DataLabel32(this);
     }
     DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest)
     {
         m_assembler.movl_mr_disp32(address.offset, address.base, dest);
         return DataLabel32(this);
     }

+    
+    DataLabelCompact load32WithCompactAddressOffsetPatch(Address address, RegisterID dest)
+    {
+        m_assembler.movl_mr_disp8(address.offset, address.base, dest);
+        return DataLabelCompact(this);
+    }
+    
+    static void repatchCompact(CodeLocationDataLabelCompact dataLabelCompact, int32_t value)
+    {
+        ASSERT(value >= 0);
+        ASSERT(value < MaximumCompactPtrAlignedAddressOffset);
+        AssemblerType_T::repatchCompact(dataLabelCompact.dataLocation(), value);
+    }
+    
+    DataLabelCompact loadCompactWithAddressOffsetPatch(Address address, RegisterID dest)
+    {
+        m_assembler.movl_mr_disp8(address.offset, address.base, dest);
+        return DataLabelCompact(this);
+    }

 
 

+    void load8(BaseIndex address, RegisterID dest)
+    {
+        m_assembler.movzbl_mr(address.offset, address.base, address.index, address.scale, dest);
+    }
+
+    void load8(ImplicitAddress address, RegisterID dest)
+    {
+        m_assembler.movzbl_mr(address.offset, address.base, dest);
+    }
+    
+    void load8Signed(BaseIndex address, RegisterID dest)
+    {
+        m_assembler.movsbl_mr(address.offset, address.base, address.index, address.scale, dest);
+    }
+
+    void load8Signed(ImplicitAddress address, RegisterID dest)
+    {
+        m_assembler.movsbl_mr(address.offset, address.base, dest);
+    }
+    

     void load16(BaseIndex address, RegisterID dest)
     {
         m_assembler.movzwl_mr(address.offset, address.base, address.index, address.scale, dest);
     }
     void load16(BaseIndex address, RegisterID dest)
     {
         m_assembler.movzwl_mr(address.offset, address.base, address.index, address.scale, dest);
     }

+    
+    void load16(Address address, RegisterID dest)
+    {
+        m_assembler.movzwl_mr(address.offset, address.base, dest);
+    }
+
+    void load16Signed(BaseIndex address, RegisterID dest)
+    {
+        m_assembler.movswl_mr(address.offset, address.base, address.index, address.scale, dest);
+    }
+    
+    void load16Signed(Address address, RegisterID dest)
+    {
+        m_assembler.movswl_mr(address.offset, address.base, dest);
+    }

 
     DataLabel32 store32WithAddressOffsetPatch(RegisterID src, Address address)
     {
 
     DataLabel32 store32WithAddressOffsetPatch(RegisterID src, Address address)
     {


@@ -353,27 +561,151 @@ public:
         m_assembler.movl_rm(src, address.offset, address.base, address.index, address.scale);
     }
 
         m_assembler.movl_rm(src, address.offset, address.base, address.index, address.scale);
     }
 

-    void store32(Imm32 imm, ImplicitAddress address)
+    void store32(TrustedImm32 imm, ImplicitAddress address)

     {
         m_assembler.movl_i32m(imm.m_value, address.offset, address.base);
     }
     {
         m_assembler.movl_i32m(imm.m_value, address.offset, address.base);
     }

+    
+    void store32(TrustedImm32 imm, BaseIndex address)
+    {
+        m_assembler.movl_i32m(imm.m_value, address.offset, address.base, address.index, address.scale);
+    }
+
+    void store8(TrustedImm32 imm, Address address)
+    {
+        ASSERT(-128 <= imm.m_value && imm.m_value < 128);
+        m_assembler.movb_i8m(imm.m_value, address.offset, address.base);
+    }
+
+    void store8(TrustedImm32 imm, BaseIndex address)
+    {
+        ASSERT(-128 <= imm.m_value && imm.m_value < 128);
+        m_assembler.movb_i8m(imm.m_value, address.offset, address.base, address.index, address.scale);
+    }
+    
+    void store8(RegisterID src, BaseIndex address)
+    {
+#if CPU(X86)
+        // On 32-bit x86 we can only store from the first 4 registers;
+        // esp..edi are mapped to the 'h' registers!
+        if (src >= 4) {
+            // Pick a temporary register.
+            RegisterID temp;
+            if (address.base != X86Registers::eax && address.index != X86Registers::eax)
+                temp = X86Registers::eax;
+            else if (address.base != X86Registers::ebx && address.index != X86Registers::ebx)
+                temp = X86Registers::ebx;
+            else {
+                ASSERT(address.base != X86Registers::ecx && address.index != X86Registers::ecx);
+                temp = X86Registers::ecx;
+            }
+
+            // Swap to the temporary register to perform the store.
+            swap(src, temp);
+            m_assembler.movb_rm(temp, address.offset, address.base, address.index, address.scale);
+            swap(src, temp);
+            return;
+        }
+#endif
+        m_assembler.movb_rm(src, address.offset, address.base, address.index, address.scale);
+    }
+
+    void store16(RegisterID src, BaseIndex address)
+    {
+#if CPU(X86)
+        // On 32-bit x86 we can only store from the first 4 registers;
+        // esp..edi are mapped to the 'h' registers!
+        if (src >= 4) {
+            // Pick a temporary register.
+            RegisterID temp;
+            if (address.base != X86Registers::eax && address.index != X86Registers::eax)
+                temp = X86Registers::eax;
+            else if (address.base != X86Registers::ebx && address.index != X86Registers::ebx)
+                temp = X86Registers::ebx;
+            else {
+                ASSERT(address.base != X86Registers::ecx && address.index != X86Registers::ecx);
+                temp = X86Registers::ecx;
+            }
+            
+            // Swap to the temporary register to perform the store.
+            swap(src, temp);
+            m_assembler.movw_rm(temp, address.offset, address.base, address.index, address.scale);
+            swap(src, temp);
+            return;
+        }
+#endif
+        m_assembler.movw_rm(src, address.offset, address.base, address.index, address.scale);
+    }

 
 
     // Floating-point operation:
     //
     // Presently only supports SSE, not x87 floating point.
 
 
 
     // Floating-point operation:
     //
     // Presently only supports SSE, not x87 floating point.
 

+    void moveDouble(FPRegisterID src, FPRegisterID dest)
+    {
+        ASSERT(isSSE2Present());
+        if (src != dest)
+            m_assembler.movsd_rr(src, dest);
+    }
+
+    void loadDouble(const void* address, FPRegisterID dest)
+    {
+#if CPU(X86)
+        ASSERT(isSSE2Present());
+        m_assembler.movsd_mr(address, dest);
+#else
+        move(TrustedImmPtr(address), scratchRegister);
+        loadDouble(scratchRegister, dest);
+#endif
+    }
+

     void loadDouble(ImplicitAddress address, FPRegisterID dest)
     {
         ASSERT(isSSE2Present());
         m_assembler.movsd_mr(address.offset, address.base, dest);
     }
     void loadDouble(ImplicitAddress address, FPRegisterID dest)
     {
         ASSERT(isSSE2Present());
         m_assembler.movsd_mr(address.offset, address.base, dest);
     }

+    
+    void loadDouble(BaseIndex address, FPRegisterID dest)
+    {
+        ASSERT(isSSE2Present());
+        m_assembler.movsd_mr(address.offset, address.base, address.index, address.scale, dest);
+    }
+    void loadFloat(BaseIndex address, FPRegisterID dest)
+    {
+        ASSERT(isSSE2Present());
+        m_assembler.movss_mr(address.offset, address.base, address.index, address.scale, dest);
+    }

 
     void storeDouble(FPRegisterID src, ImplicitAddress address)
     {
         ASSERT(isSSE2Present());
         m_assembler.movsd_rm(src, address.offset, address.base);
     }
 
     void storeDouble(FPRegisterID src, ImplicitAddress address)
     {
         ASSERT(isSSE2Present());
         m_assembler.movsd_rm(src, address.offset, address.base);
     }

+    
+    void storeDouble(FPRegisterID src, BaseIndex address)
+    {
+        ASSERT(isSSE2Present());
+        m_assembler.movsd_rm(src, address.offset, address.base, address.index, address.scale);
+    }
+    
+    void storeFloat(FPRegisterID src, BaseIndex address)
+    {
+        ASSERT(isSSE2Present());
+        m_assembler.movss_rm(src, address.offset, address.base, address.index, address.scale);
+    }
+    
+    void convertDoubleToFloat(FPRegisterID src, FPRegisterID dst)
+    {
+        ASSERT(isSSE2Present());
+        m_assembler.cvtsd2ss_rr(src, dst);
+    }
+
+    void convertFloatToDouble(FPRegisterID src, FPRegisterID dst)
+    {
+        ASSERT(isSSE2Present());
+        m_assembler.cvtss2sd_rr(src, dst);
+    }

 
     void addDouble(FPRegisterID src, FPRegisterID dest)
     {
 
     void addDouble(FPRegisterID src, FPRegisterID dest)
     {


@@ -381,6 +713,17 @@ public:
         m_assembler.addsd_rr(src, dest);
     }
 
         m_assembler.addsd_rr(src, dest);
     }
 

+    void addDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+    {
+        ASSERT(isSSE2Present());
+        if (op1 == dest)
+            addDouble(op2, dest);
+        else {
+            moveDouble(op2, dest);
+            addDouble(op1, dest);
+        }
+    }
+

     void addDouble(Address src, FPRegisterID dest)
     {
         ASSERT(isSSE2Present());
     void addDouble(Address src, FPRegisterID dest)
     {
         ASSERT(isSSE2Present());


@@ -393,6 +736,15 @@ public:
         m_assembler.divsd_rr(src, dest);
     }
 
         m_assembler.divsd_rr(src, dest);
     }
 

+    void divDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+    {
+        // B := A / B is invalid.
+        ASSERT(op1 == dest || op2 != dest);
+
+        moveDouble(op1, dest);
+        divDouble(op2, dest);
+    }
+

     void divDouble(Address src, FPRegisterID dest)
     {
         ASSERT(isSSE2Present());
     void divDouble(Address src, FPRegisterID dest)
     {
         ASSERT(isSSE2Present());


@@ -405,6 +757,15 @@ public:
         m_assembler.subsd_rr(src, dest);
     }
 
         m_assembler.subsd_rr(src, dest);
     }
 

+    void subDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+    {
+        // B := A - B is invalid.
+        ASSERT(op1 == dest || op2 != dest);
+
+        moveDouble(op1, dest);
+        subDouble(op2, dest);
+    }
+

     void subDouble(Address src, FPRegisterID dest)
     {
         ASSERT(isSSE2Present());
     void subDouble(Address src, FPRegisterID dest)
     {
         ASSERT(isSSE2Present());


@@ -417,6 +778,17 @@ public:
         m_assembler.mulsd_rr(src, dest);
     }
 
         m_assembler.mulsd_rr(src, dest);
     }
 

+    void mulDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+    {
+        ASSERT(isSSE2Present());
+        if (op1 == dest)
+            mulDouble(op2, dest);
+        else {
+            moveDouble(op2, dest);
+            mulDouble(op1, dest);
+        }
+    }
+

     void mulDouble(Address src, FPRegisterID dest)
     {
         ASSERT(isSSE2Present());
     void mulDouble(Address src, FPRegisterID dest)
     {
         ASSERT(isSSE2Present());


@@ -466,13 +838,35 @@ public:
     // If the result is not representable as a 32 bit value, branch.
     // May also branch for some values that are representable in 32 bits
     // (specifically, in this case, INT_MIN).
     // If the result is not representable as a 32 bit value, branch.
     // May also branch for some values that are representable in 32 bits
     // (specifically, in this case, INT_MIN).

-    Jump branchTruncateDoubleToInt32(FPRegisterID src, RegisterID dest)
+    enum BranchTruncateType { BranchIfTruncateFailed, BranchIfTruncateSuccessful };
+    Jump branchTruncateDoubleToInt32(FPRegisterID src, RegisterID dest, BranchTruncateType branchType = BranchIfTruncateFailed)

     {
         ASSERT(isSSE2Present());
         m_assembler.cvttsd2si_rr(src, dest);
     {
         ASSERT(isSSE2Present());
         m_assembler.cvttsd2si_rr(src, dest);

-        return branch32(Equal, dest, Imm32(0x80000000));
+        return branch32(branchType ? NotEqual : Equal, dest, TrustedImm32(0x80000000));

     }
 
     }
 

+    Jump branchTruncateDoubleToUint32(FPRegisterID src, RegisterID dest, BranchTruncateType branchType = BranchIfTruncateFailed)
+    {
+        ASSERT(isSSE2Present());
+        m_assembler.cvttsd2si_rr(src, dest);
+        return branch32(branchType ? GreaterThanOrEqual : LessThan, dest, TrustedImm32(0));
+    }
+
+    void truncateDoubleToInt32(FPRegisterID src, RegisterID dest)
+    {
+        ASSERT(isSSE2Present());
+        m_assembler.cvttsd2si_rr(src, dest);
+    }
+    
+#if CPU(X86_64)
+    void truncateDoubleToUint32(FPRegisterID src, RegisterID dest)
+    {
+        ASSERT(isSSE2Present());
+        m_assembler.cvttsd2siq_rr(src, dest);
+    }
+#endif
+    

     // Convert 'src' to an integer, and places the resulting 'dest'.
     // If the result is not representable as a 32 bit value, branch.
     // May also branch for some values that are representable in 32 bits
     // Convert 'src' to an integer, and places the resulting 'dest'.
     // If the result is not representable as a 32 bit value, branch.
     // May also branch for some values that are representable in 32 bits


@@ -492,12 +886,49 @@ public:
         failureCases.append(m_assembler.jne());
     }
 
         failureCases.append(m_assembler.jne());
     }
 

-    void zeroDouble(FPRegisterID srcDest)
+    Jump branchDoubleNonZero(FPRegisterID reg, FPRegisterID scratch)

     {
         ASSERT(isSSE2Present());
     {
         ASSERT(isSSE2Present());

-        m_assembler.xorpd_rr(srcDest, srcDest);
+        m_assembler.xorpd_rr(scratch, scratch);
+        return branchDouble(DoubleNotEqual, reg, scratch);

     }
 
     }
 

+    Jump branchDoubleZeroOrNaN(FPRegisterID reg, FPRegisterID scratch)
+    {
+        ASSERT(isSSE2Present());
+        m_assembler.xorpd_rr(scratch, scratch);
+        return branchDouble(DoubleEqualOrUnordered, reg, scratch);
+    }
+
+    void lshiftPacked(TrustedImm32 imm, XMMRegisterID reg)
+    {
+        ASSERT(isSSE2Present());
+        m_assembler.psllq_i8r(imm.m_value, reg);
+    }
+
+    void rshiftPacked(TrustedImm32 imm, XMMRegisterID reg)
+    {
+        ASSERT(isSSE2Present());
+        m_assembler.psrlq_i8r(imm.m_value, reg);
+    }
+
+    void orPacked(XMMRegisterID src, XMMRegisterID dst)
+    {
+        ASSERT(isSSE2Present());
+        m_assembler.por_rr(src, dst);
+    }
+
+    void moveInt32ToPacked(RegisterID src, XMMRegisterID dst)
+    {
+        ASSERT(isSSE2Present());
+        m_assembler.movd_rr(src, dst);
+    }
+
+    void movePackedToInt32(XMMRegisterID src, RegisterID dst)
+    {
+        ASSERT(isSSE2Present());
+        m_assembler.movd_rr(src, dst);
+    }

 
     // Stack manipulation operations:
     //
 
     // Stack manipulation operations:
     //


@@ -522,7 +953,7 @@ public:
         m_assembler.push_m(address.offset, address.base);
     }
 
         m_assembler.push_m(address.offset, address.base);
     }
 

-    void push(Imm32 imm)
+    void push(TrustedImm32 imm)

     {
         m_assembler.push_i32(imm.m_value);
     }
     {
         m_assembler.push_i32(imm.m_value);
     }


@@ -532,9 +963,9 @@ public:
     //
     // Move values in registers.
 
     //
     // Move values in registers.
 

-    void move(Imm32 imm, RegisterID dest)
+    void move(TrustedImm32 imm, RegisterID dest)

     {
     {

-        // Note: on 64-bit the Imm32 value is zero extended into the register, it
+        // Note: on 64-bit the TrustedImm32 value is zero extended into the register, it

         // may be useful to have a separate version that sign extends the value?
         if (!imm.m_value)
             m_assembler.xorl_rr(dest, dest);
         // may be useful to have a separate version that sign extends the value?
         if (!imm.m_value)
             m_assembler.xorl_rr(dest, dest);


@@ -551,7 +982,7 @@ public:
             m_assembler.movq_rr(src, dest);
     }
 
             m_assembler.movq_rr(src, dest);
     }
 

-    void move(ImmPtr imm, RegisterID dest)
+    void move(TrustedImmPtr imm, RegisterID dest)

     {
         m_assembler.movq_i64r(imm.asIntptr(), dest);
     }
     {
         m_assembler.movq_i64r(imm.asIntptr(), dest);
     }


@@ -578,7 +1009,7 @@ public:
             m_assembler.movl_rr(src, dest);
     }
 
             m_assembler.movl_rr(src, dest);
     }
 

-    void move(ImmPtr imm, RegisterID dest)
+    void move(TrustedImmPtr imm, RegisterID dest)

     {
         m_assembler.movl_i32r(imm.asIntptr(), dest);
     }
     {
         m_assembler.movl_i32r(imm.asIntptr(), dest);
     }


@@ -613,20 +1044,26 @@ public:
     // used (representing the names 'below' and 'above').
     //
     // Operands to the comparision are provided in the expected order, e.g.
     // used (representing the names 'below' and 'above').
     //
     // Operands to the comparision are provided in the expected order, e.g.

-    // jle32(reg1, Imm32(5)) will branch if the value held in reg1, when
+    // jle32(reg1, TrustedImm32(5)) will branch if the value held in reg1, when

     // treated as a signed 32bit value, is less than or equal to 5.
     //
     // jz and jnz test whether the first operand is equal to zero, and take
     // an optional second operand of a mask under which to perform the test.
 
 public:
     // treated as a signed 32bit value, is less than or equal to 5.
     //
     // jz and jnz test whether the first operand is equal to zero, and take
     // an optional second operand of a mask under which to perform the test.
 
 public:

-    Jump branch32(Condition cond, RegisterID left, RegisterID right)
+    Jump branch8(RelationalCondition cond, Address left, TrustedImm32 right)
+    {
+        m_assembler.cmpb_im(right.m_value, left.offset, left.base);
+        return Jump(m_assembler.jCC(x86Condition(cond)));
+    }
+
+    Jump branch32(RelationalCondition cond, RegisterID left, RegisterID right)

     {
         m_assembler.cmpl_rr(right, left);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 
     {
         m_assembler.cmpl_rr(right, left);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 

-    Jump branch32(Condition cond, RegisterID left, Imm32 right)
+    Jump branch32(RelationalCondition cond, RegisterID left, TrustedImm32 right)

     {
         if (((cond == Equal) || (cond == NotEqual)) && !right.m_value)
             m_assembler.testl_rr(left, left);
     {
         if (((cond == Equal) || (cond == NotEqual)) && !right.m_value)
             m_assembler.testl_rr(left, left);


@@ -635,72 +1072,53 @@ public:
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
     
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
     

-    Jump branch32(Condition cond, RegisterID left, Address right)
+    Jump branch32(RelationalCondition cond, RegisterID left, Address right)

     {
         m_assembler.cmpl_mr(right.offset, right.base, left);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
     
     {
         m_assembler.cmpl_mr(right.offset, right.base, left);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
     

-    Jump branch32(Condition cond, Address left, RegisterID right)
+    Jump branch32(RelationalCondition cond, Address left, RegisterID right)

     {
         m_assembler.cmpl_rm(right, left.offset, left.base);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 
     {
         m_assembler.cmpl_rm(right, left.offset, left.base);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 

-    Jump branch32(Condition cond, Address left, Imm32 right)
+    Jump branch32(RelationalCondition cond, Address left, TrustedImm32 right)

     {
         m_assembler.cmpl_im(right.m_value, left.offset, left.base);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 
     {
         m_assembler.cmpl_im(right.m_value, left.offset, left.base);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 

-    Jump branch32(Condition cond, BaseIndex left, Imm32 right)
+    Jump branch32(RelationalCondition cond, BaseIndex left, TrustedImm32 right)

     {
         m_assembler.cmpl_im(right.m_value, left.offset, left.base, left.index, left.scale);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 
     {
         m_assembler.cmpl_im(right.m_value, left.offset, left.base, left.index, left.scale);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 

-    Jump branch32WithUnalignedHalfWords(Condition cond, BaseIndex left, Imm32 right)
+    Jump branch32WithUnalignedHalfWords(RelationalCondition cond, BaseIndex left, TrustedImm32 right)

     {
         return branch32(cond, left, right);
     }
 
     {
         return branch32(cond, left, right);
     }
 

-    Jump branch16(Condition cond, BaseIndex left, RegisterID right)
-    {
-        m_assembler.cmpw_rm(right, left.offset, left.base, left.index, left.scale);
-        return Jump(m_assembler.jCC(x86Condition(cond)));
-    }
-
-    Jump branch16(Condition cond, BaseIndex left, Imm32 right)
-    {
-        ASSERT(!(right.m_value & 0xFFFF0000));
-
-        m_assembler.cmpw_im(right.m_value, left.offset, left.base, left.index, left.scale);
-        return Jump(m_assembler.jCC(x86Condition(cond)));
-    }
-
-    Jump branchTest32(Condition cond, RegisterID reg, RegisterID mask)
+    Jump branchTest32(ResultCondition cond, RegisterID reg, RegisterID mask)

     {
     {

-        ASSERT((cond == Zero) || (cond == NonZero));

         m_assembler.testl_rr(reg, mask);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 
         m_assembler.testl_rr(reg, mask);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 

-    Jump branchTest32(Condition cond, RegisterID reg, Imm32 mask = Imm32(-1))
+    Jump branchTest32(ResultCondition cond, RegisterID reg, TrustedImm32 mask = TrustedImm32(-1))

     {
     {

-        ASSERT((cond == Zero) || (cond == NonZero));

         // if we are only interested in the low seven bits, this can be tested with a testb
         if (mask.m_value == -1)
             m_assembler.testl_rr(reg, reg);
         // if we are only interested in the low seven bits, this can be tested with a testb
         if (mask.m_value == -1)
             m_assembler.testl_rr(reg, reg);

-        else if ((mask.m_value & ~0x7f) == 0)
-            m_assembler.testb_i8r(mask.m_value, reg);

         else
             m_assembler.testl_i32r(mask.m_value, reg);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 
         else
             m_assembler.testl_i32r(mask.m_value, reg);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 

-    Jump branchTest32(Condition cond, Address address, Imm32 mask = Imm32(-1))
+    Jump branchTest32(ResultCondition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))

     {
     {

-        ASSERT((cond == Zero) || (cond == NonZero));

         if (mask.m_value == -1)
             m_assembler.cmpl_im(0, address.offset, address.base);
         else
         if (mask.m_value == -1)
             m_assembler.cmpl_im(0, address.offset, address.base);
         else


@@ -708,15 +1126,44 @@ public:
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 

-    Jump branchTest32(Condition cond, BaseIndex address, Imm32 mask = Imm32(-1))
+    Jump branchTest32(ResultCondition cond, BaseIndex address, TrustedImm32 mask = TrustedImm32(-1))

     {
     {

-        ASSERT((cond == Zero) || (cond == NonZero));

         if (mask.m_value == -1)
             m_assembler.cmpl_im(0, address.offset, address.base, address.index, address.scale);
         else
             m_assembler.testl_i32m(mask.m_value, address.offset, address.base, address.index, address.scale);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
         if (mask.m_value == -1)
             m_assembler.cmpl_im(0, address.offset, address.base, address.index, address.scale);
         else
             m_assembler.testl_i32m(mask.m_value, address.offset, address.base, address.index, address.scale);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }

+    
+    Jump branchTest8(ResultCondition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))
+    {
+        // Byte in TrustedImm32 is not well defined, so be a little permisive here, but don't accept nonsense values.
+        ASSERT(mask.m_value >= -128 && mask.m_value <= 255);
+        if (mask.m_value == -1)
+            m_assembler.cmpb_im(0, address.offset, address.base);
+        else
+            m_assembler.testb_im(mask.m_value, address.offset, address.base);
+        return Jump(m_assembler.jCC(x86Condition(cond)));
+    }
+    
+    Jump branchTest8(ResultCondition cond, BaseIndex address, TrustedImm32 mask = TrustedImm32(-1))
+    {
+        // Byte in TrustedImm32 is not well defined, so be a little permisive here, but don't accept nonsense values.
+        ASSERT(mask.m_value >= -128 && mask.m_value <= 255);
+        if (mask.m_value == -1)
+            m_assembler.cmpb_im(0, address.offset, address.base, address.index, address.scale);
+        else
+            m_assembler.testb_im(mask.m_value, address.offset, address.base, address.index, address.scale);
+        return Jump(m_assembler.jCC(x86Condition(cond)));
+    }
+
+    Jump branch8(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
+    {
+        ASSERT(!(right.m_value & 0xFFFFFF00));
+
+        m_assembler.cmpb_im(right.m_value, left.offset, left.base, left.index, left.scale);
+        return Jump(m_assembler.jCC(x86Condition(cond)));
+    }

 
     Jump jump()
     {
 
     Jump jump()
     {


@@ -745,100 +1192,135 @@ public:
     // * jo operations branch if the (signed) arithmetic
     //   operation caused an overflow to occur.
     
     // * jo operations branch if the (signed) arithmetic
     //   operation caused an overflow to occur.
     

-    Jump branchAdd32(Condition cond, RegisterID src, RegisterID dest)
+    Jump branchAdd32(ResultCondition cond, RegisterID src, RegisterID dest)

     {
     {

-        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));

         add32(src, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 
         add32(src, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 

-    Jump branchAdd32(Condition cond, Imm32 imm, RegisterID dest)
+    Jump branchAdd32(ResultCondition cond, TrustedImm32 imm, RegisterID dest)

     {
     {

-        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));

         add32(imm, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
     
         add32(imm, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
     

-    Jump branchAdd32(Condition cond, Imm32 src, Address dest)
+    Jump branchAdd32(ResultCondition cond, TrustedImm32 src, Address dest)

     {
     {

-        ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero));

         add32(src, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 
         add32(src, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 

-    Jump branchAdd32(Condition cond, RegisterID src, Address dest)
+    Jump branchAdd32(ResultCondition cond, RegisterID src, Address dest)

     {
     {

-        ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero));

         add32(src, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 
         add32(src, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 

-    Jump branchAdd32(Condition cond, Address src, RegisterID dest)
+    Jump branchAdd32(ResultCondition cond, Address src, RegisterID dest)

     {
     {

-        ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero));

         add32(src, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 
         add32(src, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 

-    Jump branchMul32(Condition cond, RegisterID src, RegisterID dest)
+    Jump branchAdd32(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest)
+    {
+        if (src1 == dest)
+            return branchAdd32(cond, src2, dest);
+        move(src2, dest);
+        return branchAdd32(cond, src1, dest);
+    }
+
+    Jump branchAdd32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest)
+    {
+        move(src, dest);
+        return branchAdd32(cond, imm, dest);
+    }
+
+    Jump branchMul32(ResultCondition cond, RegisterID src, RegisterID dest)

     {
     {

-        ASSERT(cond == Overflow);

         mul32(src, dest);
         mul32(src, dest);

+        if (cond != Overflow)
+            m_assembler.testl_rr(dest, dest);

         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 

-    Jump branchMul32(Condition cond, Address src, RegisterID dest)
+    Jump branchMul32(ResultCondition cond, Address src, RegisterID dest)

     {
     {

-        ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero));

         mul32(src, dest);
         mul32(src, dest);

+        if (cond != Overflow)
+            m_assembler.testl_rr(dest, dest);

         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
     
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
     

-    Jump branchMul32(Condition cond, Imm32 imm, RegisterID src, RegisterID dest)
+    Jump branchMul32(ResultCondition cond, TrustedImm32 imm, RegisterID src, RegisterID dest)

     {
     {

-        ASSERT(cond == Overflow);

         mul32(imm, src, dest);
         mul32(imm, src, dest);

+        if (cond != Overflow)
+            m_assembler.testl_rr(dest, dest);

         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
     
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
     

-    Jump branchSub32(Condition cond, RegisterID src, RegisterID dest)
+    Jump branchMul32(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest)
+    {
+        if (src1 == dest)
+            return branchMul32(cond, src2, dest);
+        move(src2, dest);
+        return branchMul32(cond, src1, dest);
+    }
+
+    Jump branchSub32(ResultCondition cond, RegisterID src, RegisterID dest)

     {
     {

-        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));

         sub32(src, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
     
         sub32(src, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
     

-    Jump branchSub32(Condition cond, Imm32 imm, RegisterID dest)
+    Jump branchSub32(ResultCondition cond, TrustedImm32 imm, RegisterID dest)

     {
     {

-        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));

         sub32(imm, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 
         sub32(imm, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 

-    Jump branchSub32(Condition cond, Imm32 imm, Address dest)
+    Jump branchSub32(ResultCondition cond, TrustedImm32 imm, Address dest)

     {
     {

-        ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero));

         sub32(imm, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 
         sub32(imm, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 

-    Jump branchSub32(Condition cond, RegisterID src, Address dest)
+    Jump branchSub32(ResultCondition cond, RegisterID src, Address dest)

     {
     {

-        ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero));

         sub32(src, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 
         sub32(src, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 

-    Jump branchSub32(Condition cond, Address src, RegisterID dest)
+    Jump branchSub32(ResultCondition cond, Address src, RegisterID dest)

     {
     {

-        ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero));

         sub32(src, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 
         sub32(src, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
 

-    Jump branchOr32(Condition cond, RegisterID src, RegisterID dest)
+    Jump branchSub32(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest)
+    {
+        // B := A - B is invalid.
+        ASSERT(src1 == dest || src2 != dest);
+
+        move(src1, dest);
+        return branchSub32(cond, src2, dest);
+    }
+
+    Jump branchSub32(ResultCondition cond, RegisterID src1, TrustedImm32 src2, RegisterID dest)
+    {
+        move(src1, dest);
+        return branchSub32(cond, src2, dest);
+    }
+
+    Jump branchNeg32(ResultCondition cond, RegisterID srcDest)
+    {
+        neg32(srcDest);
+        return Jump(m_assembler.jCC(x86Condition(cond)));
+    }
+
+    Jump branchOr32(ResultCondition cond, RegisterID src, RegisterID dest)

     {
     {

-        ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero));

         or32(src, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }
         or32(src, dest);
         return Jump(m_assembler.jCC(x86Condition(cond)));
     }


@@ -871,74 +1353,89 @@ public:
         m_assembler.ret();
     }
 
         m_assembler.ret();
     }
 

-    void set8(Condition cond, RegisterID left, RegisterID right, RegisterID dest)
-    {
-        m_assembler.cmpl_rr(right, left);
-        m_assembler.setCC_r(x86Condition(cond), dest);
-    }
-
-    void set8(Condition cond, Address left, RegisterID right, RegisterID dest)
+    void compare8(RelationalCondition cond, Address left, TrustedImm32 right, RegisterID dest)

     {
     {

-        m_assembler.cmpl_mr(left.offset, left.base, right);
-        m_assembler.setCC_r(x86Condition(cond), dest);
+        m_assembler.cmpb_im(right.m_value, left.offset, left.base);
+        set32(x86Condition(cond), dest);

     }
     }

-
-    void set8(Condition cond, RegisterID left, Imm32 right, RegisterID dest)
-    {
-        if (((cond == Equal) || (cond == NotEqual)) && !right.m_value)
-            m_assembler.testl_rr(left, left);
-        else
-            m_assembler.cmpl_ir(right.m_value, left);
-        m_assembler.setCC_r(x86Condition(cond), dest);
-    }
-
-    void set32(Condition cond, RegisterID left, RegisterID right, RegisterID dest)
+    
+    void compare32(RelationalCondition cond, RegisterID left, RegisterID right, RegisterID dest)

     {
         m_assembler.cmpl_rr(right, left);
     {
         m_assembler.cmpl_rr(right, left);

-        m_assembler.setCC_r(x86Condition(cond), dest);
-        m_assembler.movzbl_rr(dest, dest);
+        set32(x86Condition(cond), dest);

     }
 
     }
 

-    void set32(Condition cond, RegisterID left, Imm32 right, RegisterID dest)
+    void compare32(RelationalCondition cond, RegisterID left, TrustedImm32 right, RegisterID dest)

     {
         if (((cond == Equal) || (cond == NotEqual)) && !right.m_value)
             m_assembler.testl_rr(left, left);
         else
             m_assembler.cmpl_ir(right.m_value, left);
     {
         if (((cond == Equal) || (cond == NotEqual)) && !right.m_value)
             m_assembler.testl_rr(left, left);
         else
             m_assembler.cmpl_ir(right.m_value, left);

-        m_assembler.setCC_r(x86Condition(cond), dest);
-        m_assembler.movzbl_rr(dest, dest);
+        set32(x86Condition(cond), dest);

     }
 
     // FIXME:
     }
 
     // FIXME:

-    // The mask should be optional... paerhaps the argument order should be
+    // The mask should be optional... perhaps the argument order should be

     // dest-src, operations always have a dest? ... possibly not true, considering
     // asm ops like test, or pseudo ops like pop().
 
     // dest-src, operations always have a dest? ... possibly not true, considering
     // asm ops like test, or pseudo ops like pop().
 

-    void setTest8(Condition cond, Address address, Imm32 mask, RegisterID dest)
+    void test8(ResultCondition cond, Address address, TrustedImm32 mask, RegisterID dest)

     {
         if (mask.m_value == -1)
     {
         if (mask.m_value == -1)

-            m_assembler.cmpl_im(0, address.offset, address.base);
+            m_assembler.cmpb_im(0, address.offset, address.base);

         else
         else

-            m_assembler.testl_i32m(mask.m_value, address.offset, address.base);
-        m_assembler.setCC_r(x86Condition(cond), dest);
+            m_assembler.testb_im(mask.m_value, address.offset, address.base);
+        set32(x86Condition(cond), dest);

     }
 
     }
 

-    void setTest32(Condition cond, Address address, Imm32 mask, RegisterID dest)
+    void test32(ResultCondition cond, Address address, TrustedImm32 mask, RegisterID dest)

     {
         if (mask.m_value == -1)
             m_assembler.cmpl_im(0, address.offset, address.base);
         else
             m_assembler.testl_i32m(mask.m_value, address.offset, address.base);
     {
         if (mask.m_value == -1)
             m_assembler.cmpl_im(0, address.offset, address.base);
         else
             m_assembler.testl_i32m(mask.m_value, address.offset, address.base);

-        m_assembler.setCC_r(x86Condition(cond), dest);
-        m_assembler.movzbl_rr(dest, dest);
+        set32(x86Condition(cond), dest);
+    }
+
+    // Invert a relational condition, e.g. == becomes !=, < becomes >=, etc.
+    static RelationalCondition invert(RelationalCondition cond)
+    {
+        return static_cast<RelationalCondition>(cond ^ 1);
+    }
+
+    void nop()
+    {
+        m_assembler.nop();

     }
 
 protected:
     }
 
 protected:

-    X86Assembler::Condition x86Condition(Condition cond)
+    X86Assembler::Condition x86Condition(RelationalCondition cond)

     {
         return static_cast<X86Assembler::Condition>(cond);
     }
 
     {
         return static_cast<X86Assembler::Condition>(cond);
     }
 

+    X86Assembler::Condition x86Condition(ResultCondition cond)
+    {
+        return static_cast<X86Assembler::Condition>(cond);
+    }
+
+    void set32(X86Assembler::Condition cond, RegisterID dest)
+    {
+#if CPU(X86)
+        // On 32-bit x86 we can only set the first 4 registers;
+        // esp..edi are mapped to the 'h' registers!
+        if (dest >= 4) {
+            m_assembler.xchgl_rr(dest, X86Registers::eax);
+            m_assembler.setCC_r(cond, X86Registers::eax);
+            m_assembler.movzbl_rr(X86Registers::eax, X86Registers::eax);
+            m_assembler.xchgl_rr(dest, X86Registers::eax);
+            return;
+        }
+#endif
+        m_assembler.setCC_r(cond, dest);
+        m_assembler.movzbl_rr(dest, dest);
+    }
+

 private:
     // Only MacroAssemblerX86 should be using the following method; SSE2 is always available on
     // x86_64, and clients & subclasses of MacroAssembler should be using 'supportsFloatingPoint()'.
 private:
     // Only MacroAssemblerX86 should be using the following method; SSE2 is always available on
     // x86_64, and clients & subclasses of MacroAssembler should be using 'supportsFloatingPoint()'.