JavaScriptCore-621.1.tar.gz

[apple/javascriptcore.git] / assembler / ARMAssembler.cpp

diff --git a/assembler/ARMAssembler.cpp b/assembler/ARMAssembler.cpp
index 6dd2b87ff6e0e9a78845dad10df63d9d4d820f05..a181b7e982f4a4eaa7c68e78a0b94197a7b06f3c 100644 (file)
--- a/assembler/ARMAssembler.cpp
+++ b/assembler/ARMAssembler.cpp
@@ -262,28 +262,29 @@ ARMWord ARMAssembler::encodeComplexImm(ARMWord imm, int dest)
 
 // Memory load/store helpers
 
 
 // Memory load/store helpers
 

-void ARMAssembler::dataTransfer32(bool isLoad, RegisterID srcDst, RegisterID base, int32_t offset)
+void ARMAssembler::dataTransfer32(bool isLoad, RegisterID srcDst, RegisterID base, int32_t offset, bool bytes)

 {
 {

+    ARMWord transferFlag = bytes ? DT_BYTE : 0;

     if (offset >= 0) {
         if (offset <= 0xfff)
     if (offset >= 0) {
         if (offset <= 0xfff)

-            dtr_u(isLoad, srcDst, base, offset);
+            dtr_u(isLoad, srcDst, base, offset | transferFlag);

         else if (offset <= 0xfffff) {
             add_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 12) | (10 << 8));
         else if (offset <= 0xfffff) {
             add_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 12) | (10 << 8));

-            dtr_u(isLoad, srcDst, ARMRegisters::S0, offset & 0xfff);
+            dtr_u(isLoad, srcDst, ARMRegisters::S0, (offset & 0xfff) | transferFlag);

         } else {
             ARMWord reg = getImm(offset, ARMRegisters::S0);
         } else {
             ARMWord reg = getImm(offset, ARMRegisters::S0);

-            dtr_ur(isLoad, srcDst, base, reg);
+            dtr_ur(isLoad, srcDst, base, reg | transferFlag);

         }
     } else {
         offset = -offset;
         if (offset <= 0xfff)
         }
     } else {
         offset = -offset;
         if (offset <= 0xfff)

-            dtr_d(isLoad, srcDst, base, offset);
+            dtr_d(isLoad, srcDst, base, offset | transferFlag);

         else if (offset <= 0xfffff) {
             sub_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 12) | (10 << 8));
         else if (offset <= 0xfffff) {
             sub_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 12) | (10 << 8));

-            dtr_d(isLoad, srcDst, ARMRegisters::S0, offset & 0xfff);
+            dtr_d(isLoad, srcDst, ARMRegisters::S0, (offset & 0xfff) | transferFlag);

         } else {
             ARMWord reg = getImm(offset, ARMRegisters::S0);
         } else {
             ARMWord reg = getImm(offset, ARMRegisters::S0);

-            dtr_dr(isLoad, srcDst, base, reg);
+            dtr_dr(isLoad, srcDst, base, reg | transferFlag);

         }
     }
 }
         }
     }
 }


@@ -356,7 +357,7 @@ void* ARMAssembler::executableCopy(ExecutablePool* allocator)
         int pos = (*iter) & (~0x1);
         ARMWord* ldrAddr = reinterpret_cast<ARMWord*>(data + pos);
         ARMWord* addr = getLdrImmAddress(ldrAddr);
         int pos = (*iter) & (~0x1);
         ARMWord* ldrAddr = reinterpret_cast<ARMWord*>(data + pos);
         ARMWord* addr = getLdrImmAddress(ldrAddr);

-        if (*addr != 0xffffffff) {
+        if (*addr != InvalidBranchTarget) {

             if (!(*iter & 1)) {
                 int diff = reinterpret_cast<ARMWord*>(data + *addr) - (ldrAddr + DefaultPrefetching);
 
             if (!(*iter & 1)) {
                 int diff = reinterpret_cast<ARMWord*>(data + *addr) - (ldrAddr + DefaultPrefetching);