JavaScriptCore-1218.34.tar.gz

[apple/javascriptcore.git] / assembler / MacroAssemblerARM.h

diff --git a/assembler/MacroAssemblerARM.h b/assembler/MacroAssemblerARM.h
index 21b8de8fffdde06583d34c31acd03f2f0d48178e..494fe640ddfef0b111f9b014b3cc0f8b3a7a9773 100644 (file)
--- a/assembler/MacroAssemblerARM.h
+++ b/assembler/MacroAssemblerARM.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2008 Apple Inc.
 /*
  * Copyright (C) 2008 Apple Inc.

- * Copyright (C) 2009 University of Szeged
+ * Copyright (C) 2009, 2010 University of Szeged

  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without


@@ -28,8 +28,6 @@
 #ifndef MacroAssemblerARM_h
 #define MacroAssemblerARM_h
 
 #ifndef MacroAssemblerARM_h
 #define MacroAssemblerARM_h
 

-#include <wtf/Platform.h>
-

 #if ENABLE(ASSEMBLER) && CPU(ARM_TRADITIONAL)
 
 #include "ARMAssembler.h"
 #if ENABLE(ASSEMBLER) && CPU(ARM_TRADITIONAL)
 
 #include "ARMAssembler.h"


@@ -42,7 +40,9 @@ class MacroAssemblerARM : public AbstractMacroAssembler<ARMAssembler> {
     static const int DoubleConditionBitSpecial = 0x10;
     COMPILE_ASSERT(!(DoubleConditionBitSpecial & DoubleConditionMask), DoubleConditionBitSpecial_should_not_interfere_with_ARMAssembler_Condition_codes);
 public:
     static const int DoubleConditionBitSpecial = 0x10;
     COMPILE_ASSERT(!(DoubleConditionBitSpecial & DoubleConditionMask), DoubleConditionBitSpecial_should_not_interfere_with_ARMAssembler_Condition_codes);
 public:

-    enum Condition {
+    typedef ARMRegisters::FPRegisterID FPRegisterID;
+
+    enum RelationalCondition {

         Equal = ARMAssembler::EQ,
         NotEqual = ARMAssembler::NE,
         Above = ARMAssembler::HI,
         Equal = ARMAssembler::EQ,
         NotEqual = ARMAssembler::NE,
         Above = ARMAssembler::HI,


@@ -52,9 +52,13 @@ public:
         GreaterThan = ARMAssembler::GT,
         GreaterThanOrEqual = ARMAssembler::GE,
         LessThan = ARMAssembler::LT,
         GreaterThan = ARMAssembler::GT,
         GreaterThanOrEqual = ARMAssembler::GE,
         LessThan = ARMAssembler::LT,

-        LessThanOrEqual = ARMAssembler::LE,
+        LessThanOrEqual = ARMAssembler::LE
+    };
+
+    enum ResultCondition {

         Overflow = ARMAssembler::VS,
         Signed = ARMAssembler::MI,
         Overflow = ARMAssembler::VS,
         Signed = ARMAssembler::MI,

+        PositiveOrZero = ARMAssembler::PL,

         Zero = ARMAssembler::EQ,
         NonZero = ARMAssembler::NE
     };
         Zero = ARMAssembler::EQ,
         NonZero = ARMAssembler::NE
     };


@@ -83,19 +87,31 @@ public:
 
     void add32(RegisterID src, RegisterID dest)
     {
 
     void add32(RegisterID src, RegisterID dest)
     {

-        m_assembler.adds_r(dest, dest, src);
+        m_assembler.adds(dest, dest, src);
+    }
+
+    void add32(RegisterID op1, RegisterID op2, RegisterID dest)
+    {
+        m_assembler.adds(dest, op1, op2);

     }
 
     }
 

-    void add32(Imm32 imm, Address address)
+    void add32(TrustedImm32 imm, Address address)

     {
         load32(address, ARMRegisters::S1);
         add32(imm, ARMRegisters::S1);
         store32(ARMRegisters::S1, address);
     }
 
     {
         load32(address, ARMRegisters::S1);
         add32(imm, ARMRegisters::S1);
         store32(ARMRegisters::S1, address);
     }
 

-    void add32(Imm32 imm, RegisterID dest)
+    void add32(TrustedImm32 imm, RegisterID dest)
+    {
+        m_assembler.adds(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+    }
+
+    void add32(AbsoluteAddress src, RegisterID dest)

     {
     {

-        m_assembler.adds_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+        move(TrustedImmPtr(src.m_ptr), ARMRegisters::S1);
+        m_assembler.dtrUp(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0);
+        add32(ARMRegisters::S1, dest);

     }
 
     void add32(Address src, RegisterID dest)
     }
 
     void add32(Address src, RegisterID dest)


@@ -104,94 +120,185 @@ public:
         add32(ARMRegisters::S1, dest);
     }
 
         add32(ARMRegisters::S1, dest);
     }
 

+    void add32(RegisterID src, TrustedImm32 imm, RegisterID dest)
+    {
+        m_assembler.adds(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+    }
+

     void and32(RegisterID src, RegisterID dest)
     {
     void and32(RegisterID src, RegisterID dest)
     {

-        m_assembler.ands_r(dest, dest, src);
+        m_assembler.bitAnds(dest, dest, src);
+    }
+
+    void and32(RegisterID op1, RegisterID op2, RegisterID dest)
+    {
+        m_assembler.bitAnds(dest, op1, op2);
+    }
+
+    void and32(TrustedImm32 imm, RegisterID dest)
+    {
+        ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true);
+        if (w & ARMAssembler::Op2InvertedImmediate)
+            m_assembler.bics(dest, dest, w & ~ARMAssembler::Op2InvertedImmediate);
+        else
+            m_assembler.bitAnds(dest, dest, w);

     }
 
     }
 

-    void and32(Imm32 imm, RegisterID dest)
+    void and32(TrustedImm32 imm, RegisterID src, RegisterID dest)

     {
         ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true);
     {
         ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true);

-        if (w & ARMAssembler::OP2_INV_IMM)
-            m_assembler.bics_r(dest, dest, w & ~ARMAssembler::OP2_INV_IMM);
+        if (w & ARMAssembler::Op2InvertedImmediate)
+            m_assembler.bics(dest, src, w & ~ARMAssembler::Op2InvertedImmediate);

         else
         else

-            m_assembler.ands_r(dest, dest, w);
+            m_assembler.bitAnds(dest, src, w);
+    }
+
+    void and32(Address src, RegisterID dest)
+    {
+        load32(src, ARMRegisters::S1);
+        and32(ARMRegisters::S1, dest);

     }
 
     }
 

-    void lshift32(RegisterID shift_amount, RegisterID dest)
+    void lshift32(RegisterID shiftAmount, RegisterID dest)

     {
     {

-        ARMWord w = ARMAssembler::getOp2(0x1f);
-        ASSERT(w != ARMAssembler::INVALID_IMM);
-        m_assembler.and_r(ARMRegisters::S0, shift_amount, w);
+        lshift32(dest, shiftAmount, dest);
+    }

 
 

-        m_assembler.movs_r(dest, m_assembler.lsl_r(dest, ARMRegisters::S0));
+    void lshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
+    {
+        ARMWord w = ARMAssembler::getOp2Byte(0x1f);
+        m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w);
+
+        m_assembler.movs(dest, m_assembler.lslRegister(src, ARMRegisters::S0));

     }
 
     }
 

-    void lshift32(Imm32 imm, RegisterID dest)
+    void lshift32(TrustedImm32 imm, RegisterID dest)

     {
     {

-        m_assembler.movs_r(dest, m_assembler.lsl(dest, imm.m_value & 0x1f));
+        m_assembler.movs(dest, m_assembler.lsl(dest, imm.m_value & 0x1f));

     }
 
     }
 

-    void mul32(RegisterID src, RegisterID dest)
+    void lshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)

     {
     {

-        if (src == dest) {
-            move(src, ARMRegisters::S0);
-            src = ARMRegisters::S0;
+        m_assembler.movs(dest, m_assembler.lsl(src, imm.m_value & 0x1f));
+    }
+
+    void mul32(RegisterID op1, RegisterID op2, RegisterID dest)
+    {
+        if (op2 == dest) {
+            if (op1 == dest) {
+                move(op2, ARMRegisters::S0);
+                op2 = ARMRegisters::S0;
+            } else {
+                // Swap the operands.
+                RegisterID tmp = op1;
+                op1 = op2;
+                op2 = tmp;
+            }

         }
         }

-        m_assembler.muls_r(dest, dest, src);
+        m_assembler.muls(dest, op1, op2);

     }
 
     }
 

-    void mul32(Imm32 imm, RegisterID src, RegisterID dest)
+    void mul32(RegisterID src, RegisterID dest)
+    {
+        mul32(src, dest, dest);
+    }
+
+    void mul32(TrustedImm32 imm, RegisterID src, RegisterID dest)

     {
         move(imm, ARMRegisters::S0);
     {
         move(imm, ARMRegisters::S0);

-        m_assembler.muls_r(dest, src, ARMRegisters::S0);
+        m_assembler.muls(dest, src, ARMRegisters::S0);

     }
 
     void neg32(RegisterID srcDest)
     {
     }
 
     void neg32(RegisterID srcDest)
     {

-        m_assembler.rsbs_r(srcDest, srcDest, ARMAssembler::getOp2(0));
+        m_assembler.rsbs(srcDest, srcDest, ARMAssembler::getOp2Byte(0));
+    }
+
+    void or32(RegisterID src, RegisterID dest)
+    {
+        m_assembler.orrs(dest, dest, src);

     }
 
     }
 

-    void not32(RegisterID dest)
+    void or32(RegisterID src, AbsoluteAddress dest)

     {
     {

-        m_assembler.mvns_r(dest, dest);
+        move(TrustedImmPtr(dest.m_ptr), ARMRegisters::S0);
+        load32(Address(ARMRegisters::S0), ARMRegisters::S1);
+        or32(src, ARMRegisters::S1);
+        store32(ARMRegisters::S1, ARMRegisters::S0);

     }
 
     }
 

-    void or32(RegisterID src, RegisterID dest)
+    void or32(TrustedImm32 imm, RegisterID dest)
+    {
+        m_assembler.orrs(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+    }
+
+    void or32(TrustedImm32 imm, RegisterID src, RegisterID dest)
+    {
+        m_assembler.orrs(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+    }
+
+    void or32(RegisterID op1, RegisterID op2, RegisterID dest)
+    {
+        m_assembler.orrs(dest, op1, op2);
+    }
+
+    void rshift32(RegisterID shiftAmount, RegisterID dest)
+    {
+        rshift32(dest, shiftAmount, dest);
+    }
+
+    void rshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
+    {
+        ARMWord w = ARMAssembler::getOp2Byte(0x1f);
+        m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w);
+
+        m_assembler.movs(dest, m_assembler.asrRegister(src, ARMRegisters::S0));
+    }
+
+    void rshift32(TrustedImm32 imm, RegisterID dest)

     {
     {

-        m_assembler.orrs_r(dest, dest, src);
+        rshift32(dest, imm, dest);

     }
 
     }
 

-    void or32(Imm32 imm, RegisterID dest)
+    void rshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)

     {
     {

-        m_assembler.orrs_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+        m_assembler.movs(dest, m_assembler.asr(src, imm.m_value & 0x1f));

     }
 
     }
 

-    void rshift32(RegisterID shift_amount, RegisterID dest)
+    void urshift32(RegisterID shiftAmount, RegisterID dest)

     {
     {

-        ARMWord w = ARMAssembler::getOp2(0x1f);
-        ASSERT(w != ARMAssembler::INVALID_IMM);
-        m_assembler.and_r(ARMRegisters::S0, shift_amount, w);
+        urshift32(dest, shiftAmount, dest);
+    }
+
+    void urshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
+    {
+        ARMWord w = ARMAssembler::getOp2Byte(0x1f);
+        m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w);

 
 

-        m_assembler.movs_r(dest, m_assembler.asr_r(dest, ARMRegisters::S0));
+        m_assembler.movs(dest, m_assembler.lsrRegister(src, ARMRegisters::S0));

     }
 
     }
 

-    void rshift32(Imm32 imm, RegisterID dest)
+    void urshift32(TrustedImm32 imm, RegisterID dest)
+    {
+        m_assembler.movs(dest, m_assembler.lsr(dest, imm.m_value & 0x1f));
+    }
+    
+    void urshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)

     {
     {

-        m_assembler.movs_r(dest, m_assembler.asr(dest, imm.m_value & 0x1f));
+        m_assembler.movs(dest, m_assembler.lsr(src, imm.m_value & 0x1f));

     }
 
     void sub32(RegisterID src, RegisterID dest)
     {
     }
 
     void sub32(RegisterID src, RegisterID dest)
     {

-        m_assembler.subs_r(dest, dest, src);
+        m_assembler.subs(dest, dest, src);

     }
 
     }
 

-    void sub32(Imm32 imm, RegisterID dest)
+    void sub32(TrustedImm32 imm, RegisterID dest)

     {
     {

-        m_assembler.subs_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+        m_assembler.subs(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));

     }
 
     }
 

-    void sub32(Imm32 imm, Address address)
+    void sub32(TrustedImm32 imm, Address address)

     {
         load32(address, ARMRegisters::S1);
         sub32(imm, ARMRegisters::S1);
     {
         load32(address, ARMRegisters::S1);
         sub32(imm, ARMRegisters::S1);


@@ -204,24 +311,86 @@ public:
         sub32(ARMRegisters::S1, dest);
     }
 
         sub32(ARMRegisters::S1, dest);
     }
 

+    void sub32(RegisterID src, TrustedImm32 imm, RegisterID dest)
+    {
+        m_assembler.subs(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+    }
+

     void xor32(RegisterID src, RegisterID dest)
     {
     void xor32(RegisterID src, RegisterID dest)
     {

-        m_assembler.eors_r(dest, dest, src);
+        m_assembler.eors(dest, dest, src);
+    }
+
+    void xor32(RegisterID op1, RegisterID op2, RegisterID dest)
+    {
+        m_assembler.eors(dest, op1, op2);
+    }
+
+    void xor32(TrustedImm32 imm, RegisterID dest)
+    {
+        if (imm.m_value == -1)
+            m_assembler.mvns(dest, dest);
+        else
+            m_assembler.eors(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));

     }
 
     }
 

-    void xor32(Imm32 imm, RegisterID dest)
+    void xor32(TrustedImm32 imm, RegisterID src, RegisterID dest)

     {
     {

-        m_assembler.eors_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+        if (imm.m_value == -1)
+            m_assembler.mvns(dest, src);
+        else    
+            m_assembler.eors(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+    }
+
+    void countLeadingZeros32(RegisterID src, RegisterID dest)
+    {
+#if WTF_ARM_ARCH_AT_LEAST(5)
+        m_assembler.clz(dest, src);
+#else
+        UNUSED_PARAM(src);
+        UNUSED_PARAM(dest);
+        RELEASE_ASSERT_NOT_REACHED();
+#endif
+    }
+
+    void load8(ImplicitAddress address, RegisterID dest)
+    {
+        m_assembler.dataTransfer32(ARMAssembler::LoadUint8, dest, address.base, address.offset);
+    }
+
+    void load8(BaseIndex address, RegisterID dest)
+    {
+        m_assembler.baseIndexTransfer32(ARMAssembler::LoadUint8, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
+    }
+
+    void load8Signed(BaseIndex address, RegisterID dest)
+    {
+        m_assembler.baseIndexTransfer16(ARMAssembler::LoadInt8, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
+    }
+
+    void load16(ImplicitAddress address, RegisterID dest)
+    {
+        m_assembler.dataTransfer16(ARMAssembler::LoadUint16, dest, address.base, address.offset);
+    }
+
+    void load16(BaseIndex address, RegisterID dest)
+    {
+        m_assembler.baseIndexTransfer16(ARMAssembler::LoadUint16, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
+    }
+
+    void load16Signed(BaseIndex address, RegisterID dest)
+    {
+        m_assembler.baseIndexTransfer16(ARMAssembler::LoadInt16, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);

     }
 
     void load32(ImplicitAddress address, RegisterID dest)
     {
     }
 
     void load32(ImplicitAddress address, RegisterID dest)
     {

-        m_assembler.dataTransfer32(true, dest, address.base, address.offset);
+        m_assembler.dataTransfer32(ARMAssembler::LoadUint32, dest, address.base, address.offset);

     }
 
     void load32(BaseIndex address, RegisterID dest)
     {
     }
 
     void load32(BaseIndex address, RegisterID dest)
     {

-        m_assembler.baseIndexTransfer32(true, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
+        m_assembler.baseIndexTransfer32(ARMAssembler::LoadUint32, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);

     }
 
 #if CPU(ARMV5_OR_LOWER)
     }
 
 #if CPU(ARMV5_OR_LOWER)


@@ -233,81 +402,111 @@ public:
     }
 #endif
 
     }
 #endif
 

+    void load16Unaligned(BaseIndex address, RegisterID dest)
+    {
+        load16(address, dest);
+    }
+
+    ConvertibleLoadLabel convertibleLoadPtr(Address address, RegisterID dest)
+    {
+        ConvertibleLoadLabel result(this);
+        ASSERT(address.offset >= 0 && address.offset <= 255);
+        m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, address.base, address.offset);
+        return result;
+    }
+

     DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest)
     {
         DataLabel32 dataLabel(this);
     DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest)
     {
         DataLabel32 dataLabel(this);

-        m_assembler.ldr_un_imm(ARMRegisters::S0, 0);
-        m_assembler.dtr_ur(true, dest, address.base, ARMRegisters::S0);
+        m_assembler.ldrUniqueImmediate(ARMRegisters::S0, 0);
+        m_assembler.dtrUpRegister(ARMAssembler::LoadUint32, dest, address.base, ARMRegisters::S0);

         return dataLabel;
     }
 
         return dataLabel;
     }
 

-    Label loadPtrWithPatchToLEA(Address address, RegisterID dest)
+    static bool isCompactPtrAlignedAddressOffset(ptrdiff_t value)

     {
     {

-        Label label(this);
-        load32(address, dest);
-        return label;
+        return value >= -4095 && value <= 4095;

     }
 
     }
 

-    void load16(BaseIndex address, RegisterID dest)
+    DataLabelCompact load32WithCompactAddressOffsetPatch(Address address, RegisterID dest)

     {
     {

-        m_assembler.add_r(ARMRegisters::S0, address.base, m_assembler.lsl(address.index, address.scale));
-        if (address.offset>=0)
-            m_assembler.ldrh_u(dest, ARMRegisters::S0, ARMAssembler::getOp2Byte(address.offset));
+        DataLabelCompact dataLabel(this);
+        ASSERT(isCompactPtrAlignedAddressOffset(address.offset));
+        if (address.offset >= 0)
+            m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, address.base, address.offset);

         else
         else

-            m_assembler.ldrh_d(dest, ARMRegisters::S0, ARMAssembler::getOp2Byte(-address.offset));
+            m_assembler.dtrDown(ARMAssembler::LoadUint32, dest, address.base, address.offset);
+        return dataLabel;

     }
 
     DataLabel32 store32WithAddressOffsetPatch(RegisterID src, Address address)
     {
         DataLabel32 dataLabel(this);
     }
 
     DataLabel32 store32WithAddressOffsetPatch(RegisterID src, Address address)
     {
         DataLabel32 dataLabel(this);

-        m_assembler.ldr_un_imm(ARMRegisters::S0, 0);
-        m_assembler.dtr_ur(false, src, address.base, ARMRegisters::S0);
+        m_assembler.ldrUniqueImmediate(ARMRegisters::S0, 0);
+        m_assembler.dtrUpRegister(ARMAssembler::StoreUint32, src, address.base, ARMRegisters::S0);

         return dataLabel;
     }
 
         return dataLabel;
     }
 

+    void store8(RegisterID src, BaseIndex address)
+    {
+        m_assembler.baseIndexTransfer32(ARMAssembler::StoreUint8, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
+    }
+
+    void store8(TrustedImm32 imm, const void* address)
+    {
+        move(TrustedImm32(reinterpret_cast<ARMWord>(address)), ARMRegisters::S0);
+        move(imm, ARMRegisters::S1);
+        m_assembler.dtrUp(ARMAssembler::StoreUint8, ARMRegisters::S1, ARMRegisters::S0, 0);
+    }
+
+    void store16(RegisterID src, BaseIndex address)
+    {
+        m_assembler.baseIndexTransfer16(ARMAssembler::StoreUint16, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
+    }
+

     void store32(RegisterID src, ImplicitAddress address)
     {
     void store32(RegisterID src, ImplicitAddress address)
     {

-        m_assembler.dataTransfer32(false, src, address.base, address.offset);
+        m_assembler.dataTransfer32(ARMAssembler::StoreUint32, src, address.base, address.offset);

     }
 
     void store32(RegisterID src, BaseIndex address)
     {
     }
 
     void store32(RegisterID src, BaseIndex address)
     {

-        m_assembler.baseIndexTransfer32(false, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
+        m_assembler.baseIndexTransfer32(ARMAssembler::StoreUint32, src, address.base, address.index, static_cast<int>(address.scale), address.offset);

     }
 
     }
 

-    void store32(Imm32 imm, ImplicitAddress address)
+    void store32(TrustedImm32 imm, ImplicitAddress address)

     {
     {

-        if (imm.m_isPointer)
-            m_assembler.ldr_un_imm(ARMRegisters::S1, imm.m_value);
-        else
-            move(imm, ARMRegisters::S1);
+        move(imm, ARMRegisters::S1);

         store32(ARMRegisters::S1, address);
     }
 
         store32(ARMRegisters::S1, address);
     }
 

-    void store32(RegisterID src, void* address)
+    void store32(TrustedImm32 imm, BaseIndex address)

     {
     {

-        m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
-        m_assembler.dtr_u(false, src, ARMRegisters::S0, 0);
+        move(imm, ARMRegisters::S1);
+        m_assembler.baseIndexTransfer32(ARMAssembler::StoreUint32, ARMRegisters::S1, address.base, address.index, static_cast<int>(address.scale), address.offset);

     }
 
     }
 

-    void store32(Imm32 imm, void* address)
+    void store32(RegisterID src, const void* address)

     {
     {

-        m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
-        if (imm.m_isPointer)
-            m_assembler.ldr_un_imm(ARMRegisters::S1, imm.m_value);
-        else
-            m_assembler.moveImm(imm.m_value, ARMRegisters::S1);
-        m_assembler.dtr_u(false, ARMRegisters::S1, ARMRegisters::S0, 0);
+        m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
+        m_assembler.dtrUp(ARMAssembler::StoreUint32, src, ARMRegisters::S0, 0);
+    }
+
+    void store32(TrustedImm32 imm, const void* address)
+    {
+        m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
+        m_assembler.moveImm(imm.m_value, ARMRegisters::S1);
+        m_assembler.dtrUp(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0);

     }
 
     void pop(RegisterID dest)
     {
     }
 
     void pop(RegisterID dest)
     {

-        m_assembler.pop_r(dest);
+        m_assembler.pop(dest);

     }
 
     void push(RegisterID src)
     {
     }
 
     void push(RegisterID src)
     {

-        m_assembler.push_r(src);
+        m_assembler.push(src);

     }
 
     void push(Address address)
     }
 
     void push(Address address)


@@ -316,35 +515,33 @@ public:
         push(ARMRegisters::S1);
     }
 
         push(ARMRegisters::S1);
     }
 

-    void push(Imm32 imm)
+    void push(TrustedImm32 imm)

     {
         move(imm, ARMRegisters::S0);
         push(ARMRegisters::S0);
     }
 
     {
         move(imm, ARMRegisters::S0);
         push(ARMRegisters::S0);
     }
 

-    void move(Imm32 imm, RegisterID dest)
+    void move(TrustedImm32 imm, RegisterID dest)

     {
     {

-        if (imm.m_isPointer)
-            m_assembler.ldr_un_imm(dest, imm.m_value);
-        else
-            m_assembler.moveImm(imm.m_value, dest);
+        m_assembler.moveImm(imm.m_value, dest);

     }
 
     void move(RegisterID src, RegisterID dest)
     {
     }
 
     void move(RegisterID src, RegisterID dest)
     {

-        m_assembler.mov_r(dest, src);
+        if (src != dest)
+            m_assembler.mov(dest, src);

     }
 
     }
 

-    void move(ImmPtr imm, RegisterID dest)
+    void move(TrustedImmPtr imm, RegisterID dest)

     {
     {

-        move(Imm32(imm), dest);
+        move(TrustedImm32(imm), dest);

     }
 
     void swap(RegisterID reg1, RegisterID reg2)
     {
     }
 
     void swap(RegisterID reg1, RegisterID reg2)
     {

-        m_assembler.mov_r(ARMRegisters::S0, reg1);
-        m_assembler.mov_r(reg1, reg2);
-        m_assembler.mov_r(reg2, ARMRegisters::S0);
+        xor32(reg1, reg2);
+        xor32(reg2, reg1);
+        xor32(reg1, reg2);

     }
 
     void signExtend32ToPtr(RegisterID src, RegisterID dest)
     }
 
     void signExtend32ToPtr(RegisterID src, RegisterID dest)


@@ -359,94 +556,99 @@ public:
             move(src, dest);
     }
 
             move(src, dest);
     }
 

-    Jump branch32(Condition cond, RegisterID left, RegisterID right, int useConstantPool = 0)
+    Jump branch8(RelationalCondition cond, Address left, TrustedImm32 right)
+    {
+        load8(left, ARMRegisters::S1);
+        return branch32(cond, ARMRegisters::S1, right);
+    }
+
+    Jump branch8(RelationalCondition cond, BaseIndex left, TrustedImm32 right)

     {
     {

-        m_assembler.cmp_r(left, right);
+        ASSERT(!(right.m_value & 0xFFFFFF00));
+        load8(left, ARMRegisters::S1);
+        return branch32(cond, ARMRegisters::S1, right);
+    }
+
+    Jump branch32(RelationalCondition cond, RegisterID left, RegisterID right, int useConstantPool = 0)
+    {
+        m_assembler.cmp(left, right);

         return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool));
     }
 
         return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool));
     }
 

-    Jump branch32(Condition cond, RegisterID left, Imm32 right, int useConstantPool = 0)
+    Jump branch32(RelationalCondition cond, RegisterID left, TrustedImm32 right, int useConstantPool = 0)

     {
     {

-        if (right.m_isPointer) {
-            m_assembler.ldr_un_imm(ARMRegisters::S0, right.m_value);
-            m_assembler.cmp_r(left, ARMRegisters::S0);
-        } else
-            m_assembler.cmp_r(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));
+        internalCompare32(left, right);

         return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool));
     }
 
         return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool));
     }
 

-    Jump branch32(Condition cond, RegisterID left, Address right)
+    Jump branch32(RelationalCondition cond, RegisterID left, Address right)

     {
         load32(right, ARMRegisters::S1);
         return branch32(cond, left, ARMRegisters::S1);
     }
 
     {
         load32(right, ARMRegisters::S1);
         return branch32(cond, left, ARMRegisters::S1);
     }
 

-    Jump branch32(Condition cond, Address left, RegisterID right)
+    Jump branch32(RelationalCondition cond, Address left, RegisterID right)

     {
         load32(left, ARMRegisters::S1);
         return branch32(cond, ARMRegisters::S1, right);
     }
 
     {
         load32(left, ARMRegisters::S1);
         return branch32(cond, ARMRegisters::S1, right);
     }
 

-    Jump branch32(Condition cond, Address left, Imm32 right)
+    Jump branch32(RelationalCondition cond, Address left, TrustedImm32 right)

     {
         load32(left, ARMRegisters::S1);
         return branch32(cond, ARMRegisters::S1, right);
     }
 
     {
         load32(left, ARMRegisters::S1);
         return branch32(cond, ARMRegisters::S1, right);
     }
 

-    Jump branch32(Condition cond, BaseIndex left, Imm32 right)
+    Jump branch32(RelationalCondition cond, BaseIndex left, TrustedImm32 right)

     {
         load32(left, ARMRegisters::S1);
         return branch32(cond, ARMRegisters::S1, right);
     }
 
     {
         load32(left, ARMRegisters::S1);
         return branch32(cond, ARMRegisters::S1, right);
     }
 

-    Jump branch32WithUnalignedHalfWords(Condition cond, BaseIndex left, Imm32 right)
+    Jump branch32WithUnalignedHalfWords(RelationalCondition cond, BaseIndex left, TrustedImm32 right)

     {
         load32WithUnalignedHalfWords(left, ARMRegisters::S1);
         return branch32(cond, ARMRegisters::S1, right);
     }
 
     {
         load32WithUnalignedHalfWords(left, ARMRegisters::S1);
         return branch32(cond, ARMRegisters::S1, right);
     }
 

-    Jump branch16(Condition cond, BaseIndex left, RegisterID right)
+    Jump branchTest8(ResultCondition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))

     {
     {

-        UNUSED_PARAM(cond);
-        UNUSED_PARAM(left);
-        UNUSED_PARAM(right);
-        ASSERT_NOT_REACHED();
-        return jump();
+        load8(address, ARMRegisters::S1);
+        return branchTest32(cond, ARMRegisters::S1, mask);

     }
 
     }
 

-    Jump branch16(Condition cond, BaseIndex left, Imm32 right)
+    Jump branchTest8(ResultCondition cond, AbsoluteAddress address, TrustedImm32 mask = TrustedImm32(-1))

     {
     {

-        load16(left, ARMRegisters::S0);
-        move(right, ARMRegisters::S1);
-        m_assembler.cmp_r(ARMRegisters::S0, ARMRegisters::S1);
-        return m_assembler.jmp(ARMCondition(cond));
+        move(TrustedImmPtr(address.m_ptr), ARMRegisters::S1);
+        load8(Address(ARMRegisters::S1), ARMRegisters::S1);
+        return branchTest32(cond, ARMRegisters::S1, mask);

     }
 
     }
 

-    Jump branchTest32(Condition cond, RegisterID reg, RegisterID mask)
+    Jump branchTest32(ResultCondition cond, RegisterID reg, RegisterID mask)

     {
         ASSERT((cond == Zero) || (cond == NonZero));
     {
         ASSERT((cond == Zero) || (cond == NonZero));

-        m_assembler.tst_r(reg, mask);
+        m_assembler.tst(reg, mask);

         return Jump(m_assembler.jmp(ARMCondition(cond)));
     }
 
         return Jump(m_assembler.jmp(ARMCondition(cond)));
     }
 

-    Jump branchTest32(Condition cond, RegisterID reg, Imm32 mask = Imm32(-1))
+    Jump branchTest32(ResultCondition cond, RegisterID reg, TrustedImm32 mask = TrustedImm32(-1))

     {
         ASSERT((cond == Zero) || (cond == NonZero));
         ARMWord w = m_assembler.getImm(mask.m_value, ARMRegisters::S0, true);
     {
         ASSERT((cond == Zero) || (cond == NonZero));
         ARMWord w = m_assembler.getImm(mask.m_value, ARMRegisters::S0, true);

-        if (w & ARMAssembler::OP2_INV_IMM)
-            m_assembler.bics_r(ARMRegisters::S0, reg, w & ~ARMAssembler::OP2_INV_IMM);
+        if (w & ARMAssembler::Op2InvertedImmediate)
+            m_assembler.bics(ARMRegisters::S0, reg, w & ~ARMAssembler::Op2InvertedImmediate);

         else
         else

-            m_assembler.tst_r(reg, w);
+            m_assembler.tst(reg, w);

         return Jump(m_assembler.jmp(ARMCondition(cond)));
     }
 
         return Jump(m_assembler.jmp(ARMCondition(cond)));
     }
 

-    Jump branchTest32(Condition cond, Address address, Imm32 mask = Imm32(-1))
+    Jump branchTest32(ResultCondition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))

     {
         load32(address, ARMRegisters::S1);
         return branchTest32(cond, ARMRegisters::S1, mask);
     }
 
     {
         load32(address, ARMRegisters::S1);
         return branchTest32(cond, ARMRegisters::S1, mask);
     }
 

-    Jump branchTest32(Condition cond, BaseIndex address, Imm32 mask = Imm32(-1))
+    Jump branchTest32(ResultCondition cond, BaseIndex address, TrustedImm32 mask = TrustedImm32(-1))

     {
         load32(address, ARMRegisters::S1);
         return branchTest32(cond, ARMRegisters::S1, mask);
     {
         load32(address, ARMRegisters::S1);
         return branchTest32(cond, ARMRegisters::S1, mask);


@@ -459,7 +661,7 @@ public:
 
     void jump(RegisterID target)
     {
 
     void jump(RegisterID target)
     {

-        move(target, ARMRegisters::pc);
+        m_assembler.bx(target);

     }
 
     void jump(Address address)
     }
 
     void jump(Address address)


@@ -467,43 +669,97 @@ public:
         load32(address, ARMRegisters::pc);
     }
 
         load32(address, ARMRegisters::pc);
     }
 

-    Jump branchAdd32(Condition cond, RegisterID src, RegisterID dest)
+    void jump(AbsoluteAddress address)

     {
     {

-        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
+        move(TrustedImmPtr(address.m_ptr), ARMRegisters::S0);
+        load32(Address(ARMRegisters::S0, 0), ARMRegisters::pc);
+    }
+
+    void moveDoubleToInts(FPRegisterID src, RegisterID dest1, RegisterID dest2)
+    {
+        m_assembler.vmov(dest1, dest2, src);
+    }
+
+    void moveIntsToDouble(RegisterID src1, RegisterID src2, FPRegisterID dest, FPRegisterID)
+    {
+        m_assembler.vmov(dest, src1, src2);
+    }
+
+    Jump branchAdd32(ResultCondition cond, RegisterID src, RegisterID dest)
+    {
+        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
+            || (cond == NonZero) || (cond == PositiveOrZero));

         add32(src, dest);
         return Jump(m_assembler.jmp(ARMCondition(cond)));
     }
 
         add32(src, dest);
         return Jump(m_assembler.jmp(ARMCondition(cond)));
     }
 

-    Jump branchAdd32(Condition cond, Imm32 imm, RegisterID dest)
+    Jump branchAdd32(ResultCondition cond, RegisterID op1, RegisterID op2, RegisterID dest)

     {
     {

-        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
+        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
+            || (cond == NonZero) || (cond == PositiveOrZero));
+        add32(op1, op2, dest);
+        return Jump(m_assembler.jmp(ARMCondition(cond)));
+    }
+
+    Jump branchAdd32(ResultCondition cond, TrustedImm32 imm, RegisterID dest)
+    {
+        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
+            || (cond == NonZero) || (cond == PositiveOrZero));
+        add32(imm, dest);
+        return Jump(m_assembler.jmp(ARMCondition(cond)));
+    }
+
+    Jump branchAdd32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest)
+    {
+        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
+            || (cond == NonZero) || (cond == PositiveOrZero));
+        add32(src, imm, dest);
+        return Jump(m_assembler.jmp(ARMCondition(cond)));
+    }
+
+    Jump branchAdd32(ResultCondition cond, TrustedImm32 imm, AbsoluteAddress dest)
+    {
+        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
+            || (cond == NonZero) || (cond == PositiveOrZero));

         add32(imm, dest);
         return Jump(m_assembler.jmp(ARMCondition(cond)));
     }
 
         add32(imm, dest);
         return Jump(m_assembler.jmp(ARMCondition(cond)));
     }
 

-    void mull32(RegisterID src1, RegisterID src2, RegisterID dest)
+    void mull32(RegisterID op1, RegisterID op2, RegisterID dest)

     {
     {

-        if (src1 == dest) {
-            move(src1, ARMRegisters::S0);
-            src1 = ARMRegisters::S0;
+        if (op2 == dest) {
+            if (op1 == dest) {
+                move(op2, ARMRegisters::S0);
+                op2 = ARMRegisters::S0;
+            } else {
+                // Swap the operands.
+                RegisterID tmp = op1;
+                op1 = op2;
+                op2 = tmp;
+            }

         }
         }

-        m_assembler.mull_r(ARMRegisters::S1, dest, src2, src1);
-        m_assembler.cmp_r(ARMRegisters::S1, m_assembler.asr(dest, 31));
+        m_assembler.mull(ARMRegisters::S1, dest, op1, op2);
+        m_assembler.cmp(ARMRegisters::S1, m_assembler.asr(dest, 31));

     }
 
     }
 

-    Jump branchMul32(Condition cond, RegisterID src, RegisterID dest)
+    Jump branchMul32(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest)

     {
         ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
         if (cond == Overflow) {
     {
         ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
         if (cond == Overflow) {

-            mull32(src, dest, dest);
+            mull32(src1, src2, dest);

             cond = NonZero;
         }
         else
             cond = NonZero;
         }
         else

-            mul32(src, dest);
+            mul32(src1, src2, dest);

         return Jump(m_assembler.jmp(ARMCondition(cond)));
     }
 
         return Jump(m_assembler.jmp(ARMCondition(cond)));
     }
 

-    Jump branchMul32(Condition cond, Imm32 imm, RegisterID src, RegisterID dest)
+    Jump branchMul32(ResultCondition cond, RegisterID src, RegisterID dest)
+    {
+        return branchMul32(cond, src, dest, dest);
+    }
+
+    Jump branchMul32(ResultCondition cond, TrustedImm32 imm, RegisterID src, RegisterID dest)

     {
         ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
         if (cond == Overflow) {
     {
         ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
         if (cond == Overflow) {


@@ -516,27 +772,56 @@ public:
         return Jump(m_assembler.jmp(ARMCondition(cond)));
     }
 
         return Jump(m_assembler.jmp(ARMCondition(cond)));
     }
 

-    Jump branchSub32(Condition cond, RegisterID src, RegisterID dest)
+    Jump branchSub32(ResultCondition cond, RegisterID src, RegisterID dest)

     {
         ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
         sub32(src, dest);
         return Jump(m_assembler.jmp(ARMCondition(cond)));
     }
 
     {
         ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
         sub32(src, dest);
         return Jump(m_assembler.jmp(ARMCondition(cond)));
     }
 

-    Jump branchSub32(Condition cond, Imm32 imm, RegisterID dest)
+    Jump branchSub32(ResultCondition cond, TrustedImm32 imm, RegisterID dest)

     {
         ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
         sub32(imm, dest);
         return Jump(m_assembler.jmp(ARMCondition(cond)));
     }
 
     {
         ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
         sub32(imm, dest);
         return Jump(m_assembler.jmp(ARMCondition(cond)));
     }
 

-    Jump branchOr32(Condition cond, RegisterID src, RegisterID dest)
+    Jump branchSub32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest)
+    {
+        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
+        sub32(src, imm, dest);
+        return Jump(m_assembler.jmp(ARMCondition(cond)));
+    }
+
+    Jump branchSub32(ResultCondition cond, RegisterID op1, RegisterID op2, RegisterID dest)
+    {
+        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
+        m_assembler.subs(dest, op1, op2);
+        return Jump(m_assembler.jmp(ARMCondition(cond)));
+    }
+
+    Jump branchNeg32(ResultCondition cond, RegisterID srcDest)
+    {
+        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
+        neg32(srcDest);
+        return Jump(m_assembler.jmp(ARMCondition(cond)));
+    }
+
+    Jump branchOr32(ResultCondition cond, RegisterID src, RegisterID dest)

     {
         ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero));
         or32(src, dest);
         return Jump(m_assembler.jmp(ARMCondition(cond)));
     }
 
     {
         ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero));
         or32(src, dest);
         return Jump(m_assembler.jmp(ARMCondition(cond)));
     }
 

+    PatchableJump patchableBranch32(RelationalCondition cond, RegisterID reg, TrustedImm32 imm)
+    {
+        internalCompare32(reg, imm);
+        Jump jump(m_assembler.loadBranchTarget(ARMRegisters::S1, ARMCondition(cond), true));
+        m_assembler.bx(ARMRegisters::S1, ARMCondition(cond));
+        return PatchableJump(jump);
+    }
+

     void breakpoint()
     {
         m_assembler.bkpt(0);
     void breakpoint()
     {
         m_assembler.bkpt(0);


@@ -544,16 +829,13 @@ public:
 
     Call nearCall()
     {
 
     Call nearCall()
     {

-        prepareCall();
-        return Call(m_assembler.jmp(ARMAssembler::AL, true), Call::LinkableNear);
+        m_assembler.loadBranchTarget(ARMRegisters::S1, ARMAssembler::AL, true);
+        return Call(m_assembler.blx(ARMRegisters::S1), Call::LinkableNear);

     }
 
     Call call(RegisterID target)
     {
     }
 
     Call call(RegisterID target)
     {

-        prepareCall();
-        move(ARMRegisters::pc, target);
-        JmpSrc jmpSrc;
-        return Call(jmpSrc, Call::None);
+        return Call(m_assembler.blx(target), Call::None);

     }
 
     void call(Address address)
     }
 
     void call(Address address)


@@ -563,104 +845,127 @@ public:
 
     void ret()
     {
 
     void ret()
     {

-        m_assembler.mov_r(ARMRegisters::pc, linkRegister);
+        m_assembler.bx(linkRegister);

     }
 
     }
 

-    void set32(Condition cond, RegisterID left, RegisterID right, RegisterID dest)
+    void compare32(RelationalCondition cond, RegisterID left, RegisterID right, RegisterID dest)

     {
     {

-        m_assembler.cmp_r(left, right);
-        m_assembler.mov_r(dest, ARMAssembler::getOp2(0));
-        m_assembler.mov_r(dest, ARMAssembler::getOp2(1), ARMCondition(cond));
+        m_assembler.cmp(left, right);
+        m_assembler.mov(dest, ARMAssembler::getOp2Byte(0));
+        m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));

     }
 
     }
 

-    void set32(Condition cond, RegisterID left, Imm32 right, RegisterID dest)
+    void compare32(RelationalCondition cond, RegisterID left, TrustedImm32 right, RegisterID dest)

     {
     {

-        m_assembler.cmp_r(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));
-        m_assembler.mov_r(dest, ARMAssembler::getOp2(0));
-        m_assembler.mov_r(dest, ARMAssembler::getOp2(1), ARMCondition(cond));
+        m_assembler.cmp(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));
+        m_assembler.mov(dest, ARMAssembler::getOp2Byte(0));
+        m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));

     }
 
     }
 

-    void set8(Condition cond, RegisterID left, RegisterID right, RegisterID dest)
+    void compare8(RelationalCondition cond, Address left, TrustedImm32 right, RegisterID dest)

     {
     {

-        // ARM doesn't have byte registers
-        set32(cond, left, right, dest);
+        load8(left, ARMRegisters::S1);
+        compare32(cond, ARMRegisters::S1, right, dest);

     }
 
     }
 

-    void set8(Condition cond, Address left, RegisterID right, RegisterID dest)
+    void test32(ResultCondition cond, RegisterID reg, TrustedImm32 mask, RegisterID dest)

     {
     {

-        // ARM doesn't have byte registers
-        load32(left, ARMRegisters::S1);
-        set32(cond, ARMRegisters::S1, right, dest);
+        if (mask.m_value == -1)
+            m_assembler.cmp(0, reg);
+        else
+            m_assembler.tst(reg, m_assembler.getImm(mask.m_value, ARMRegisters::S0));
+        m_assembler.mov(dest, ARMAssembler::getOp2Byte(0));
+        m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));

     }
 
     }
 

-    void set8(Condition cond, RegisterID left, Imm32 right, RegisterID dest)
+    void test32(ResultCondition cond, Address address, TrustedImm32 mask, RegisterID dest)

     {
     {

-        // ARM doesn't have byte registers
-        set32(cond, left, right, dest);
+        load32(address, ARMRegisters::S1);
+        test32(cond, ARMRegisters::S1, mask, dest);

     }
 
     }
 

-    void setTest32(Condition cond, Address address, Imm32 mask, RegisterID dest)
+    void test8(ResultCondition cond, Address address, TrustedImm32 mask, RegisterID dest)

     {
     {

-        load32(address, ARMRegisters::S1);
-        if (mask.m_value == -1)
-            m_assembler.cmp_r(0, ARMRegisters::S1);
-        else
-            m_assembler.tst_r(ARMRegisters::S1, m_assembler.getImm(mask.m_value, ARMRegisters::S0));
-        m_assembler.mov_r(dest, ARMAssembler::getOp2(0));
-        m_assembler.mov_r(dest, ARMAssembler::getOp2(1), ARMCondition(cond));
+        load8(address, ARMRegisters::S1);
+        test32(cond, ARMRegisters::S1, mask, dest);

     }
 
     }
 

-    void setTest8(Condition cond, Address address, Imm32 mask, RegisterID dest)
+    void add32(TrustedImm32 imm, RegisterID src, RegisterID dest)

     {
     {

-        // ARM doesn't have byte registers
-        setTest32(cond, address, mask, dest);
+        m_assembler.add(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));

     }
 
     }
 

-    void add32(Imm32 imm, RegisterID src, RegisterID dest)
+    void add32(TrustedImm32 imm, AbsoluteAddress address)

     {
     {

-        m_assembler.add_r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+        load32(address.m_ptr, ARMRegisters::S1);
+        add32(imm, ARMRegisters::S1);
+        store32(ARMRegisters::S1, address.m_ptr);

     }
 
     }
 

-    void add32(Imm32 imm, AbsoluteAddress address)
+    void add64(TrustedImm32 imm, AbsoluteAddress address)

     {
     {

-        m_assembler.ldr_un_imm(ARMRegisters::S1, reinterpret_cast<ARMWord>(address.m_ptr));
-        m_assembler.dtr_u(true, ARMRegisters::S1, ARMRegisters::S1, 0);
-        add32(imm, ARMRegisters::S1);
-        m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address.m_ptr));
-        m_assembler.dtr_u(false, ARMRegisters::S1, ARMRegisters::S0, 0);
+        ARMWord tmp;
+
+        move(TrustedImmPtr(address.m_ptr), ARMRegisters::S1);
+        m_assembler.dtrUp(ARMAssembler::LoadUint32, ARMRegisters::S0, ARMRegisters::S1, 0);
+
+        if ((tmp = ARMAssembler::getOp2(imm.m_value)) != ARMAssembler::InvalidImmediate)
+            m_assembler.adds(ARMRegisters::S0, ARMRegisters::S0, tmp);
+        else if ((tmp = ARMAssembler::getOp2(-imm.m_value)) != ARMAssembler::InvalidImmediate)
+            m_assembler.subs(ARMRegisters::S0, ARMRegisters::S0, tmp);
+        else {
+            m_assembler.adds(ARMRegisters::S0, ARMRegisters::S0, m_assembler.getImm(imm.m_value, ARMRegisters::S1));
+            move(TrustedImmPtr(address.m_ptr), ARMRegisters::S1);
+        }
+        m_assembler.dtrUp(ARMAssembler::StoreUint32, ARMRegisters::S0, ARMRegisters::S1, 0);
+
+        m_assembler.dtrUp(ARMAssembler::LoadUint32, ARMRegisters::S0, ARMRegisters::S1, sizeof(ARMWord));
+        if (imm.m_value >= 0)
+            m_assembler.adc(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
+        else
+            m_assembler.sbc(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
+        m_assembler.dtrUp(ARMAssembler::StoreUint32, ARMRegisters::S0, ARMRegisters::S1, sizeof(ARMWord));

     }
 
     }
 

-    void sub32(Imm32 imm, AbsoluteAddress address)
+    void sub32(TrustedImm32 imm, AbsoluteAddress address)

     {
     {

-        m_assembler.ldr_un_imm(ARMRegisters::S1, reinterpret_cast<ARMWord>(address.m_ptr));
-        m_assembler.dtr_u(true, ARMRegisters::S1, ARMRegisters::S1, 0);
+        load32(address.m_ptr, ARMRegisters::S1);

         sub32(imm, ARMRegisters::S1);
         sub32(imm, ARMRegisters::S1);

-        m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address.m_ptr));
-        m_assembler.dtr_u(false, ARMRegisters::S1, ARMRegisters::S0, 0);
+        store32(ARMRegisters::S1, address.m_ptr);

     }
 
     }
 

-    void load32(void* address, RegisterID dest)
+    void load32(const void* address, RegisterID dest)

     {
     {

-        m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
-        m_assembler.dtr_u(true, dest, ARMRegisters::S0, 0);
+        m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
+        m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, ARMRegisters::S0, 0);

     }
 
     }
 

-    Jump branch32(Condition cond, AbsoluteAddress left, RegisterID right)
+    Jump branch32(RelationalCondition cond, AbsoluteAddress left, RegisterID right)

     {
         load32(left.m_ptr, ARMRegisters::S1);
         return branch32(cond, ARMRegisters::S1, right);
     }
 
     {
         load32(left.m_ptr, ARMRegisters::S1);
         return branch32(cond, ARMRegisters::S1, right);
     }
 

-    Jump branch32(Condition cond, AbsoluteAddress left, Imm32 right)
+    Jump branch32(RelationalCondition cond, AbsoluteAddress left, TrustedImm32 right)

     {
         load32(left.m_ptr, ARMRegisters::S1);
         return branch32(cond, ARMRegisters::S1, right);
     }
 
     {
         load32(left.m_ptr, ARMRegisters::S1);
         return branch32(cond, ARMRegisters::S1, right);
     }
 

+    void relativeTableJump(RegisterID index, int scale)
+    {
+        ASSERT(scale >= 0 && scale <= 31);
+        m_assembler.add(ARMRegisters::pc, ARMRegisters::pc, m_assembler.lsl(index, scale));
+
+        // NOP the default prefetching
+        m_assembler.mov(ARMRegisters::r0, ARMRegisters::r0);
+    }
+

     Call call()
     {
     Call call()
     {

-        prepareCall();
-        return Call(m_assembler.jmp(ARMAssembler::AL, true), Call::Linkable);
+        ensureSpace(2 * sizeof(ARMWord), sizeof(ARMWord));
+        m_assembler.loadBranchTarget(ARMRegisters::S1, ARMAssembler::AL, true);
+        return Call(m_assembler.blx(ARMRegisters::S1), Call::Linkable);

     }
 
     Call tailRecursiveCall()
     }
 
     Call tailRecursiveCall()


@@ -673,29 +978,31 @@ public:
         return Call::fromTailJump(oldJump);
     }
 
         return Call::fromTailJump(oldJump);
     }
 

-    DataLabelPtr moveWithPatch(ImmPtr initialValue, RegisterID dest)
+    DataLabelPtr moveWithPatch(TrustedImmPtr initialValue, RegisterID dest)

     {
         DataLabelPtr dataLabel(this);
     {
         DataLabelPtr dataLabel(this);

-        m_assembler.ldr_un_imm(dest, reinterpret_cast<ARMWord>(initialValue.m_value));
+        m_assembler.ldrUniqueImmediate(dest, reinterpret_cast<ARMWord>(initialValue.m_value));

         return dataLabel;
     }
 
         return dataLabel;
     }
 

-    Jump branchPtrWithPatch(Condition cond, RegisterID left, DataLabelPtr& dataLabel, ImmPtr initialRightValue = ImmPtr(0))
+    Jump branchPtrWithPatch(RelationalCondition cond, RegisterID left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(0))

     {
     {

+        ensureSpace(3 * sizeof(ARMWord), 2 * sizeof(ARMWord));

         dataLabel = moveWithPatch(initialRightValue, ARMRegisters::S1);
         Jump jump = branch32(cond, left, ARMRegisters::S1, true);
         return jump;
     }
 
         dataLabel = moveWithPatch(initialRightValue, ARMRegisters::S1);
         Jump jump = branch32(cond, left, ARMRegisters::S1, true);
         return jump;
     }
 

-    Jump branchPtrWithPatch(Condition cond, Address left, DataLabelPtr& dataLabel, ImmPtr initialRightValue = ImmPtr(0))
+    Jump branchPtrWithPatch(RelationalCondition cond, Address left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(0))

     {
         load32(left, ARMRegisters::S1);
     {
         load32(left, ARMRegisters::S1);

+        ensureSpace(3 * sizeof(ARMWord), 2 * sizeof(ARMWord));

         dataLabel = moveWithPatch(initialRightValue, ARMRegisters::S0);
         Jump jump = branch32(cond, ARMRegisters::S0, ARMRegisters::S1, true);
         return jump;
     }
 
         dataLabel = moveWithPatch(initialRightValue, ARMRegisters::S0);
         Jump jump = branch32(cond, ARMRegisters::S0, ARMRegisters::S1, true);
         return jump;
     }
 

-    DataLabelPtr storePtrWithPatch(ImmPtr initialValue, ImplicitAddress address)
+    DataLabelPtr storePtrWithPatch(TrustedImmPtr initialValue, ImplicitAddress address)

     {
         DataLabelPtr dataLabel = moveWithPatch(initialValue, ARMRegisters::S1);
         store32(ARMRegisters::S1, address);
     {
         DataLabelPtr dataLabel = moveWithPatch(initialValue, ARMRegisters::S1);
         store32(ARMRegisters::S1, address);


@@ -704,39 +1011,82 @@ public:
 
     DataLabelPtr storePtrWithPatch(ImplicitAddress address)
     {
 
     DataLabelPtr storePtrWithPatch(ImplicitAddress address)
     {

-        return storePtrWithPatch(ImmPtr(0), address);
+        return storePtrWithPatch(TrustedImmPtr(0), address);

     }
 
     // Floating point operators
     }
 
     // Floating point operators

-    bool supportsFloatingPoint() const
+    static bool supportsFloatingPoint()

     {
         return s_isVFPPresent;
     }
 
     {
         return s_isVFPPresent;
     }
 

-    bool supportsFloatingPointTruncate() const
+    static bool supportsFloatingPointTruncate()

     {
         return false;
     }
 
     {
         return false;
     }
 

+    static bool supportsFloatingPointSqrt()
+    {
+        return s_isVFPPresent;
+    }
+    static bool supportsFloatingPointAbs() { return false; }
+
+    void loadFloat(BaseIndex address, FPRegisterID dest)
+    {
+        m_assembler.baseIndexTransferFloat(ARMAssembler::LoadFloat, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
+    }
+

     void loadDouble(ImplicitAddress address, FPRegisterID dest)
     {
     void loadDouble(ImplicitAddress address, FPRegisterID dest)
     {

-        m_assembler.doubleTransfer(true, dest, address.base, address.offset);
+        m_assembler.dataTransferFloat(ARMAssembler::LoadDouble, dest, address.base, address.offset);

     }
 
     }
 

-    void loadDouble(void* address, FPRegisterID dest)
+    void loadDouble(BaseIndex address, FPRegisterID dest)

     {
     {

-        m_assembler.ldr_un_imm(ARMRegisters::S0, (ARMWord)address);
-        m_assembler.fdtr_u(true, dest, ARMRegisters::S0, 0);
+        m_assembler.baseIndexTransferFloat(ARMAssembler::LoadDouble, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
+    }
+
+    void loadDouble(const void* address, FPRegisterID dest)
+    {
+        move(TrustedImm32(reinterpret_cast<ARMWord>(address)), ARMRegisters::S0);
+        m_assembler.doubleDtrUp(ARMAssembler::LoadDouble, dest, ARMRegisters::S0, 0);
+    }
+
+    void storeFloat(FPRegisterID src, BaseIndex address)
+    {
+        m_assembler.baseIndexTransferFloat(ARMAssembler::StoreFloat, src, address.base, address.index, static_cast<int>(address.scale), address.offset);

     }
 
     void storeDouble(FPRegisterID src, ImplicitAddress address)
     {
     }
 
     void storeDouble(FPRegisterID src, ImplicitAddress address)
     {

-        m_assembler.doubleTransfer(false, src, address.base, address.offset);
+        m_assembler.dataTransferFloat(ARMAssembler::StoreDouble, src, address.base, address.offset);
+    }
+
+    void storeDouble(FPRegisterID src, BaseIndex address)
+    {
+        m_assembler.baseIndexTransferFloat(ARMAssembler::StoreDouble, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
+    }
+
+    void storeDouble(FPRegisterID src, const void* address)
+    {
+        move(TrustedImm32(reinterpret_cast<ARMWord>(address)), ARMRegisters::S0);
+        m_assembler.dataTransferFloat(ARMAssembler::StoreDouble, src, ARMRegisters::S0, 0);
+    }
+
+    void moveDouble(FPRegisterID src, FPRegisterID dest)
+    {
+        if (src != dest)
+            m_assembler.vmov_f64(dest, src);

     }
 
     void addDouble(FPRegisterID src, FPRegisterID dest)
     {
     }
 
     void addDouble(FPRegisterID src, FPRegisterID dest)
     {

-        m_assembler.faddd_r(dest, dest, src);
+        m_assembler.vadd_f64(dest, dest, src);
+    }
+
+    void addDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+    {
+        m_assembler.vadd_f64(dest, op1, op2);

     }
 
     void addDouble(Address src, FPRegisterID dest)
     }
 
     void addDouble(Address src, FPRegisterID dest)


@@ -745,21 +1095,37 @@ public:
         addDouble(ARMRegisters::SD0, dest);
     }
 
         addDouble(ARMRegisters::SD0, dest);
     }
 

+    void addDouble(AbsoluteAddress address, FPRegisterID dest)
+    {
+        loadDouble(address.m_ptr, ARMRegisters::SD0);
+        addDouble(ARMRegisters::SD0, dest);
+    }
+

     void divDouble(FPRegisterID src, FPRegisterID dest)
     {
     void divDouble(FPRegisterID src, FPRegisterID dest)
     {

-        m_assembler.fdivd_r(dest, dest, src);
+        m_assembler.vdiv_f64(dest, dest, src);
+    }
+
+    void divDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+    {
+        m_assembler.vdiv_f64(dest, op1, op2);

     }
 
     void divDouble(Address src, FPRegisterID dest)
     {
     }
 
     void divDouble(Address src, FPRegisterID dest)
     {

-        ASSERT_NOT_REACHED(); // Untested
+        RELEASE_ASSERT_NOT_REACHED(); // Untested

         loadDouble(src, ARMRegisters::SD0);
         divDouble(ARMRegisters::SD0, dest);
     }
 
     void subDouble(FPRegisterID src, FPRegisterID dest)
     {
         loadDouble(src, ARMRegisters::SD0);
         divDouble(ARMRegisters::SD0, dest);
     }
 
     void subDouble(FPRegisterID src, FPRegisterID dest)
     {

-        m_assembler.fsubd_r(dest, dest, src);
+        m_assembler.vsub_f64(dest, dest, src);
+    }
+
+    void subDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+    {
+        m_assembler.vsub_f64(dest, op1, op2);

     }
 
     void subDouble(Address src, FPRegisterID dest)
     }
 
     void subDouble(Address src, FPRegisterID dest)


@@ -770,7 +1136,7 @@ public:
 
     void mulDouble(FPRegisterID src, FPRegisterID dest)
     {
 
     void mulDouble(FPRegisterID src, FPRegisterID dest)
     {

-        m_assembler.fmuld_r(dest, dest, src);
+        m_assembler.vmul_f64(dest, dest, src);

     }
 
     void mulDouble(Address src, FPRegisterID dest)
     }
 
     void mulDouble(Address src, FPRegisterID dest)


@@ -779,35 +1145,61 @@ public:
         mulDouble(ARMRegisters::SD0, dest);
     }
 
         mulDouble(ARMRegisters::SD0, dest);
     }
 

+    void mulDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+    {
+        m_assembler.vmul_f64(dest, op1, op2);
+    }
+
+    void sqrtDouble(FPRegisterID src, FPRegisterID dest)
+    {
+        m_assembler.vsqrt_f64(dest, src);
+    }
+    
+    void absDouble(FPRegisterID src, FPRegisterID dest)
+    {
+        m_assembler.vabs_f64(dest, src);
+    }
+
+    void negateDouble(FPRegisterID src, FPRegisterID dest)
+    {
+        m_assembler.vneg_f64(dest, src);
+    }
+

     void convertInt32ToDouble(RegisterID src, FPRegisterID dest)
     {
     void convertInt32ToDouble(RegisterID src, FPRegisterID dest)
     {

-        m_assembler.fmsr_r(dest, src);
-        m_assembler.fsitod_r(dest, dest);
+        m_assembler.vmov_vfp32(dest << 1, src);
+        m_assembler.vcvt_f64_s32(dest, dest << 1);

     }
 
     void convertInt32ToDouble(Address src, FPRegisterID dest)
     {
     }
 
     void convertInt32ToDouble(Address src, FPRegisterID dest)
     {

-        ASSERT_NOT_REACHED(); // Untested
-        // flds does not worth the effort here

         load32(src, ARMRegisters::S1);
         convertInt32ToDouble(ARMRegisters::S1, dest);
     }
 
     void convertInt32ToDouble(AbsoluteAddress src, FPRegisterID dest)
     {
         load32(src, ARMRegisters::S1);
         convertInt32ToDouble(ARMRegisters::S1, dest);
     }
 
     void convertInt32ToDouble(AbsoluteAddress src, FPRegisterID dest)
     {

-        ASSERT_NOT_REACHED(); // Untested
-        // flds does not worth the effort here
-        m_assembler.ldr_un_imm(ARMRegisters::S1, (ARMWord)src.m_ptr);
-        m_assembler.dtr_u(true, ARMRegisters::S1, ARMRegisters::S1, 0);
+        move(TrustedImmPtr(src.m_ptr), ARMRegisters::S1);
+        load32(Address(ARMRegisters::S1), ARMRegisters::S1);

         convertInt32ToDouble(ARMRegisters::S1, dest);
     }
 
         convertInt32ToDouble(ARMRegisters::S1, dest);
     }
 

+    void convertFloatToDouble(FPRegisterID src, FPRegisterID dst)
+    {
+        m_assembler.vcvt_f64_f32(dst, src);
+    }
+
+    void convertDoubleToFloat(FPRegisterID src, FPRegisterID dst)
+    {
+        m_assembler.vcvt_f32_f64(dst, src);
+    }
+

     Jump branchDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right)
     {
     Jump branchDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right)
     {

-        m_assembler.fcmpd_r(left, right);
-        m_assembler.fmstat();
+        m_assembler.vcmp_f64(left, right);
+        m_assembler.vmrs_apsr();

         if (cond & DoubleConditionBitSpecial)
         if (cond & DoubleConditionBitSpecial)

-            m_assembler.cmp_r(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::VS);
+            m_assembler.cmp(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::VS);

         return Jump(m_assembler.jmp(static_cast<ARMAssembler::Condition>(cond & ~DoubleConditionMask)));
     }
 
         return Jump(m_assembler.jmp(static_cast<ARMAssembler::Condition>(cond & ~DoubleConditionMask)));
     }
 


@@ -815,39 +1207,134 @@ public:
     // If the result is not representable as a 32 bit value, branch.
     // May also branch for some values that are representable in 32 bits
     // (specifically, in this case, INT_MIN).
     // If the result is not representable as a 32 bit value, branch.
     // May also branch for some values that are representable in 32 bits
     // (specifically, in this case, INT_MIN).

-    Jump branchTruncateDoubleToInt32(FPRegisterID src, RegisterID dest)
+    enum BranchTruncateType { BranchIfTruncateFailed, BranchIfTruncateSuccessful };
+    Jump branchTruncateDoubleToInt32(FPRegisterID src, RegisterID dest, BranchTruncateType branchType = BranchIfTruncateFailed)

     {
     {

-        UNUSED_PARAM(src);
-        UNUSED_PARAM(dest);
-        ASSERT_NOT_REACHED();
-        return jump();
+        truncateDoubleToInt32(src, dest);
+
+        m_assembler.add(ARMRegisters::S0, dest, ARMAssembler::getOp2Byte(1));
+        m_assembler.bic(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(1));
+
+        ARMWord w = ARMAssembler::getOp2(0x80000000);
+        ASSERT(w != ARMAssembler::InvalidImmediate);
+        m_assembler.cmp(ARMRegisters::S0, w);
+        return Jump(m_assembler.jmp(branchType == BranchIfTruncateFailed ? ARMAssembler::EQ : ARMAssembler::NE));
+    }
+
+    Jump branchTruncateDoubleToUint32(FPRegisterID src, RegisterID dest, BranchTruncateType branchType = BranchIfTruncateFailed)
+    {
+        truncateDoubleToUint32(src, dest);
+
+        m_assembler.add(ARMRegisters::S0, dest, ARMAssembler::getOp2Byte(1));
+        m_assembler.bic(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(1));
+
+        m_assembler.cmp(ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
+        return Jump(m_assembler.jmp(branchType == BranchIfTruncateFailed ? ARMAssembler::EQ : ARMAssembler::NE));
+    }
+
+    // Result is undefined if the value is outside of the integer range.
+    void truncateDoubleToInt32(FPRegisterID src, RegisterID dest)
+    {
+        m_assembler.vcvt_s32_f64(ARMRegisters::SD0 << 1, src);
+        m_assembler.vmov_arm32(dest, ARMRegisters::SD0 << 1);
+    }
+
+    void truncateDoubleToUint32(FPRegisterID src, RegisterID dest)
+    {
+        m_assembler.vcvt_u32_f64(ARMRegisters::SD0 << 1, src);
+        m_assembler.vmov_arm32(dest, ARMRegisters::SD0 << 1);

     }
 
     // Convert 'src' to an integer, and places the resulting 'dest'.
     // If the result is not representable as a 32 bit value, branch.
     // May also branch for some values that are representable in 32 bits
     // (specifically, in this case, 0).
     }
 
     // Convert 'src' to an integer, and places the resulting 'dest'.
     // If the result is not representable as a 32 bit value, branch.
     // May also branch for some values that are representable in 32 bits
     // (specifically, in this case, 0).

-    void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID fpTemp)
+    void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID, bool negZeroCheck = true)

     {
     {

-        m_assembler.ftosid_r(ARMRegisters::SD0, src);
-        m_assembler.fmrs_r(dest, ARMRegisters::SD0);
+        m_assembler.vcvt_s32_f64(ARMRegisters::SD0 << 1, src);
+        m_assembler.vmov_arm32(dest, ARMRegisters::SD0 << 1);

 
         // Convert the integer result back to float & compare to the original value - if not equal or unordered (NaN) then jump.
 
         // Convert the integer result back to float & compare to the original value - if not equal or unordered (NaN) then jump.

-        m_assembler.fsitod_r(ARMRegisters::SD0, ARMRegisters::SD0);
+        m_assembler.vcvt_f64_s32(ARMRegisters::SD0, ARMRegisters::SD0 << 1);

         failureCases.append(branchDouble(DoubleNotEqualOrUnordered, src, ARMRegisters::SD0));
 
         // If the result is zero, it might have been -0.0, and 0.0 equals to -0.0
         failureCases.append(branchDouble(DoubleNotEqualOrUnordered, src, ARMRegisters::SD0));
 
         // If the result is zero, it might have been -0.0, and 0.0 equals to -0.0

-        failureCases.append(branchTest32(Zero, dest));
+        if (negZeroCheck)
+            failureCases.append(branchTest32(Zero, dest));
+    }
+
+    Jump branchDoubleNonZero(FPRegisterID reg, FPRegisterID scratch)
+    {
+        m_assembler.mov(ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
+        convertInt32ToDouble(ARMRegisters::S0, scratch);
+        return branchDouble(DoubleNotEqual, reg, scratch);
+    }
+
+    Jump branchDoubleZeroOrNaN(FPRegisterID reg, FPRegisterID scratch)
+    {
+        m_assembler.mov(ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
+        convertInt32ToDouble(ARMRegisters::S0, scratch);
+        return branchDouble(DoubleEqualOrUnordered, reg, scratch);
+    }
+
+    // Invert a relational condition, e.g. == becomes !=, < becomes >=, etc.
+    static RelationalCondition invert(RelationalCondition cond)
+    {
+        ASSERT((static_cast<uint32_t>(cond & 0x0fffffff)) == 0 && static_cast<uint32_t>(cond) < static_cast<uint32_t>(ARMAssembler::AL));
+        return static_cast<RelationalCondition>(cond ^ 0x10000000);

     }
 
     }
 

-    void zeroDouble(FPRegisterID srcDest)
+    void nop()

     {
     {

-        m_assembler.mov_r(ARMRegisters::S0, ARMAssembler::getOp2(0));
-        convertInt32ToDouble(ARMRegisters::S0, srcDest);
+        m_assembler.nop();
+    }
+
+    static FunctionPtr readCallTarget(CodeLocationCall call)
+    {
+        return FunctionPtr(reinterpret_cast<void(*)()>(ARMAssembler::readCallTarget(call.dataLocation())));
+    }
+
+    static void replaceWithJump(CodeLocationLabel instructionStart, CodeLocationLabel destination)
+    {
+        ARMAssembler::replaceWithJump(instructionStart.dataLocation(), destination.dataLocation());
+    }
+    
+    static ptrdiff_t maxJumpReplacementSize()
+    {
+        ARMAssembler::maxJumpReplacementSize();
+        return 0;
+    }
+
+    static bool canJumpReplacePatchableBranchPtrWithPatch() { return false; }
+
+    static CodeLocationLabel startOfPatchableBranchPtrWithPatchOnAddress(CodeLocationDataLabelPtr)
+    {
+        UNREACHABLE_FOR_PLATFORM();
+        return CodeLocationLabel();
+    }
+
+    static CodeLocationLabel startOfBranchPtrWithPatchOnRegister(CodeLocationDataLabelPtr label)
+    {
+        return label.labelAtOffset(0);
+    }
+
+    static void revertJumpReplacementToBranchPtrWithPatch(CodeLocationLabel instructionStart, RegisterID reg, void* initialValue)
+    {
+        ARMAssembler::revertBranchPtrWithPatch(instructionStart.dataLocation(), reg, reinterpret_cast<uintptr_t>(initialValue) & 0xffff);
+    }
+
+    static void revertJumpReplacementToPatchableBranchPtrWithPatch(CodeLocationLabel, Address, void*)
+    {
+        UNREACHABLE_FOR_PLATFORM();

     }
 
 protected:
     }
 
 protected:

-    ARMAssembler::Condition ARMCondition(Condition cond)
+    ARMAssembler::Condition ARMCondition(RelationalCondition cond)
+    {
+        return static_cast<ARMAssembler::Condition>(cond);
+    }
+
+    ARMAssembler::Condition ARMCondition(ResultCondition cond)

     {
         return static_cast<ARMAssembler::Condition>(cond);
     }
     {
         return static_cast<ARMAssembler::Condition>(cond);
     }


@@ -862,55 +1349,28 @@ protected:
         return m_assembler.sizeOfConstantPool();
     }
 
         return m_assembler.sizeOfConstantPool();
     }
 

-    void prepareCall()
-    {
-        ensureSpace(2 * sizeof(ARMWord), sizeof(ARMWord));
-
-        m_assembler.mov_r(linkRegister, ARMRegisters::pc);
-    }
-

     void call32(RegisterID base, int32_t offset)
     {
     void call32(RegisterID base, int32_t offset)
     {

-        if (base == ARMRegisters::sp)
-            offset += 4;
-
-        if (offset >= 0) {
-            if (offset <= 0xfff) {
-                prepareCall();
-                m_assembler.dtr_u(true, ARMRegisters::pc, base, offset);
-            } else if (offset <= 0xfffff) {
-                m_assembler.add_r(ARMRegisters::S0, base, ARMAssembler::OP2_IMM | (offset >> 12) | (10 << 8));
-                prepareCall();
-                m_assembler.dtr_u(true, ARMRegisters::pc, ARMRegisters::S0, offset & 0xfff);
-            } else {
-                ARMWord reg = m_assembler.getImm(offset, ARMRegisters::S0);
-                prepareCall();
-                m_assembler.dtr_ur(true, ARMRegisters::pc, base, reg);
-            }
-        } else  {
-            offset = -offset;
-            if (offset <= 0xfff) {
-                prepareCall();
-                m_assembler.dtr_d(true, ARMRegisters::pc, base, offset);
-            } else if (offset <= 0xfffff) {
-                m_assembler.sub_r(ARMRegisters::S0, base, ARMAssembler::OP2_IMM | (offset >> 12) | (10 << 8));
-                prepareCall();
-                m_assembler.dtr_d(true, ARMRegisters::pc, ARMRegisters::S0, offset & 0xfff);
-            } else {
-                ARMWord reg = m_assembler.getImm(offset, ARMRegisters::S0);
-                prepareCall();
-                m_assembler.dtr_dr(true, ARMRegisters::pc, base, reg);
-            }
-        }
+        load32(Address(base, offset), ARMRegisters::S1);
+        m_assembler.blx(ARMRegisters::S1);

     }
 
 private:
     friend class LinkBuffer;
     friend class RepatchBuffer;
 
     }
 
 private:
     friend class LinkBuffer;
     friend class RepatchBuffer;
 

+    void internalCompare32(RegisterID left, TrustedImm32 right)
+    {
+        ARMWord tmp = (static_cast<unsigned>(right.m_value) == 0x80000000) ? ARMAssembler::InvalidImmediate : m_assembler.getOp2(-right.m_value);
+        if (tmp != ARMAssembler::InvalidImmediate)
+            m_assembler.cmn(left, tmp);
+        else
+            m_assembler.cmp(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));
+    }
+

     static void linkCall(void* code, Call call, FunctionPtr function)
     {
     static void linkCall(void* code, Call call, FunctionPtr function)
     {

-        ARMAssembler::linkCall(code, call.m_jmp, function.value());
+        ARMAssembler::linkCall(code, call.m_label, function.value());

     }
 
     static void repatchCall(CodeLocationCall call, CodeLocationLabel destination)
     }
 
     static void repatchCall(CodeLocationCall call, CodeLocationLabel destination)