COMPILE_ASSERT(!(DoubleConditionBitSpecial & DoubleConditionMask), DoubleConditionBitSpecial_should_not_interfere_with_ARMAssembler_Condition_codes);
public:
typedef ARMRegisters::FPRegisterID FPRegisterID;
- static const int MaximumCompactPtrAlignedAddressOffset = 0x7FFFFFFF;
enum RelationalCondition {
Equal = ARMAssembler::EQ,
enum ResultCondition {
Overflow = ARMAssembler::VS,
Signed = ARMAssembler::MI,
+ PositiveOrZero = ARMAssembler::PL,
Zero = ARMAssembler::EQ,
NonZero = ARMAssembler::NE
};
void add32(RegisterID src, RegisterID dest)
{
- m_assembler.adds_r(dest, dest, src);
+ m_assembler.adds(dest, dest, src);
+ }
+
+ void add32(RegisterID op1, RegisterID op2, RegisterID dest)
+ {
+ m_assembler.adds(dest, op1, op2);
}
void add32(TrustedImm32 imm, Address address)
void add32(TrustedImm32 imm, RegisterID dest)
{
- m_assembler.adds_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+ m_assembler.adds(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+ }
+
+ void add32(AbsoluteAddress src, RegisterID dest)
+ {
+ move(TrustedImmPtr(src.m_ptr), ARMRegisters::S1);
+ m_assembler.dtrUp(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0);
+ add32(ARMRegisters::S1, dest);
}
void add32(Address src, RegisterID dest)
void add32(RegisterID src, TrustedImm32 imm, RegisterID dest)
{
- m_assembler.adds_r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+ m_assembler.adds(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
}
void and32(RegisterID src, RegisterID dest)
{
- m_assembler.ands_r(dest, dest, src);
+ m_assembler.bitAnds(dest, dest, src);
+ }
+
+ void and32(RegisterID op1, RegisterID op2, RegisterID dest)
+ {
+ m_assembler.bitAnds(dest, op1, op2);
}
void and32(TrustedImm32 imm, RegisterID dest)
{
ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true);
- if (w & ARMAssembler::OP2_INV_IMM)
- m_assembler.bics_r(dest, dest, w & ~ARMAssembler::OP2_INV_IMM);
+ if (w & ARMAssembler::Op2InvertedImmediate)
+ m_assembler.bics(dest, dest, w & ~ARMAssembler::Op2InvertedImmediate);
else
- m_assembler.ands_r(dest, dest, w);
+ m_assembler.bitAnds(dest, dest, w);
}
void and32(TrustedImm32 imm, RegisterID src, RegisterID dest)
{
ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true);
- if (w & ARMAssembler::OP2_INV_IMM)
- m_assembler.bics_r(dest, src, w & ~ARMAssembler::OP2_INV_IMM);
+ if (w & ARMAssembler::Op2InvertedImmediate)
+ m_assembler.bics(dest, src, w & ~ARMAssembler::Op2InvertedImmediate);
else
- m_assembler.ands_r(dest, src, w);
+ m_assembler.bitAnds(dest, src, w);
}
- void lshift32(RegisterID shift_amount, RegisterID dest)
+ void and32(Address src, RegisterID dest)
{
- ARMWord w = ARMAssembler::getOp2(0x1f);
- ASSERT(w != ARMAssembler::INVALID_IMM);
- m_assembler.and_r(ARMRegisters::S0, shift_amount, w);
+ load32(src, ARMRegisters::S1);
+ and32(ARMRegisters::S1, dest);
+ }
- m_assembler.movs_r(dest, m_assembler.lsl_r(dest, ARMRegisters::S0));
+ void lshift32(RegisterID shiftAmount, RegisterID dest)
+ {
+ lshift32(dest, shiftAmount, dest);
+ }
+
+ void lshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
+ {
+ ARMWord w = ARMAssembler::getOp2Byte(0x1f);
+ m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w);
+
+ m_assembler.movs(dest, m_assembler.lslRegister(src, ARMRegisters::S0));
}
void lshift32(TrustedImm32 imm, RegisterID dest)
{
- m_assembler.movs_r(dest, m_assembler.lsl(dest, imm.m_value & 0x1f));
+ m_assembler.movs(dest, m_assembler.lsl(dest, imm.m_value & 0x1f));
}
void lshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
{
- m_assembler.movs_r(dest, m_assembler.lsl(src, imm.m_value & 0x1f));
+ m_assembler.movs(dest, m_assembler.lsl(src, imm.m_value & 0x1f));
}
- void mul32(RegisterID src, RegisterID dest)
+ void mul32(RegisterID op1, RegisterID op2, RegisterID dest)
{
- if (src == dest) {
- move(src, ARMRegisters::S0);
- src = ARMRegisters::S0;
+ if (op2 == dest) {
+ if (op1 == dest) {
+ move(op2, ARMRegisters::S0);
+ op2 = ARMRegisters::S0;
+ } else {
+ // Swap the operands.
+ RegisterID tmp = op1;
+ op1 = op2;
+ op2 = tmp;
+ }
}
- m_assembler.muls_r(dest, dest, src);
+ m_assembler.muls(dest, op1, op2);
+ }
+
+ void mul32(RegisterID src, RegisterID dest)
+ {
+ mul32(src, dest, dest);
}
void mul32(TrustedImm32 imm, RegisterID src, RegisterID dest)
{
move(imm, ARMRegisters::S0);
- m_assembler.muls_r(dest, src, ARMRegisters::S0);
+ m_assembler.muls(dest, src, ARMRegisters::S0);
}
void neg32(RegisterID srcDest)
{
- m_assembler.rsbs_r(srcDest, srcDest, ARMAssembler::getOp2(0));
+ m_assembler.rsbs(srcDest, srcDest, ARMAssembler::getOp2Byte(0));
}
void or32(RegisterID src, RegisterID dest)
{
- m_assembler.orrs_r(dest, dest, src);
+ m_assembler.orrs(dest, dest, src);
+ }
+
+ void or32(RegisterID src, AbsoluteAddress dest)
+ {
+ move(TrustedImmPtr(dest.m_ptr), ARMRegisters::S0);
+ load32(Address(ARMRegisters::S0), ARMRegisters::S1);
+ or32(src, ARMRegisters::S1);
+ store32(ARMRegisters::S1, ARMRegisters::S0);
}
void or32(TrustedImm32 imm, RegisterID dest)
{
- m_assembler.orrs_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+ m_assembler.orrs(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
}
void or32(TrustedImm32 imm, RegisterID src, RegisterID dest)
{
- m_assembler.orrs_r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+ m_assembler.orrs(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
}
void or32(RegisterID op1, RegisterID op2, RegisterID dest)
{
- m_assembler.orrs_r(dest, op1, op2);
+ m_assembler.orrs(dest, op1, op2);
}
- void rshift32(RegisterID shift_amount, RegisterID dest)
+ void rshift32(RegisterID shiftAmount, RegisterID dest)
{
- ARMWord w = ARMAssembler::getOp2(0x1f);
- ASSERT(w != ARMAssembler::INVALID_IMM);
- m_assembler.and_r(ARMRegisters::S0, shift_amount, w);
+ rshift32(dest, shiftAmount, dest);
+ }
- m_assembler.movs_r(dest, m_assembler.asr_r(dest, ARMRegisters::S0));
+ void rshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
+ {
+ ARMWord w = ARMAssembler::getOp2Byte(0x1f);
+ m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w);
+
+ m_assembler.movs(dest, m_assembler.asrRegister(src, ARMRegisters::S0));
}
-
+
void rshift32(TrustedImm32 imm, RegisterID dest)
{
rshift32(dest, imm, dest);
void rshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
{
- m_assembler.movs_r(dest, m_assembler.asr(src, imm.m_value & 0x1f));
+ m_assembler.movs(dest, m_assembler.asr(src, imm.m_value & 0x1f));
}
-
- void urshift32(RegisterID shift_amount, RegisterID dest)
+
+ void urshift32(RegisterID shiftAmount, RegisterID dest)
{
- ARMWord w = ARMAssembler::getOp2(0x1f);
- ASSERT(w != ARMAssembler::INVALID_IMM);
- m_assembler.and_r(ARMRegisters::S0, shift_amount, w);
-
- m_assembler.movs_r(dest, m_assembler.lsr_r(dest, ARMRegisters::S0));
+ urshift32(dest, shiftAmount, dest);
}
-
+
+ void urshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
+ {
+ ARMWord w = ARMAssembler::getOp2Byte(0x1f);
+ m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w);
+
+ m_assembler.movs(dest, m_assembler.lsrRegister(src, ARMRegisters::S0));
+ }
+
void urshift32(TrustedImm32 imm, RegisterID dest)
{
- m_assembler.movs_r(dest, m_assembler.lsr(dest, imm.m_value & 0x1f));
+ m_assembler.movs(dest, m_assembler.lsr(dest, imm.m_value & 0x1f));
}
void urshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
{
- m_assembler.movs_r(dest, m_assembler.lsr(src, imm.m_value & 0x1f));
+ m_assembler.movs(dest, m_assembler.lsr(src, imm.m_value & 0x1f));
}
void sub32(RegisterID src, RegisterID dest)
{
- m_assembler.subs_r(dest, dest, src);
+ m_assembler.subs(dest, dest, src);
}
void sub32(TrustedImm32 imm, RegisterID dest)
{
- m_assembler.subs_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+ m_assembler.subs(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
}
void sub32(TrustedImm32 imm, Address address)
void sub32(RegisterID src, TrustedImm32 imm, RegisterID dest)
{
- m_assembler.subs_r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+ m_assembler.subs(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
}
void xor32(RegisterID src, RegisterID dest)
{
- m_assembler.eors_r(dest, dest, src);
+ m_assembler.eors(dest, dest, src);
+ }
+
+ void xor32(RegisterID op1, RegisterID op2, RegisterID dest)
+ {
+ m_assembler.eors(dest, op1, op2);
}
void xor32(TrustedImm32 imm, RegisterID dest)
{
if (imm.m_value == -1)
- m_assembler.mvns_r(dest, dest);
+ m_assembler.mvns(dest, dest);
else
- m_assembler.eors_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+ m_assembler.eors(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
}
void xor32(TrustedImm32 imm, RegisterID src, RegisterID dest)
{
if (imm.m_value == -1)
- m_assembler.mvns_r(dest, src);
+ m_assembler.mvns(dest, src);
else
- m_assembler.eors_r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+ m_assembler.eors(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
}
void countLeadingZeros32(RegisterID src, RegisterID dest)
{
#if WTF_ARM_ARCH_AT_LEAST(5)
- m_assembler.clz_r(dest, src);
+ m_assembler.clz(dest, src);
#else
UNUSED_PARAM(src);
UNUSED_PARAM(dest);
- ASSERT_NOT_REACHED();
+ RELEASE_ASSERT_NOT_REACHED();
#endif
}
void load8(ImplicitAddress address, RegisterID dest)
{
- m_assembler.dataTransfer32(true, dest, address.base, address.offset, true);
+ m_assembler.dataTransfer32(ARMAssembler::LoadUint8, dest, address.base, address.offset);
}
void load8(BaseIndex address, RegisterID dest)
{
- m_assembler.baseIndexTransfer32(true, dest, address.base, address.index, static_cast<int>(address.scale), address.offset, true);
+ m_assembler.baseIndexTransfer32(ARMAssembler::LoadUint8, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
+ }
+
+ void load8Signed(BaseIndex address, RegisterID dest)
+ {
+ m_assembler.baseIndexTransfer16(ARMAssembler::LoadInt8, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
+ }
+
+ void load16(ImplicitAddress address, RegisterID dest)
+ {
+ m_assembler.dataTransfer16(ARMAssembler::LoadUint16, dest, address.base, address.offset);
+ }
+
+ void load16(BaseIndex address, RegisterID dest)
+ {
+ m_assembler.baseIndexTransfer16(ARMAssembler::LoadUint16, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
+ }
+
+ void load16Signed(BaseIndex address, RegisterID dest)
+ {
+ m_assembler.baseIndexTransfer16(ARMAssembler::LoadInt16, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
}
void load32(ImplicitAddress address, RegisterID dest)
{
- m_assembler.dataTransfer32(true, dest, address.base, address.offset);
+ m_assembler.dataTransfer32(ARMAssembler::LoadUint32, dest, address.base, address.offset);
}
void load32(BaseIndex address, RegisterID dest)
{
- m_assembler.baseIndexTransfer32(true, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
+ m_assembler.baseIndexTransfer32(ARMAssembler::LoadUint32, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
}
#if CPU(ARMV5_OR_LOWER)
load16(address, dest);
}
- DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest)
+ ConvertibleLoadLabel convertibleLoadPtr(Address address, RegisterID dest)
{
- DataLabel32 dataLabel(this);
- m_assembler.ldr_un_imm(ARMRegisters::S0, 0);
- m_assembler.dtr_ur(true, dest, address.base, ARMRegisters::S0);
- return dataLabel;
+ ConvertibleLoadLabel result(this);
+ ASSERT(address.offset >= 0 && address.offset <= 255);
+ m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, address.base, address.offset);
+ return result;
}
-
- DataLabelCompact load32WithCompactAddressOffsetPatch(Address address, RegisterID dest)
+
+ DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest)
{
- DataLabelCompact dataLabel(this);
- load32WithAddressOffsetPatch(address, dest);
+ DataLabel32 dataLabel(this);
+ m_assembler.ldrUniqueImmediate(ARMRegisters::S0, 0);
+ m_assembler.dtrUpRegister(ARMAssembler::LoadUint32, dest, address.base, ARMRegisters::S0);
return dataLabel;
}
- void load16(BaseIndex address, RegisterID dest)
+ static bool isCompactPtrAlignedAddressOffset(ptrdiff_t value)
{
- m_assembler.add_r(ARMRegisters::S1, address.base, m_assembler.lsl(address.index, address.scale));
- load16(Address(ARMRegisters::S1, address.offset), dest);
+ return value >= -4095 && value <= 4095;
}
-
- void load16(ImplicitAddress address, RegisterID dest)
+
+ DataLabelCompact load32WithCompactAddressOffsetPatch(Address address, RegisterID dest)
{
+ DataLabelCompact dataLabel(this);
+ ASSERT(isCompactPtrAlignedAddressOffset(address.offset));
if (address.offset >= 0)
- m_assembler.ldrh_u(dest, address.base, m_assembler.getOffsetForHalfwordDataTransfer(address.offset, ARMRegisters::S0));
+ m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, address.base, address.offset);
else
- m_assembler.ldrh_d(dest, address.base, m_assembler.getOffsetForHalfwordDataTransfer(-address.offset, ARMRegisters::S0));
+ m_assembler.dtrDown(ARMAssembler::LoadUint32, dest, address.base, address.offset);
+ return dataLabel;
}
DataLabel32 store32WithAddressOffsetPatch(RegisterID src, Address address)
{
DataLabel32 dataLabel(this);
- m_assembler.ldr_un_imm(ARMRegisters::S0, 0);
- m_assembler.dtr_ur(false, src, address.base, ARMRegisters::S0);
+ m_assembler.ldrUniqueImmediate(ARMRegisters::S0, 0);
+ m_assembler.dtrUpRegister(ARMAssembler::StoreUint32, src, address.base, ARMRegisters::S0);
return dataLabel;
}
+ void store8(RegisterID src, BaseIndex address)
+ {
+ m_assembler.baseIndexTransfer32(ARMAssembler::StoreUint8, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
+ }
+
+ void store8(TrustedImm32 imm, const void* address)
+ {
+ move(TrustedImm32(reinterpret_cast<ARMWord>(address)), ARMRegisters::S0);
+ move(imm, ARMRegisters::S1);
+ m_assembler.dtrUp(ARMAssembler::StoreUint8, ARMRegisters::S1, ARMRegisters::S0, 0);
+ }
+
+ void store16(RegisterID src, BaseIndex address)
+ {
+ m_assembler.baseIndexTransfer16(ARMAssembler::StoreUint16, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
+ }
+
void store32(RegisterID src, ImplicitAddress address)
{
- m_assembler.dataTransfer32(false, src, address.base, address.offset);
+ m_assembler.dataTransfer32(ARMAssembler::StoreUint32, src, address.base, address.offset);
}
void store32(RegisterID src, BaseIndex address)
{
- m_assembler.baseIndexTransfer32(false, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
+ m_assembler.baseIndexTransfer32(ARMAssembler::StoreUint32, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
}
void store32(TrustedImm32 imm, ImplicitAddress address)
{
- if (imm.m_isPointer)
- m_assembler.ldr_un_imm(ARMRegisters::S1, imm.m_value);
- else
- move(imm, ARMRegisters::S1);
+ move(imm, ARMRegisters::S1);
store32(ARMRegisters::S1, address);
}
- void store32(RegisterID src, void* address)
+ void store32(TrustedImm32 imm, BaseIndex address)
{
- m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
- m_assembler.dtr_u(false, src, ARMRegisters::S0, 0);
+ move(imm, ARMRegisters::S1);
+ m_assembler.baseIndexTransfer32(ARMAssembler::StoreUint32, ARMRegisters::S1, address.base, address.index, static_cast<int>(address.scale), address.offset);
}
- void store32(TrustedImm32 imm, void* address)
+ void store32(RegisterID src, const void* address)
{
- m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
- if (imm.m_isPointer)
- m_assembler.ldr_un_imm(ARMRegisters::S1, imm.m_value);
- else
- m_assembler.moveImm(imm.m_value, ARMRegisters::S1);
- m_assembler.dtr_u(false, ARMRegisters::S1, ARMRegisters::S0, 0);
+ m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
+ m_assembler.dtrUp(ARMAssembler::StoreUint32, src, ARMRegisters::S0, 0);
+ }
+
+ void store32(TrustedImm32 imm, const void* address)
+ {
+ m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
+ m_assembler.moveImm(imm.m_value, ARMRegisters::S1);
+ m_assembler.dtrUp(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0);
}
void pop(RegisterID dest)
{
- m_assembler.pop_r(dest);
+ m_assembler.pop(dest);
}
void push(RegisterID src)
{
- m_assembler.push_r(src);
+ m_assembler.push(src);
}
void push(Address address)
void move(TrustedImm32 imm, RegisterID dest)
{
- if (imm.m_isPointer)
- m_assembler.ldr_un_imm(dest, imm.m_value);
- else
- m_assembler.moveImm(imm.m_value, dest);
+ m_assembler.moveImm(imm.m_value, dest);
}
void move(RegisterID src, RegisterID dest)
{
- m_assembler.mov_r(dest, src);
+ if (src != dest)
+ m_assembler.mov(dest, src);
}
void move(TrustedImmPtr imm, RegisterID dest)
void swap(RegisterID reg1, RegisterID reg2)
{
- m_assembler.mov_r(ARMRegisters::S0, reg1);
- m_assembler.mov_r(reg1, reg2);
- m_assembler.mov_r(reg2, ARMRegisters::S0);
+ xor32(reg1, reg2);
+ xor32(reg2, reg1);
+ xor32(reg1, reg2);
}
void signExtend32ToPtr(RegisterID src, RegisterID dest)
Jump branch32(RelationalCondition cond, RegisterID left, RegisterID right, int useConstantPool = 0)
{
- m_assembler.cmp_r(left, right);
+ m_assembler.cmp(left, right);
return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool));
}
Jump branch32(RelationalCondition cond, RegisterID left, TrustedImm32 right, int useConstantPool = 0)
{
- if (right.m_isPointer) {
- m_assembler.ldr_un_imm(ARMRegisters::S0, right.m_value);
- m_assembler.cmp_r(left, ARMRegisters::S0);
- } else {
- ARMWord tmp = (right.m_value == 0x80000000) ? ARMAssembler::INVALID_IMM : m_assembler.getOp2(-right.m_value);
- if (tmp != ARMAssembler::INVALID_IMM)
- m_assembler.cmn_r(left, tmp);
- else
- m_assembler.cmp_r(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));
- }
+ internalCompare32(left, right);
return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool));
}
return branchTest32(cond, ARMRegisters::S1, mask);
}
+ Jump branchTest8(ResultCondition cond, AbsoluteAddress address, TrustedImm32 mask = TrustedImm32(-1))
+ {
+ move(TrustedImmPtr(address.m_ptr), ARMRegisters::S1);
+ load8(Address(ARMRegisters::S1), ARMRegisters::S1);
+ return branchTest32(cond, ARMRegisters::S1, mask);
+ }
+
Jump branchTest32(ResultCondition cond, RegisterID reg, RegisterID mask)
{
ASSERT((cond == Zero) || (cond == NonZero));
- m_assembler.tst_r(reg, mask);
+ m_assembler.tst(reg, mask);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
{
ASSERT((cond == Zero) || (cond == NonZero));
ARMWord w = m_assembler.getImm(mask.m_value, ARMRegisters::S0, true);
- if (w & ARMAssembler::OP2_INV_IMM)
- m_assembler.bics_r(ARMRegisters::S0, reg, w & ~ARMAssembler::OP2_INV_IMM);
+ if (w & ARMAssembler::Op2InvertedImmediate)
+ m_assembler.bics(ARMRegisters::S0, reg, w & ~ARMAssembler::Op2InvertedImmediate);
else
- m_assembler.tst_r(reg, w);
+ m_assembler.tst(reg, w);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
load32(address, ARMRegisters::pc);
}
+ void jump(AbsoluteAddress address)
+ {
+ move(TrustedImmPtr(address.m_ptr), ARMRegisters::S0);
+ load32(Address(ARMRegisters::S0, 0), ARMRegisters::pc);
+ }
+
+ void moveDoubleToInts(FPRegisterID src, RegisterID dest1, RegisterID dest2)
+ {
+ m_assembler.vmov(dest1, dest2, src);
+ }
+
+ void moveIntsToDouble(RegisterID src1, RegisterID src2, FPRegisterID dest, FPRegisterID)
+ {
+ m_assembler.vmov(dest, src1, src2);
+ }
+
Jump branchAdd32(ResultCondition cond, RegisterID src, RegisterID dest)
{
- ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
+ ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
+ || (cond == NonZero) || (cond == PositiveOrZero));
add32(src, dest);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
+ Jump branchAdd32(ResultCondition cond, RegisterID op1, RegisterID op2, RegisterID dest)
+ {
+ ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
+ || (cond == NonZero) || (cond == PositiveOrZero));
+ add32(op1, op2, dest);
+ return Jump(m_assembler.jmp(ARMCondition(cond)));
+ }
+
Jump branchAdd32(ResultCondition cond, TrustedImm32 imm, RegisterID dest)
{
- ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
+ ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
+ || (cond == NonZero) || (cond == PositiveOrZero));
add32(imm, dest);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
Jump branchAdd32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest)
{
- ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
+ ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
+ || (cond == NonZero) || (cond == PositiveOrZero));
add32(src, imm, dest);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
- void mull32(RegisterID src1, RegisterID src2, RegisterID dest)
+ Jump branchAdd32(ResultCondition cond, TrustedImm32 imm, AbsoluteAddress dest)
{
- if (src1 == dest) {
- move(src1, ARMRegisters::S0);
- src1 = ARMRegisters::S0;
+ ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
+ || (cond == NonZero) || (cond == PositiveOrZero));
+ add32(imm, dest);
+ return Jump(m_assembler.jmp(ARMCondition(cond)));
+ }
+
+ void mull32(RegisterID op1, RegisterID op2, RegisterID dest)
+ {
+ if (op2 == dest) {
+ if (op1 == dest) {
+ move(op2, ARMRegisters::S0);
+ op2 = ARMRegisters::S0;
+ } else {
+ // Swap the operands.
+ RegisterID tmp = op1;
+ op1 = op2;
+ op2 = tmp;
+ }
}
- m_assembler.mull_r(ARMRegisters::S1, dest, src2, src1);
- m_assembler.cmp_r(ARMRegisters::S1, m_assembler.asr(dest, 31));
+ m_assembler.mull(ARMRegisters::S1, dest, op1, op2);
+ m_assembler.cmp(ARMRegisters::S1, m_assembler.asr(dest, 31));
}
- Jump branchMul32(ResultCondition cond, RegisterID src, RegisterID dest)
+ Jump branchMul32(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest)
{
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
if (cond == Overflow) {
- mull32(src, dest, dest);
+ mull32(src1, src2, dest);
cond = NonZero;
}
else
- mul32(src, dest);
+ mul32(src1, src2, dest);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
+ Jump branchMul32(ResultCondition cond, RegisterID src, RegisterID dest)
+ {
+ return branchMul32(cond, src, dest, dest);
+ }
+
Jump branchMul32(ResultCondition cond, TrustedImm32 imm, RegisterID src, RegisterID dest)
{
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
Jump branchSub32(ResultCondition cond, RegisterID op1, RegisterID op2, RegisterID dest)
{
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
- m_assembler.subs_r(dest, op1, op2);
+ m_assembler.subs(dest, op1, op2);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
+ PatchableJump patchableBranch32(RelationalCondition cond, RegisterID reg, TrustedImm32 imm)
+ {
+ internalCompare32(reg, imm);
+ Jump jump(m_assembler.loadBranchTarget(ARMRegisters::S1, ARMCondition(cond), true));
+ m_assembler.bx(ARMRegisters::S1, ARMCondition(cond));
+ return PatchableJump(jump);
+ }
+
void breakpoint()
{
m_assembler.bkpt(0);
Call nearCall()
{
-#if WTF_ARM_ARCH_AT_LEAST(5)
- ensureSpace(2 * sizeof(ARMWord), sizeof(ARMWord));
m_assembler.loadBranchTarget(ARMRegisters::S1, ARMAssembler::AL, true);
return Call(m_assembler.blx(ARMRegisters::S1), Call::LinkableNear);
-#else
- prepareCall();
- return Call(m_assembler.jmp(ARMAssembler::AL, true), Call::LinkableNear);
-#endif
}
Call call(RegisterID target)
void compare32(RelationalCondition cond, RegisterID left, RegisterID right, RegisterID dest)
{
- m_assembler.cmp_r(left, right);
- m_assembler.mov_r(dest, ARMAssembler::getOp2(0));
- m_assembler.mov_r(dest, ARMAssembler::getOp2(1), ARMCondition(cond));
+ m_assembler.cmp(left, right);
+ m_assembler.mov(dest, ARMAssembler::getOp2Byte(0));
+ m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));
}
void compare32(RelationalCondition cond, RegisterID left, TrustedImm32 right, RegisterID dest)
{
- m_assembler.cmp_r(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));
- m_assembler.mov_r(dest, ARMAssembler::getOp2(0));
- m_assembler.mov_r(dest, ARMAssembler::getOp2(1), ARMCondition(cond));
+ m_assembler.cmp(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));
+ m_assembler.mov(dest, ARMAssembler::getOp2Byte(0));
+ m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));
}
void compare8(RelationalCondition cond, Address left, TrustedImm32 right, RegisterID dest)
void test32(ResultCondition cond, RegisterID reg, TrustedImm32 mask, RegisterID dest)
{
if (mask.m_value == -1)
- m_assembler.cmp_r(0, reg);
+ m_assembler.cmp(0, reg);
else
- m_assembler.tst_r(reg, m_assembler.getImm(mask.m_value, ARMRegisters::S0));
- m_assembler.mov_r(dest, ARMAssembler::getOp2(0));
- m_assembler.mov_r(dest, ARMAssembler::getOp2(1), ARMCondition(cond));
+ m_assembler.tst(reg, m_assembler.getImm(mask.m_value, ARMRegisters::S0));
+ m_assembler.mov(dest, ARMAssembler::getOp2Byte(0));
+ m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));
}
void test32(ResultCondition cond, Address address, TrustedImm32 mask, RegisterID dest)
void add32(TrustedImm32 imm, RegisterID src, RegisterID dest)
{
- m_assembler.add_r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
+ m_assembler.add(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
}
void add32(TrustedImm32 imm, AbsoluteAddress address)
{
- m_assembler.ldr_un_imm(ARMRegisters::S1, reinterpret_cast<ARMWord>(address.m_ptr));
- m_assembler.dtr_u(true, ARMRegisters::S1, ARMRegisters::S1, 0);
+ load32(address.m_ptr, ARMRegisters::S1);
add32(imm, ARMRegisters::S1);
- m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address.m_ptr));
- m_assembler.dtr_u(false, ARMRegisters::S1, ARMRegisters::S0, 0);
+ store32(ARMRegisters::S1, address.m_ptr);
+ }
+
+ void add64(TrustedImm32 imm, AbsoluteAddress address)
+ {
+ ARMWord tmp;
+
+ move(TrustedImmPtr(address.m_ptr), ARMRegisters::S1);
+ m_assembler.dtrUp(ARMAssembler::LoadUint32, ARMRegisters::S0, ARMRegisters::S1, 0);
+
+ if ((tmp = ARMAssembler::getOp2(imm.m_value)) != ARMAssembler::InvalidImmediate)
+ m_assembler.adds(ARMRegisters::S0, ARMRegisters::S0, tmp);
+ else if ((tmp = ARMAssembler::getOp2(-imm.m_value)) != ARMAssembler::InvalidImmediate)
+ m_assembler.subs(ARMRegisters::S0, ARMRegisters::S0, tmp);
+ else {
+ m_assembler.adds(ARMRegisters::S0, ARMRegisters::S0, m_assembler.getImm(imm.m_value, ARMRegisters::S1));
+ move(TrustedImmPtr(address.m_ptr), ARMRegisters::S1);
+ }
+ m_assembler.dtrUp(ARMAssembler::StoreUint32, ARMRegisters::S0, ARMRegisters::S1, 0);
+
+ m_assembler.dtrUp(ARMAssembler::LoadUint32, ARMRegisters::S0, ARMRegisters::S1, sizeof(ARMWord));
+ if (imm.m_value >= 0)
+ m_assembler.adc(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
+ else
+ m_assembler.sbc(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
+ m_assembler.dtrUp(ARMAssembler::StoreUint32, ARMRegisters::S0, ARMRegisters::S1, sizeof(ARMWord));
}
void sub32(TrustedImm32 imm, AbsoluteAddress address)
{
- m_assembler.ldr_un_imm(ARMRegisters::S1, reinterpret_cast<ARMWord>(address.m_ptr));
- m_assembler.dtr_u(true, ARMRegisters::S1, ARMRegisters::S1, 0);
+ load32(address.m_ptr, ARMRegisters::S1);
sub32(imm, ARMRegisters::S1);
- m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address.m_ptr));
- m_assembler.dtr_u(false, ARMRegisters::S1, ARMRegisters::S0, 0);
+ store32(ARMRegisters::S1, address.m_ptr);
}
void load32(const void* address, RegisterID dest)
{
- m_assembler.ldr
_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
- m_assembler.dtr_u(true, dest, ARMRegisters::S0, 0);
+ m_assembler.ldr
UniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
+ m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, ARMRegisters::S0, 0);
}
Jump branch32(RelationalCondition cond, AbsoluteAddress left, RegisterID right)
void relativeTableJump(RegisterID index, int scale)
{
ASSERT(scale >= 0 && scale <= 31);
- m_assembler.add_r(ARMRegisters::pc, ARMRegisters::pc, m_assembler.lsl(index, scale));
+ m_assembler.add(ARMRegisters::pc, ARMRegisters::pc, m_assembler.lsl(index, scale));
// NOP the default prefetching
- m_assembler.mov_r(ARMRegisters::r0, ARMRegisters::r0);
+ m_assembler.mov(ARMRegisters::r0, ARMRegisters::r0);
}
Call call()
{
-#if WTF_ARM_ARCH_AT_LEAST(5)
ensureSpace(2 * sizeof(ARMWord), sizeof(ARMWord));
m_assembler.loadBranchTarget(ARMRegisters::S1, ARMAssembler::AL, true);
return Call(m_assembler.blx(ARMRegisters::S1), Call::Linkable);
-#else
- prepareCall();
- return Call(m_assembler.jmp(ARMAssembler::AL, true), Call::Linkable);
-#endif
}
Call tailRecursiveCall()
DataLabelPtr moveWithPatch(TrustedImmPtr initialValue, RegisterID dest)
{
DataLabelPtr dataLabel(this);
- m_assembler.ldr
_un_imm(dest, reinterpret_cast<ARMWord>(initialValue.m_value));
+ m_assembler.ldr
UniqueImmediate(dest, reinterpret_cast<ARMWord>(initialValue.m_value));
return dataLabel;
}
Jump branchPtrWithPatch(RelationalCondition cond, RegisterID left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(0))
{
+ ensureSpace(3 * sizeof(ARMWord), 2 * sizeof(ARMWord));
dataLabel = moveWithPatch(initialRightValue, ARMRegisters::S1);
Jump jump = branch32(cond, left, ARMRegisters::S1, true);
return jump;
Jump branchPtrWithPatch(RelationalCondition cond, Address left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(0))
{
load32(left, ARMRegisters::S1);
+ ensureSpace(3 * sizeof(ARMWord), 2 * sizeof(ARMWord));
dataLabel = moveWithPatch(initialRightValue, ARMRegisters::S0);
Jump jump = branch32(cond, ARMRegisters::S0, ARMRegisters::S1, true);
return jump;
}
static bool supportsFloatingPointAbs() { return false; }
+ void loadFloat(BaseIndex address, FPRegisterID dest)
+ {
+ m_assembler.baseIndexTransferFloat(ARMAssembler::LoadFloat, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
+ }
+
void loadDouble(ImplicitAddress address, FPRegisterID dest)
{
- m_assembler.doubleTransfer(true, dest, address.base, address.offset);
+ m_assembler.dataTransferFloat(ARMAssembler::LoadDouble, dest, address.base, address.offset);
+ }
+
+ void loadDouble(BaseIndex address, FPRegisterID dest)
+ {
+ m_assembler.baseIndexTransferFloat(ARMAssembler::LoadDouble, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
}
void loadDouble(const void* address, FPRegisterID dest)
{
- m_assembler.ldr_un_imm(ARMRegisters::S0, (ARMWord)address);
- m_assembler.fdtr_u(true, dest, ARMRegisters::S0, 0);
+ move(TrustedImm32(reinterpret_cast<ARMWord>(address)), ARMRegisters::S0);
+ m_assembler.doubleDtrUp(ARMAssembler::LoadDouble, dest, ARMRegisters::S0, 0);
+ }
+
+ void storeFloat(FPRegisterID src, BaseIndex address)
+ {
+ m_assembler.baseIndexTransferFloat(ARMAssembler::StoreFloat, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
}
void storeDouble(FPRegisterID src, ImplicitAddress address)
{
- m_assembler.doubleTransfer(false, src, address.base, address.offset);
+ m_assembler.dataTransferFloat(ARMAssembler::StoreDouble, src, address.base, address.offset);
+ }
+
+ void storeDouble(FPRegisterID src, BaseIndex address)
+ {
+ m_assembler.baseIndexTransferFloat(ARMAssembler::StoreDouble, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
+ }
+
+ void storeDouble(FPRegisterID src, const void* address)
+ {
+ move(TrustedImm32(reinterpret_cast<ARMWord>(address)), ARMRegisters::S0);
+ m_assembler.dataTransferFloat(ARMAssembler::StoreDouble, src, ARMRegisters::S0, 0);
+ }
+
+ void moveDouble(FPRegisterID src, FPRegisterID dest)
+ {
+ if (src != dest)
+ m_assembler.vmov_f64(dest, src);
}
void addDouble(FPRegisterID src, FPRegisterID dest)
{
- m_assembler.vadd_f64_r(dest, dest, src);
+ m_assembler.vadd_f64(dest, dest, src);
+ }
+
+ void addDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+ {
+ m_assembler.vadd_f64(dest, op1, op2);
}
void addDouble(Address src, FPRegisterID dest)
addDouble(ARMRegisters::SD0, dest);
}
+ void addDouble(AbsoluteAddress address, FPRegisterID dest)
+ {
+ loadDouble(address.m_ptr, ARMRegisters::SD0);
+ addDouble(ARMRegisters::SD0, dest);
+ }
+
void divDouble(FPRegisterID src, FPRegisterID dest)
{
- m_assembler.vdiv_f64_r(dest, dest, src);
+ m_assembler.vdiv_f64(dest, dest, src);
+ }
+
+ void divDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+ {
+ m_assembler.vdiv_f64(dest, op1, op2);
}
void divDouble(Address src, FPRegisterID dest)
{
- ASSERT_NOT_REACHED(); // Untested
+ RELEASE_ASSERT_NOT_REACHED(); // Untested
loadDouble(src, ARMRegisters::SD0);
divDouble(ARMRegisters::SD0, dest);
}
void subDouble(FPRegisterID src, FPRegisterID dest)
{
- m_assembler.vsub_f64_r(dest, dest, src);
+ m_assembler.vsub_f64(dest, dest, src);
+ }
+
+ void subDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+ {
+ m_assembler.vsub_f64(dest, op1, op2);
}
void subDouble(Address src, FPRegisterID dest)
void mulDouble(FPRegisterID src, FPRegisterID dest)
{
- m_assembler.vmul_f64_r(dest, dest, src);
+ m_assembler.vmul_f64(dest, dest, src);
}
void mulDouble(Address src, FPRegisterID dest)
mulDouble(ARMRegisters::SD0, dest);
}
+ void mulDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+ {
+ m_assembler.vmul_f64(dest, op1, op2);
+ }
+
void sqrtDouble(FPRegisterID src, FPRegisterID dest)
{
- m_assembler.vsqrt_f64_r(dest, src);
+ m_assembler.vsqrt_f64(dest, src);
}
- void absDouble(FPRegisterID, FPRegisterID)
+ void absDouble(FPRegisterID src, FPRegisterID dest)
+ {
+ m_assembler.vabs_f64(dest, src);
+ }
+
+ void negateDouble(FPRegisterID src, FPRegisterID dest)
{
- ASSERT_NOT_REACHED();
+ m_assembler.vneg_f64(dest, src);
}
void convertInt32ToDouble(RegisterID src, FPRegisterID dest)
{
- m_assembler.vmov_vfp_r(dest << 1, src);
- m_assembler.vcvt_f64_s32_r(dest, dest << 1);
+ m_assembler.vmov_vfp32(dest << 1, src);
+ m_assembler.vcvt_f64_s32(dest, dest << 1);
}
void convertInt32ToDouble(Address src, FPRegisterID dest)
{
- ASSERT_NOT_REACHED(); // Untested
- // flds does not worth the effort here
load32(src, ARMRegisters::S1);
convertInt32ToDouble(ARMRegisters::S1, dest);
}
void convertInt32ToDouble(AbsoluteAddress src, FPRegisterID dest)
{
- ASSERT_NOT_REACHED(); // Untested
- // flds does not worth the effort here
- m_assembler.ldr_un_imm(ARMRegisters::S1, (ARMWord)src.m_ptr);
- m_assembler.dtr_u(true, ARMRegisters::S1, ARMRegisters::S1, 0);
+ move(TrustedImmPtr(src.m_ptr), ARMRegisters::S1);
+ load32(Address(ARMRegisters::S1), ARMRegisters::S1);
convertInt32ToDouble(ARMRegisters::S1, dest);
}
+ void convertFloatToDouble(FPRegisterID src, FPRegisterID dst)
+ {
+ m_assembler.vcvt_f64_f32(dst, src);
+ }
+
+ void convertDoubleToFloat(FPRegisterID src, FPRegisterID dst)
+ {
+ m_assembler.vcvt_f32_f64(dst, src);
+ }
+
Jump branchDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right)
{
- m_assembler.vcmp_f64_r(left, right);
+ m_assembler.vcmp_f64(left, right);
m_assembler.vmrs_apsr();
if (cond & DoubleConditionBitSpecial)
- m_assembler.cmp_r(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::VS);
+ m_assembler.cmp(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::VS);
return Jump(m_assembler.jmp(static_cast<ARMAssembler::Condition>(cond & ~DoubleConditionMask)));
}
// If the result is not representable as a 32 bit value, branch.
// May also branch for some values that are representable in 32 bits
// (specifically, in this case, INT_MIN).
- Jump branchTruncateDoubleToInt32(FPRegisterID src, RegisterID dest)
+ enum BranchTruncateType { BranchIfTruncateFailed, BranchIfTruncateSuccessful };
+ Jump branchTruncateDoubleToInt32(FPRegisterID src, RegisterID dest, BranchTruncateType branchType = BranchIfTruncateFailed)
{
- UNUSED_PARAM(src);
- UNUSED_PARAM(dest);
- ASSERT_NOT_REACHED();
- return jump();
+ truncateDoubleToInt32(src, dest);
+
+ m_assembler.add(ARMRegisters::S0, dest, ARMAssembler::getOp2Byte(1));
+ m_assembler.bic(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(1));
+
+ ARMWord w = ARMAssembler::getOp2(0x80000000);
+ ASSERT(w != ARMAssembler::InvalidImmediate);
+ m_assembler.cmp(ARMRegisters::S0, w);
+ return Jump(m_assembler.jmp(branchType == BranchIfTruncateFailed ? ARMAssembler::EQ : ARMAssembler::NE));
+ }
+
+ Jump branchTruncateDoubleToUint32(FPRegisterID src, RegisterID dest, BranchTruncateType branchType = BranchIfTruncateFailed)
+ {
+ truncateDoubleToUint32(src, dest);
+
+ m_assembler.add(ARMRegisters::S0, dest, ARMAssembler::getOp2Byte(1));
+ m_assembler.bic(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(1));
+
+ m_assembler.cmp(ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
+ return Jump(m_assembler.jmp(branchType == BranchIfTruncateFailed ? ARMAssembler::EQ : ARMAssembler::NE));
+ }
+
+ // Result is undefined if the value is outside of the integer range.
+ void truncateDoubleToInt32(FPRegisterID src, RegisterID dest)
+ {
+ m_assembler.vcvt_s32_f64(ARMRegisters::SD0 << 1, src);
+ m_assembler.vmov_arm32(dest, ARMRegisters::SD0 << 1);
+ }
+
+ void truncateDoubleToUint32(FPRegisterID src, RegisterID dest)
+ {
+ m_assembler.vcvt_u32_f64(ARMRegisters::SD0 << 1, src);
+ m_assembler.vmov_arm32(dest, ARMRegisters::SD0 << 1);
}
// Convert 'src' to an integer, and places the resulting 'dest'.
// If the result is not representable as a 32 bit value, branch.
// May also branch for some values that are representable in 32 bits
// (specifically, in this case, 0).
- void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID fpTemp)
+ void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID, bool negZeroCheck = true)
{
- m_assembler.vcvt_s32_f64_r(ARMRegisters::SD0 << 1, src);
- m_assembler.vmov_arm_r(dest, ARMRegisters::SD0 << 1);
+ m_assembler.vcvt_s32_f64(ARMRegisters::SD0 << 1, src);
+ m_assembler.vmov_arm32(dest, ARMRegisters::SD0 << 1);
// Convert the integer result back to float & compare to the original value - if not equal or unordered (NaN) then jump.
- m_assembler.vcvt_f64_s32_r(ARMRegisters::SD0, ARMRegisters::SD0 << 1);
+ m_assembler.vcvt_f64_s32(ARMRegisters::SD0, ARMRegisters::SD0 << 1);
failureCases.append(branchDouble(DoubleNotEqualOrUnordered, src, ARMRegisters::SD0));
// If the result is zero, it might have been -0.0, and 0.0 equals to -0.0
- failureCases.append(branchTest32(Zero, dest));
+ if (negZeroCheck)
+ failureCases.append(branchTest32(Zero, dest));
}
Jump branchDoubleNonZero(FPRegisterID reg, FPRegisterID scratch)
{
- m_assembler.mov_r(ARMRegisters::S0, ARMAssembler::getOp2(0));
+ m_assembler.mov(ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
convertInt32ToDouble(ARMRegisters::S0, scratch);
return branchDouble(DoubleNotEqual, reg, scratch);
}
Jump branchDoubleZeroOrNaN(FPRegisterID reg, FPRegisterID scratch)
{
- m_assembler.mov_r(ARMRegisters::S0, ARMAssembler::getOp2(0));
+ m_assembler.mov(ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
convertInt32ToDouble(ARMRegisters::S0, scratch);
return branchDouble(DoubleEqualOrUnordered, reg, scratch);
}
+ // Invert a relational condition, e.g. == becomes !=, < becomes >=, etc.
+ static RelationalCondition invert(RelationalCondition cond)
+ {
+ ASSERT((static_cast<uint32_t>(cond & 0x0fffffff)) == 0 && static_cast<uint32_t>(cond) < static_cast<uint32_t>(ARMAssembler::AL));
+ return static_cast<RelationalCondition>(cond ^ 0x10000000);
+ }
+
void nop()
{
m_assembler.nop();
return FunctionPtr(reinterpret_cast<void(*)()>(ARMAssembler::readCallTarget(call.dataLocation())));
}
+ static void replaceWithJump(CodeLocationLabel instructionStart, CodeLocationLabel destination)
+ {
+ ARMAssembler::replaceWithJump(instructionStart.dataLocation(), destination.dataLocation());
+ }
+
+ static ptrdiff_t maxJumpReplacementSize()
+ {
+ ARMAssembler::maxJumpReplacementSize();
+ return 0;
+ }
+
+ static bool canJumpReplacePatchableBranchPtrWithPatch() { return false; }
+
+ static CodeLocationLabel startOfPatchableBranchPtrWithPatchOnAddress(CodeLocationDataLabelPtr)
+ {
+ UNREACHABLE_FOR_PLATFORM();
+ return CodeLocationLabel();
+ }
+
+ static CodeLocationLabel startOfBranchPtrWithPatchOnRegister(CodeLocationDataLabelPtr label)
+ {
+ return label.labelAtOffset(0);
+ }
+
+ static void revertJumpReplacementToBranchPtrWithPatch(CodeLocationLabel instructionStart, RegisterID reg, void* initialValue)
+ {
+ ARMAssembler::revertBranchPtrWithPatch(instructionStart.dataLocation(), reg, reinterpret_cast<uintptr_t>(initialValue) & 0xffff);
+ }
+
+ static void revertJumpReplacementToPatchableBranchPtrWithPatch(CodeLocationLabel, Address, void*)
+ {
+ UNREACHABLE_FOR_PLATFORM();
+ }
+
protected:
ARMAssembler::Condition ARMCondition(RelationalCondition cond)
{
return m_assembler.sizeOfConstantPool();
}
- void prepareCall()
- {
-#if WTF_ARM_ARCH_VERSION < 5
- ensureSpace(2 * sizeof(ARMWord), sizeof(ARMWord));
-
- m_assembler.mov_r(linkRegister, ARMRegisters::pc);
-#endif
- }
-
void call32(RegisterID base, int32_t offset)
{
-#if WTF_ARM_ARCH_AT_LEAST(5)
- int targetReg = ARMRegisters::S1;
-#else
- int targetReg = ARMRegisters::pc;
-#endif
- int tmpReg = ARMRegisters::S1;
-
- if (base == ARMRegisters::sp)
- offset += 4;
-
- if (offset >= 0) {
- if (offset <= 0xfff) {
- prepareCall();
- m_assembler.dtr_u(true, targetReg, base, offset);
- } else if (offset <= 0xfffff) {
- m_assembler.add_r(tmpReg, base, ARMAssembler::OP2_IMM | (offset >> 12) | (10 << 8));
- prepareCall();
- m_assembler.dtr_u(true, targetReg, tmpReg, offset & 0xfff);
- } else {
- m_assembler.moveImm(offset, tmpReg);
- prepareCall();
- m_assembler.dtr_ur(true, targetReg, base, tmpReg);
- }
- } else {
- offset = -offset;
- if (offset <= 0xfff) {
- prepareCall();
- m_assembler.dtr_d(true, targetReg, base, offset);
- } else if (offset <= 0xfffff) {
- m_assembler.sub_r(tmpReg, base, ARMAssembler::OP2_IMM | (offset >> 12) | (10 << 8));
- prepareCall();
- m_assembler.dtr_d(true, targetReg, tmpReg, offset & 0xfff);
- } else {
- m_assembler.moveImm(offset, tmpReg);
- prepareCall();
- m_assembler.dtr_dr(true, targetReg, base, tmpReg);
- }
- }
-#if WTF_ARM_ARCH_AT_LEAST(5)
- m_assembler.blx(targetReg);
-#endif
+ load32(Address(base, offset), ARMRegisters::S1);
+ m_assembler.blx(ARMRegisters::S1);
}
private:
friend class LinkBuffer;
friend class RepatchBuffer;
+ void internalCompare32(RegisterID left, TrustedImm32 right)
+ {
+ ARMWord tmp = (static_cast<unsigned>(right.m_value) == 0x80000000) ? ARMAssembler::InvalidImmediate : m_assembler.getOp2(-right.m_value);
+ if (tmp != ARMAssembler::InvalidImmediate)
+ m_assembler.cmn(left, tmp);
+ else
+ m_assembler.cmp(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));
+ }
+
static void linkCall(void* code, Call call, FunctionPtr function)
{
ARMAssembler::linkCall(code, call.m_label, function.value());
projects / apple / javascriptcore.git / blobdiff