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[apple/javascriptcore.git] / assembler / ARMAssembler.h
diff --git a/assembler/ARMAssembler.h b/assembler/ARMAssembler.h
index 2ca0949803079ba7bb4864bab1d29c6aa4722ad5..087d31c14ab91ba25c089ec9fd40de7ce084bd3f 100644 (file)
--- a/assembler/ARMAssembler.h
+++ b/assembler/ARMAssembler.h
@@ -30,6 +30,7 @@
 #if ENABLE(ASSEMBLER) && CPU(ARM_TRADITIONAL)
 
 #include "AssemblerBufferWithConstantPool.h"
 #if ENABLE(ASSEMBLER) && CPU(ARM_TRADITIONAL)
 
 #include "AssemblerBufferWithConstantPool.h"
+#include "JITCompilationEffort.h"
 #include <wtf/Assertions.h>
 namespace JSC {
 
 #include <wtf/Assertions.h>
 namespace JSC {
 
@@ -41,23 +42,18 @@ namespace JSC {
             r1,
             r2,
             r3,
             r1,
             r2,
             r3,
-            S0 = r3,
             r4,
             r5,
             r4,
             r5,
-            r6,
+            r6, S0 = r6,
             r7,
             r8,
             r7,
             r8,
-            S1 = r8,
             r9,
             r10,
             r9,
             r10,
-            r11,
-            r12,
-            r13,
-            sp = r13,
-            r14,
-            lr = r14,
-            r15,
-            pc = r15
+            r11, fp = r11, // frame pointer
+            r12, ip = r12, S1 = r12,
+            r13, sp = r13,
+            r14, lr = r14,
+            r15, pc = r15
         } RegisterID;
 
         typedef enum {
         } RegisterID;
 
         typedef enum {
@@ -65,9 +61,82 @@ namespace JSC {
             d1,
             d2,
             d3,
             d1,
             d2,
             d3,
-            SD0 = d3
+            d4,
+            d5,
+            d6,
+            d7, SD0 = d7, /* Same as thumb assembler. */
+            d8,
+            d9,
+            d10,
+            d11,
+            d12,
+            d13,
+            d14,
+            d15,
+            d16,
+            d17,
+            d18,
+            d19,
+            d20,
+            d21,
+            d22,
+            d23,
+            d24,
+            d25,
+            d26,
+            d27,
+            d28,
+            d29,
+            d30,
+            d31
         } FPRegisterID;
 
         } FPRegisterID;
 
+#if USE(MASM_PROBE)
+    #define FOR_EACH_CPU_REGISTER(V) \
+        FOR_EACH_CPU_GPREGISTER(V) \
+        FOR_EACH_CPU_SPECIAL_REGISTER(V) \
+        FOR_EACH_CPU_FPREGISTER(V)
+
+    #define FOR_EACH_CPU_GPREGISTER(V) \
+        V(void*, r0) \
+        V(void*, r1) \
+        V(void*, r2) \
+        V(void*, r3) \
+        V(void*, r4) \
+        V(void*, r5) \
+        V(void*, r6) \
+        V(void*, r7) \
+        V(void*, r8) \
+        V(void*, r9) \
+        V(void*, r10) \
+        V(void*, r11) \
+        V(void*, ip) \
+        V(void*, sp) \
+        V(void*, lr) \
+        V(void*, pc)
+
+    #define FOR_EACH_CPU_SPECIAL_REGISTER(V) \
+        V(void*, apsr) \
+        V(void*, fpscr) \
+
+    #define FOR_EACH_CPU_FPREGISTER(V) \
+        V(double, d0) \
+        V(double, d1) \
+        V(double, d2) \
+        V(double, d3) \
+        V(double, d4) \
+        V(double, d5) \
+        V(double, d6) \
+        V(double, d7) \
+        V(double, d8) \
+        V(double, d9) \
+        V(double, d10) \
+        V(double, d11) \
+        V(double, d12) \
+        V(double, d13) \
+        V(double, d14) \
+        V(double, d15)
+#endif // USE(MASM_PROBE)
     } // namespace ARMRegisters
 
     class ARMAssembler {
     } // namespace ARMRegisters
 
     class ARMAssembler {
@@ -75,27 +144,38 @@ namespace JSC {
         typedef ARMRegisters::RegisterID RegisterID;
         typedef ARMRegisters::FPRegisterID FPRegisterID;
         typedef AssemblerBufferWithConstantPool<2048, 4, 4, ARMAssembler> ARMBuffer;
         typedef ARMRegisters::RegisterID RegisterID;
         typedef ARMRegisters::FPRegisterID FPRegisterID;
         typedef AssemblerBufferWithConstantPool<2048, 4, 4, ARMAssembler> ARMBuffer;
-        typedef SegmentedVector<int, 64> Jumps;
+        typedef SegmentedVector<AssemblerLabel, 64> Jumps;
 
 
-        ARMAssembler() { }
+        ARMAssembler()
+            : m_indexOfTailOfLastWatchpoint(1)
+        {
+        }
+
+        ARMBuffer& buffer() { return m_buffer; }
+
+        static RegisterID firstRegister() { return ARMRegisters::r0; }
+        static RegisterID lastRegister() { return ARMRegisters::r15; }
+
+        static FPRegisterID firstFPRegister() { return ARMRegisters::d0; }
+        static FPRegisterID lastFPRegister() { return ARMRegisters::d31; }
 
         // ARM conditional constants
         typedef enum {
 
         // ARM conditional constants
         typedef enum {
-            EQ = 0x00000000, // Zero
-            NE = 0x10000000, // Non-zero
-            CS = 0x20000000,
-            CC = 0x30000000,
-            MI = 0x40000000,
-            PL = 0x50000000,
-            VS = 0x60000000,
-            VC = 0x70000000,
-            HI = 0x80000000,
-            LS = 0x90000000,
-            GE = 0xa0000000,
-            LT = 0xb0000000,
-            GT = 0xc0000000,
-            LE = 0xd0000000,
-            AL = 0xe0000000
+            EQ = 0x00000000, // Zero / Equal.
+            NE = 0x10000000, // Non-zero / Not equal.
+            CS = 0x20000000, // Unsigned higher or same.
+            CC = 0x30000000, // Unsigned lower.
+            MI = 0x40000000, // Negative.
+            PL = 0x50000000, // Positive or zero.
+            VS = 0x60000000, // Overflowed.
+            VC = 0x70000000, // Not overflowed.
+            HI = 0x80000000, // Unsigned higher.
+            LS = 0x90000000, // Unsigned lower or same.
+            GE = 0xa0000000, // Signed greater than or equal.
+            LT = 0xb0000000, // Signed less than.
+            GT = 0xc0000000, // Signed greater than.
+            LE = 0xd0000000, // Signed less than or equal.
+            AL = 0xe0000000  // Unconditional / Always execute.
         } Condition;
 
         // ARM instruction constants
         } Condition;
 
         // ARM instruction constants
@@ -118,468 +198,519 @@ namespace JSC {
             MVN = (0xf << 21),
             MUL = 0x00000090,
             MULL = 0x00c00090,
             MVN = (0xf << 21),
             MUL = 0x00000090,
             MULL = 0x00c00090,
-            FADDD = 0x0e300b00,
-            FDIVD = 0x0e800b00,
-            FSUBD = 0x0e300b40,
-            FMULD = 0x0e200b00,
-            FCMPD = 0x0eb40b40,
-            FSQRTD = 0x0eb10bc0,
-            DTR = 0x05000000,
-            LDRH = 0x00100090,
-            STRH = 0x00000090,
+            VMOV_F64 = 0x0eb00b40,
+            VADD_F64 = 0x0e300b00,
+            VDIV_F64 = 0x0e800b00,
+            VSUB_F64 = 0x0e300b40,
+            VMUL_F64 = 0x0e200b00,
+            VCMP_F64 = 0x0eb40b40,
+            VSQRT_F64 = 0x0eb10bc0,
+            VABS_F64 = 0x0eb00bc0,
+            VNEG_F64 = 0x0eb10b40,
             STMDB = 0x09200000,
             LDMIA = 0x08b00000,
             STMDB = 0x09200000,
             LDMIA = 0x08b00000,
-            FDTR = 0x0d000b00,
             B = 0x0a000000,
             BL = 0x0b000000,
             B = 0x0a000000,
             BL = 0x0b000000,
-#if WTF_ARM_ARCH_AT_LEAST(5) || defined(__ARM_ARCH_4T__)
             BX = 0x012fff10,
             BX = 0x012fff10,
-#endif
-            FMSR = 0x0e000a10,
-            FMRS = 0x0e100a10,
-            FSITOD = 0x0eb80bc0,
-            FTOSID = 0x0ebd0b40,
-            FMSTAT = 0x0ef1fa10,
-#if WTF_ARM_ARCH_AT_LEAST(5)
+            VMOV_VFP64 = 0x0c400a10,
+            VMOV_ARM64 = 0x0c500a10,
+            VMOV_VFP32 = 0x0e000a10,
+            VMOV_ARM32 = 0x0e100a10,
+            VCVT_F64_S32 = 0x0eb80bc0,
+            VCVT_S32_F64 = 0x0ebd0bc0,
+            VCVT_U32_F64 = 0x0ebc0bc0,
+            VCVT_F32_F64 = 0x0eb70bc0,
+            VCVT_F64_F32 = 0x0eb70ac0,
+            VMRS_APSR = 0x0ef1fa10,
             CLZ = 0x016f0f10,
             CLZ = 0x016f0f10,
-            BKPT = 0xe120070,
+            BKPT = 0xe1200070,
             BLX = 0x012fff30,
             BLX = 0x012fff30,
-#endif
 #if WTF_ARM_ARCH_AT_LEAST(7)
             MOVW = 0x03000000,
             MOVT = 0x03400000,
 #endif
 #if WTF_ARM_ARCH_AT_LEAST(7)
             MOVW = 0x03000000,
             MOVT = 0x03400000,
 #endif
+            NOP = 0xe1a00000,
+            DMB_SY = 0xf57ff05f,
         };
 
         enum {
         };
 
         enum {
-            OP2_IMM = (1 << 25),
-            OP2_IMMh = (1 << 22),
-            OP2_INV_IMM = (1 << 26),
-            SET_CC = (1 << 20),
-            OP2_OFSREG = (1 << 25),
-            DT_UP = (1 << 23),
-            DT_BYTE = (1 << 22),
-            DT_WB = (1 << 21),
-            // This flag is inlcuded in LDR and STR
-            DT_PRE = (1 << 24),
-            HDT_UH = (1 << 5),
-            DT_LOAD = (1 << 20),
+            Op2Immediate = (1 << 25),
+            ImmediateForHalfWordTransfer = (1 << 22),
+            Op2InvertedImmediate = (1 << 26),
+            SetConditionalCodes = (1 << 20),
+            Op2IsRegisterArgument = (1 << 25),
+            // Data transfer flags.
+            DataTransferUp = (1 << 23),
+            DataTransferWriteBack = (1 << 21),
+            DataTransferPostUpdate = (1 << 24),
+            DataTransferLoad = (1 << 20),
+            ByteDataTransfer = (1 << 22),
+        };
+
+        enum DataTransferTypeA {
+            LoadUint32 = 0x05000000 | DataTransferLoad,
+            LoadUint8 = 0x05400000 | DataTransferLoad,
+            StoreUint32 = 0x05000000,
+            StoreUint8 = 0x05400000,
+        };
+
+        enum DataTransferTypeB {
+            LoadUint16 = 0x010000b0 | DataTransferLoad,
+            LoadInt16 = 0x010000f0 | DataTransferLoad,
+            LoadInt8 = 0x010000d0 | DataTransferLoad,
+            StoreUint16 = 0x010000b0,
+        };
+
+        enum DataTransferTypeFloat {
+            LoadFloat = 0x0d000a00 | DataTransferLoad,
+            LoadDouble = 0x0d000b00 | DataTransferLoad,
+            StoreFloat = 0x0d000a00,
+            StoreDouble = 0x0d000b00,
         };
 
         // Masks of ARM instructions
         enum {
         };
 
         // Masks of ARM instructions
         enum {
-            BRANCH_MASK = 0x00ffffff,
-            NONARM = 0xf0000000,
-            SDT_MASK = 0x0c000000,
-            SDT_OFFSET_MASK = 0xfff,
+            BranchOffsetMask = 0x00ffffff,
+            ConditionalFieldMask = 0xf0000000,
+            DataTransferOffsetMask = 0xfff,
         };
 
         enum {
         };
 
         enum {
-            BOFFSET_MIN = -0x00800000,
-            BOFFSET_MAX = 0x007fffff,
-            SDT = 0x04000000,
+            MinimumBranchOffsetDistance = -0x00800000,
+            MaximumBranchOffsetDistance = 0x007fffff,
         };
 
         enum {
             padForAlign8  = 0x00,
             padForAlign16 = 0x0000,
         };
 
         enum {
             padForAlign8  = 0x00,
             padForAlign16 = 0x0000,
-            padForAlign32 = 0xee120070,
+            padForAlign32 = 0xe12fff7f // 'bkpt 0xffff' instruction.
         };
 
         };
 
-        static const ARMWord INVALID_IMM = 0xf0000000;
+        static const ARMWord InvalidImmediate = 0xf0000000;
         static const ARMWord InvalidBranchTarget = 0xffffffff;
         static const ARMWord InvalidBranchTarget = 0xffffffff;
-        static const int DefaultPrefetching = 2;
-
-        class JmpSrc {
-            friend class ARMAssembler;
-        public:
-            JmpSrc()
-                : m_offset(-1)
-            {
-            }
+        static const int DefaultPrefetchOffset = 2;
 
 
-        private:
-            JmpSrc(int offset)
-                : m_offset(offset)
-            {
-            }
+        static const ARMWord BlxInstructionMask = 0x012fff30;
+        static const ARMWord LdrOrAddInstructionMask = 0x0ff00000;
+        static const ARMWord LdrPcImmediateInstructionMask = 0x0f7f0000;
 
 
-            int m_offset;
-        };
+        static const ARMWord AddImmediateInstruction = 0x02800000;
+        static const ARMWord BlxInstruction = 0x012fff30;
+        static const ARMWord LdrImmediateInstruction = 0x05900000;
+        static const ARMWord LdrPcImmediateInstruction = 0x051f0000;
 
 
-        class JmpDst {
-            friend class ARMAssembler;
-        public:
-            JmpDst()
-                : m_offset(-1)
-                , m_used(false)
-            {
-            }
+        // Instruction formating
 
 
-            bool isUsed() const { return m_used; }
-            void used() { m_used = true; }
-        private:
-            JmpDst(int offset)
-                : m_offset(offset)
-                , m_used(false)
-            {
-                ASSERT(m_offset == offset);
-            }
+        void emitInstruction(ARMWord op, int rd, int rn, ARMWord op2)
+        {
+            ASSERT(((op2 & ~Op2Immediate) <= 0xfff) || (((op2 & ~ImmediateForHalfWordTransfer) <= 0xfff)));
+            m_buffer.putInt(op | RN(rn) | RD(rd) | op2);
+        }
 
 
-            int m_offset : 31;
-            int m_used : 1;
-        };
+        void emitDoublePrecisionInstruction(ARMWord op, int dd, int dn, int dm)
+        {
+            ASSERT((dd >= 0 && dd <= 31) && (dn >= 0 && dn <= 31) && (dm >= 0 && dm <= 31));
+            m_buffer.putInt(op | ((dd & 0xf) << 12) | ((dd & 0x10) << (22 - 4))
+                               | ((dn & 0xf) << 16) | ((dn & 0x10) << (7 - 4))
+                               | (dm & 0xf) | ((dm & 0x10) << (5 - 4)));
+        }
 
 
-        // Instruction formating
+        void emitSinglePrecisionInstruction(ARMWord op, int sd, int sn, int sm)
+        {
+            ASSERT((sd >= 0 && sd <= 31) && (sn >= 0 && sn <= 31) && (sm >= 0 && sm <= 31));
+            m_buffer.putInt(op | ((sd >> 1) << 12) | ((sd & 0x1) << 22)
+                               | ((sn >> 1) << 16) | ((sn & 0x1) << 7)
+                               | (sm >> 1) | ((sm & 0x1) << 5));
+        }
 
 
-        void emitInst(ARMWord op, int rd, int rn, ARMWord op2)
+        void bitAnd(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            ASSERT ( ((op2 & ~OP2_IMM) <= 0xfff) || (((op2 & ~OP2_IMMh) <= 0xfff)) );
-            m_buffer.putInt(op | RN(rn) | RD(rd) | op2);
+            emitInstruction(toARMWord(cc) | AND, rd, rn, op2);
         }
 
         }
 
-        void and_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void bitAnds(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | AND, rd, rn, op2);
+            emitInstruction(toARMWord(cc) | AND | SetConditionalCodes, rd, rn, op2);
         }
 
         }
 
-        void ands_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void eor(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | AND | SET_CC, rd, rn, op2);
+            emitInstruction(toARMWord(cc) | EOR, rd, rn, op2);
         }
 
         }
 
-        void eor_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void eors(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | EOR, rd, rn, op2);
+            emitInstruction(toARMWord(cc) | EOR | SetConditionalCodes, rd, rn, op2);
         }
 
         }
 
-        void eors_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void sub(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | EOR | SET_CC, rd, rn, op2);
+            emitInstruction(toARMWord(cc) | SUB, rd, rn, op2);
         }
 
         }
 
-        void sub_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void subs(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | SUB, rd, rn, op2);
+            emitInstruction(toARMWord(cc) | SUB | SetConditionalCodes, rd, rn, op2);
         }
 
         }
 
-        void subs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void rsb(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | SUB | SET_CC, rd, rn, op2);
+            emitInstruction(toARMWord(cc) | RSB, rd, rn, op2);
         }
 
         }
 
-        void rsb_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void rsbs(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | RSB, rd, rn, op2);
+            emitInstruction(toARMWord(cc) | RSB | SetConditionalCodes, rd, rn, op2);
         }
 
         }
 
-        void rsbs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void add(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | RSB | SET_CC, rd, rn, op2);
+            emitInstruction(toARMWord(cc) | ADD, rd, rn, op2);
         }
 
         }
 
-        void add_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void adds(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | ADD, rd, rn, op2);
+            emitInstruction(toARMWord(cc) | ADD | SetConditionalCodes, rd, rn, op2);
         }
 
         }
 
-        void adds_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void adc(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | ADD | SET_CC, rd, rn, op2);
+            emitInstruction(toARMWord(cc) | ADC, rd, rn, op2);
         }
 
         }
 
-        void adc_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void adcs(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | ADC, rd, rn, op2);
+            emitInstruction(toARMWord(cc) | ADC | SetConditionalCodes, rd, rn, op2);
         }
 
         }
 
-        void adcs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void sbc(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | ADC | SET_CC, rd, rn, op2);
+            emitInstruction(toARMWord(cc) | SBC, rd, rn, op2);
         }
 
         }
 
-        void sbc_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void sbcs(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | SBC, rd, rn, op2);
+            emitInstruction(toARMWord(cc) | SBC | SetConditionalCodes, rd, rn, op2);
         }
 
         }
 
-        void sbcs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void rsc(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | SBC | SET_CC, rd, rn, op2);
+            emitInstruction(toARMWord(cc) | RSC, rd, rn, op2);
         }
 
         }
 
-        void rsc_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void rscs(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | RSC, rd, rn, op2);
+            emitInstruction(toARMWord(cc) | RSC | SetConditionalCodes, rd, rn, op2);
         }
 
         }
 
-        void rscs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void tst(int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | RSC | SET_CC, rd, rn, op2);
+            emitInstruction(toARMWord(cc) | TST | SetConditionalCodes, 0, rn, op2);
         }
 
         }
 
-        void tst_r(int rn, ARMWord op2, Condition cc = AL)
+        void teq(int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | TST | SET_CC, 0, rn, op2);
+            emitInstruction(toARMWord(cc) | TEQ | SetConditionalCodes, 0, rn, op2);
         }
 
         }
 
-        void teq_r(int rn, ARMWord op2, Condition cc = AL)
+        void cmp(int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | TEQ | SET_CC, 0, rn, op2);
+            emitInstruction(toARMWord(cc) | CMP | SetConditionalCodes, 0, rn, op2);
         }
 
         }
 
-        void cmp_r(int rn, ARMWord op2, Condition cc = AL)
+        void cmn(int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | CMP | SET_CC, 0, rn, op2);
+            emitInstruction(toARMWord(cc) | CMN | SetConditionalCodes, 0, rn, op2);
         }
 
         }
 
-        void orr_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void orr(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | ORR, rd, rn, op2);
+            emitInstruction(toARMWord(cc) | ORR, rd, rn, op2);
         }
 
         }
 
-        void orrs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void orrs(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | ORR | SET_CC, rd, rn, op2);
+            emitInstruction(toARMWord(cc) | ORR | SetConditionalCodes, rd, rn, op2);
         }
 
         }
 
-        void mov_r(int rd, ARMWord op2, Condition cc = AL)
+        void mov(int rd, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | MOV, rd, ARMRegisters::r0, op2);
+            emitInstruction(toARMWord(cc) | MOV, rd, ARMRegisters::r0, op2);
         }
 
 #if WTF_ARM_ARCH_AT_LEAST(7)
         }
 
 #if WTF_ARM_ARCH_AT_LEAST(7)
-        void movw_r(int rd, ARMWord op2, Condition cc = AL)
+        void movw(int rd, ARMWord op2, Condition cc = AL)
         {
             ASSERT((op2 | 0xf0fff) == 0xf0fff);
         {
             ASSERT((op2 | 0xf0fff) == 0xf0fff);
-            m_buffer.putInt(static_cast<ARMWord>(cc) | MOVW | RD(rd) | op2);
+            m_buffer.putInt(toARMWord(cc) | MOVW | RD(rd) | op2);
         }
 
         }
 
-        void movt_r(int rd, ARMWord op2, Condition cc = AL)
+        void movt(int rd, ARMWord op2, Condition cc = AL)
         {
             ASSERT((op2 | 0xf0fff) == 0xf0fff);
         {
             ASSERT((op2 | 0xf0fff) == 0xf0fff);
-            m_buffer.putInt(static_cast<ARMWord>(cc) | MOVT | RD(rd) | op2);
+            m_buffer.putInt(toARMWord(cc) | MOVT | RD(rd) | op2);
         }
 #endif
 
         }
 #endif
 
-        void movs_r(int rd, ARMWord op2, Condition cc = AL)
+        void movs(int rd, ARMWord op2, Condition cc = AL)
+        {
+            emitInstruction(toARMWord(cc) | MOV | SetConditionalCodes, rd, ARMRegisters::r0, op2);
+        }
+
+        void bic(int rd, int rn, ARMWord op2, Condition cc = AL)
+        {
+            emitInstruction(toARMWord(cc) | BIC, rd, rn, op2);
+        }
+
+        void bics(int rd, int rn, ARMWord op2, Condition cc = AL)
+        {
+            emitInstruction(toARMWord(cc) | BIC | SetConditionalCodes, rd, rn, op2);
+        }
+
+        void mvn(int rd, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | MOV | SET_CC, rd, ARMRegisters::r0, op2);
+            emitInstruction(toARMWord(cc) | MVN, rd, ARMRegisters::r0, op2);
         }
 
         }
 
-        void bic_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void mvns(int rd, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | BIC, rd, rn, op2);
+            emitInstruction(toARMWord(cc) | MVN | SetConditionalCodes, rd, ARMRegisters::r0, op2);
         }
 
         }
 
-        void bics_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void mul(int rd, int rn, int rm, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | BIC | SET_CC, rd, rn, op2);
+            m_buffer.putInt(toARMWord(cc) | MUL | RN(rd) | RS(rn) | RM(rm));
         }
 
         }
 
-        void mvn_r(int rd, ARMWord op2, Condition cc = AL)
+        void muls(int rd, int rn, int rm, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | MVN, rd, ARMRegisters::r0, op2);
+            m_buffer.putInt(toARMWord(cc) | MUL | SetConditionalCodes | RN(rd) | RS(rn) | RM(rm));
         }
 
         }
 
-        void mvns_r(int rd, ARMWord op2, Condition cc = AL)
+        void mull(int rdhi, int rdlo, int rn, int rm, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | MVN | SET_CC, rd, ARMRegisters::r0, op2);
+            m_buffer.putInt(toARMWord(cc) | MULL | RN(rdhi) | RD(rdlo) | RS(rn) | RM(rm));
         }
 
         }
 
-        void mul_r(int rd, int rn, int rm, Condition cc = AL)
+        void vmov_f64(int dd, int dm, Condition cc = AL)
         {
         {
-            m_buffer.putInt(static_cast<ARMWord>(cc) | MUL | RN(rd) | RS(rn) | RM(rm));
+            emitDoublePrecisionInstruction(toARMWord(cc) | VMOV_F64, dd, 0, dm);
         }
 
         }
 
-        void muls_r(int rd, int rn, int rm, Condition cc = AL)
+        void vadd_f64(int dd, int dn, int dm, Condition cc = AL)
         {
         {
-            m_buffer.putInt(static_cast<ARMWord>(cc) | MUL | SET_CC | RN(rd) | RS(rn) | RM(rm));
+            emitDoublePrecisionInstruction(toARMWord(cc) | VADD_F64, dd, dn, dm);
         }
 
         }
 
-        void mull_r(int rdhi, int rdlo, int rn, int rm, Condition cc = AL)
+        void vdiv_f64(int dd, int dn, int dm, Condition cc = AL)
         {
         {
-            m_buffer.putInt(static_cast<ARMWord>(cc) | MULL | RN(rdhi) | RD(rdlo) | RS(rn) | RM(rm));
+            emitDoublePrecisionInstruction(toARMWord(cc) | VDIV_F64, dd, dn, dm);
         }
 
         }
 
-        void faddd_r(int dd, int dn, int dm, Condition cc = AL)
+        void vsub_f64(int dd, int dn, int dm, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | FADDD, dd, dn, dm);
+            emitDoublePrecisionInstruction(toARMWord(cc) | VSUB_F64, dd, dn, dm);
         }
 
         }
 
-        void fdivd_r(int dd, int dn, int dm, Condition cc = AL)
+        void vmul_f64(int dd, int dn, int dm, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | FDIVD, dd, dn, dm);
+            emitDoublePrecisionInstruction(toARMWord(cc) | VMUL_F64, dd, dn, dm);
         }
 
         }
 
-        void fsubd_r(int dd, int dn, int dm, Condition cc = AL)
+        void vcmp_f64(int dd, int dm, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | FSUBD, dd, dn, dm);
+            emitDoublePrecisionInstruction(toARMWord(cc) | VCMP_F64, dd, 0, dm);
         }
 
         }
 
-        void fmuld_r(int dd, int dn, int dm, Condition cc = AL)
+        void vsqrt_f64(int dd, int dm, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | FMULD, dd, dn, dm);
+            emitDoublePrecisionInstruction(toARMWord(cc) | VSQRT_F64, dd, 0, dm);
         }
 
         }
 
-        void fcmpd_r(int dd, int dm, Condition cc = AL)
+        void vabs_f64(int dd, int dm, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | FCMPD, dd, 0, dm);
+            emitDoublePrecisionInstruction(toARMWord(cc) | VABS_F64, dd, 0, dm);
         }
 
         }
 
-        void fsqrtd_r(int dd, int dm, Condition cc = AL)
+        void vneg_f64(int dd, int dm, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | FSQRTD, dd, 0, dm);
+            emitDoublePrecisionInstruction(toARMWord(cc) | VNEG_F64, dd, 0, dm);
         }
 
         }
 
-        void ldr_imm(int rd, ARMWord imm, Condition cc = AL)
+        void ldrImmediate(int rd, ARMWord imm, Condition cc = AL)
         {
         {
-            m_buffer.putIntWithConstantInt(static_cast<ARMWord>(cc) | DTR | DT_LOAD | DT_UP | RN(ARMRegisters::pc) | RD(rd), imm, true);
+            m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm, true);
         }
 
         }
 
-        void ldr_un_imm(int rd, ARMWord imm, Condition cc = AL)
+        void ldrUniqueImmediate(int rd, ARMWord imm, Condition cc = AL)
         {
         {
-            m_buffer.putIntWithConstantInt(static_cast<ARMWord>(cc) | DTR | DT_LOAD | DT_UP | RN(ARMRegisters::pc) | RD(rd), imm);
+            m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm);
         }
 
         }
 
-        void dtr_u(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL)
+        void dtrUp(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | DTR | (isLoad ? DT_LOAD : 0) | DT_UP, rd, rb, op2);
+            emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rb, op2);
         }
 
         }
 
-        void dtr_ur(bool isLoad, int rd, int rb, int rm, Condition cc = AL)
+        void dtrUpRegister(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | DTR | (isLoad ? DT_LOAD : 0) | DT_UP | OP2_OFSREG, rd, rb, rm);
+            emitInstruction(toARMWord(cc) | transferType | DataTransferUp | Op2IsRegisterArgument, rd, rb, rm);
         }
 
         }
 
-        void dtr_d(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL)
+        void dtrDown(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | DTR | (isLoad ? DT_LOAD : 0), rd, rb, op2);
+            emitInstruction(toARMWord(cc) | transferType, rd, rb, op2);
         }
 
         }
 
-        void dtr_dr(bool isLoad, int rd, int rb, int rm, Condition cc = AL)
+        void dtrDownRegister(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | DTR | (isLoad ? DT_LOAD : 0) | OP2_OFSREG, rd, rb, rm);
+            emitInstruction(toARMWord(cc) | transferType | Op2IsRegisterArgument, rd, rb, rm);
         }
 
         }
 
-        void ldrh_r(int rd, int rn, int rm, Condition cc = AL)
+        void halfDtrUp(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | LDRH | HDT_UH | DT_UP | DT_PRE, rd, rn, rm);
+            emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rb, op2);
         }
 
         }
 
-        void ldrh_d(int rd, int rb, ARMWord op2, Condition cc = AL)
+        void halfDtrUpRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | LDRH | HDT_UH | DT_PRE, rd, rb, op2);
+            emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rn, rm);
         }
 
         }
 
-        void ldrh_u(int rd, int rb, ARMWord op2, Condition cc = AL)
+        void halfDtrDown(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | LDRH | HDT_UH | DT_UP | DT_PRE, rd, rb, op2);
+            emitInstruction(toARMWord(cc) | transferType, rd, rb, op2);
         }
 
         }
 
-        void strh_r(int rn, int rm, int rd, Condition cc = AL)
+        void halfDtrDownRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | STRH | HDT_UH | DT_UP | DT_PRE, rd, rn, rm);
+            emitInstruction(toARMWord(cc) | transferType, rd, rn, rm);
         }
 
         }
 
-        void fdtr_u(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL)
+        void doubleDtrUp(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL)
         {
         {
-            ASSERT(op2 <= 0xff);
-            emitInst(static_cast<ARMWord>(cc) | FDTR | DT_UP | (isLoad ? DT_LOAD : 0), rd, rb, op2);
+            ASSERT(op2 <= 0xff && rd <= 15);
+            /* Only d0-d15 and s0, s2, s4 ... s30 are supported. */
+            m_buffer.putInt(toARMWord(cc) | DataTransferUp | type | (rd << 12) | RN(rb) | op2);
         }
 
         }
 
-        void fdtr_d(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL)
+        void doubleDtrDown(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL)
         {
         {
-            ASSERT(op2 <= 0xff);
-            emitInst(static_cast<ARMWord>(cc) | FDTR | (isLoad ? DT_LOAD : 0), rd, rb, op2);
+            ASSERT(op2 <= 0xff && rd <= 15);
+            /* Only d0-d15 and s0, s2, s4 ... s30 are supported. */
+            m_buffer.putInt(toARMWord(cc) | type | (rd << 12) | RN(rb) | op2);
         }
 
         }
 
-        void push_r(int reg, Condition cc = AL)
+        void push(int reg, Condition cc = AL)
         {
             ASSERT(ARMWord(reg) <= 0xf);
         {
             ASSERT(ARMWord(reg) <= 0xf);
-            m_buffer.putInt(cc | DTR | DT_WB | RN(ARMRegisters::sp) | RD(reg) | 0x4);
+            m_buffer.putInt(toARMWord(cc) | StoreUint32 | DataTransferWriteBack | RN(ARMRegisters::sp) | RD(reg) | 0x4);
         }
 
         }
 
-        void pop_r(int reg, Condition cc = AL)
+        void pop(int reg, Condition cc = AL)
         {
             ASSERT(ARMWord(reg) <= 0xf);
         {
             ASSERT(ARMWord(reg) <= 0xf);
-            m_buffer.putInt(cc | (DTR ^ DT_PRE) | DT_LOAD | DT_UP | RN(ARMRegisters::sp) | RD(reg) | 0x4);
+            m_buffer.putInt(toARMWord(cc) | (LoadUint32 ^ DataTransferPostUpdate) | DataTransferUp | RN(ARMRegisters::sp) | RD(reg) | 0x4);
         }
 
         }
 
-        inline void poke_r(int reg, Condition cc = AL)
+        inline void poke(int reg, Condition cc = AL)
         {
         {
-            dtr_d(false, ARMRegisters::sp, 0, reg, cc);
+            dtrDown(StoreUint32, ARMRegisters::sp, 0, reg, cc);
         }
 
         }
 
-        inline void peek_r(int reg, Condition cc = AL)
+        inline void peek(int reg, Condition cc = AL)
         {
         {
-            dtr_u(true, reg, ARMRegisters::sp, 0, cc);
+            dtrUp(LoadUint32, reg, ARMRegisters::sp, 0, cc);
         }
 
         }
 
-        void fmsr_r(int dd, int rn, Condition cc = AL)
+        void vmov_vfp64(int sm, int rt, int rt2, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | FMSR, rn, dd, 0);
+            ASSERT(rt != rt2);
+            m_buffer.putInt(toARMWord(cc) | VMOV_VFP64 | RN(rt2) | RD(rt) | (sm & 0xf) | ((sm & 0x10) << (5 - 4)));
         }
 
         }
 
-        void fmrs_r(int rd, int dn, Condition cc = AL)
+        void vmov_arm64(int rt, int rt2, int sm, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | FMRS, rd, dn, 0);
+            ASSERT(rt != rt2);
+            m_buffer.putInt(toARMWord(cc) | VMOV_ARM64 | RN(rt2) | RD(rt) | (sm & 0xf) | ((sm & 0x10) << (5 - 4)));
         }
 
         }
 
-        void fsitod_r(int dd, int dm, Condition cc = AL)
+        void vmov_vfp32(int sn, int rt, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | FSITOD, dd, 0, dm);
+            ASSERT(rt <= 15);
+            emitSinglePrecisionInstruction(toARMWord(cc) | VMOV_VFP32, rt << 1, sn, 0);
         }
 
         }
 
-        void ftosid_r(int fd, int dm, Condition cc = AL)
+        void vmov_arm32(int rt, int sn, Condition cc = AL)
         {
         {
-            emitInst(static_cast<ARMWord>(cc) | FTOSID, fd, 0, dm);
+            ASSERT(rt <= 15);
+            emitSinglePrecisionInstruction(toARMWord(cc) | VMOV_ARM32, rt << 1, sn, 0);
         }
 
         }
 
-        void fmstat(Condition cc = AL)
+        void vcvt_f64_s32(int dd, int sm, Condition cc = AL)
         {
         {
-            m_buffer.putInt(static_cast<ARMWord>(cc) | FMSTAT);
+            ASSERT(!(sm & 0x1)); // sm must be divisible by 2
+            emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_F64_S32, dd, 0, (sm >> 1));
         }
 
         }
 
-#if WTF_ARM_ARCH_AT_LEAST(5)
-        void clz_r(int rd, int rm, Condition cc = AL)
+        void vcvt_s32_f64(int sd, int dm, Condition cc = AL)
         {
         {
-            m_buffer.putInt(static_cast<ARMWord>(cc) | CLZ | RD(rd) | RM(rm));
+            ASSERT(!(sd & 0x1)); // sd must be divisible by 2
+            emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_S32_F64, (sd >> 1), 0, dm);
+        }
+
+        void vcvt_u32_f64(int sd, int dm, Condition cc = AL)
+        {
+            ASSERT(!(sd & 0x1)); // sd must be divisible by 2
+            emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_U32_F64, (sd >> 1), 0, dm);
+        }
+
+        void vcvt_f64_f32(int dd, int sm, Condition cc = AL)
+        {
+            ASSERT(dd <= 15 && sm <= 15);
+            emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_F64_F32, dd, 0, sm);
+        }
+
+        void vcvt_f32_f64(int dd, int sm, Condition cc = AL)
+        {
+            ASSERT(dd <= 15 && sm <= 15);
+            emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_F32_F64, dd, 0, sm);
+        }
+
+        void vmrs_apsr(Condition cc = AL)
+        {
+            m_buffer.putInt(toARMWord(cc) | VMRS_APSR);
+        }
+
+        void clz(int rd, int rm, Condition cc = AL)
+        {
+            m_buffer.putInt(toARMWord(cc) | CLZ | RD(rd) | RM(rm));
         }
         }
-#endif
 
         void bkpt(ARMWord value)
         {
 
         void bkpt(ARMWord value)
         {
-#if WTF_ARM_ARCH_AT_LEAST(5)
             m_buffer.putInt(BKPT | ((value & 0xff0) << 4) | (value & 0xf));
             m_buffer.putInt(BKPT | ((value & 0xff0) << 4) | (value & 0xf));
-#else
-            // Cannot access to Zero memory address
-            dtr_dr(true, ARMRegisters::S0, ARMRegisters::S0, ARMRegisters::S0);
-#endif
+        }
+
+        void nop()
+        {
+            m_buffer.putInt(NOP);
+        }
+
+        void dmbSY()
+        {
+            m_buffer.putInt(DMB_SY);
         }
 
         void bx(int rm, Condition cc = AL)
         {
         }
 
         void bx(int rm, Condition cc = AL)
         {
-#if WTF_ARM_ARCH_AT_LEAST(5) || defined(__ARM_ARCH_4T__)
-            emitInst(static_cast<ARMWord>(cc) | BX, 0, 0, RM(rm));
-#else
-            mov_r(ARMRegisters::pc, RM(rm), cc);
-#endif
+            emitInstruction(toARMWord(cc) | BX, 0, 0, RM(rm));
         }
 
         }
 
-        JmpSrc blx(int rm, Condition cc = AL)
+        AssemblerLabel blx(int rm, Condition cc = AL)
         {
         {
-#if WTF_ARM_ARCH_AT_LEAST(5)
-            int s = m_buffer.uncheckedSize();
-            emitInst(static_cast<ARMWord>(cc) | BLX, 0, 0, RM(rm));
-#else
-            ASSERT(rm != 14);
-            ensureSpace(2 * sizeof(ARMWord), 0);
-            mov_r(ARMRegisters::lr, ARMRegisters::pc, cc);
-            int s = m_buffer.uncheckedSize();
-            bx(rm, cc);
-#endif
-            return JmpSrc(s);
+            emitInstruction(toARMWord(cc) | BLX, 0, 0, RM(rm));
+            return m_buffer.label();
         }
 
         static ARMWord lsl(int reg, ARMWord value)
         }
 
         static ARMWord lsl(int reg, ARMWord value)
@@ -603,21 +734,21 @@ namespace JSC {
             return reg | (value << 7) | 0x40;
         }
 
             return reg | (value << 7) | 0x40;
         }
 
-        static ARMWord lsl_r(int reg, int shiftReg)
+        static ARMWord lslRegister(int reg, int shiftReg)
         {
             ASSERT(reg <= ARMRegisters::pc);
             ASSERT(shiftReg <= ARMRegisters::pc);
             return reg | (shiftReg << 8) | 0x10;
         }
 
         {
             ASSERT(reg <= ARMRegisters::pc);
             ASSERT(shiftReg <= ARMRegisters::pc);
             return reg | (shiftReg << 8) | 0x10;
         }
 
-        static ARMWord lsr_r(int reg, int shiftReg)
+        static ARMWord lsrRegister(int reg, int shiftReg)
         {
             ASSERT(reg <= ARMRegisters::pc);
             ASSERT(shiftReg <= ARMRegisters::pc);
             return reg | (shiftReg << 8) | 0x30;
         }
 
         {
             ASSERT(reg <= ARMRegisters::pc);
             ASSERT(shiftReg <= ARMRegisters::pc);
             return reg | (shiftReg << 8) | 0x30;
         }
 
-        static ARMWord asr_r(int reg, int shiftReg)
+        static ARMWord asrRegister(int reg, int shiftReg)
         {
             ASSERT(reg <= ARMRegisters::pc);
             ASSERT(shiftReg <= ARMRegisters::pc);
         {
             ASSERT(reg <= ARMRegisters::pc);
             ASSERT(shiftReg <= ARMRegisters::pc);
@@ -626,9 +757,9 @@ namespace JSC {
 
         // General helpers
 
 
         // General helpers
 
-        int size()
+        size_t codeSize() const
         {
         {
-            return m_buffer.size();
+            return m_buffer.codeSize();
         }
 
         void ensureSpace(int insnSpace, int constSpace)
         }
 
         void ensureSpace(int insnSpace, int constSpace)
@@ -641,63 +772,96 @@ namespace JSC {
             return m_buffer.sizeOfConstantPool();
         }
 
             return m_buffer.sizeOfConstantPool();
         }
 
-        JmpDst label()
+        AssemblerLabel labelIgnoringWatchpoints()
         {
         {
-            return JmpDst(m_buffer.size());
+            m_buffer.ensureSpaceForAnyInstruction();
+            return m_buffer.label();
         }
 
         }
 
-        JmpDst align(int alignment)
+        AssemblerLabel labelForWatchpoint()
+        {
+            m_buffer.ensureSpaceForAnyInstruction(maxJumpReplacementSize() / sizeof(ARMWord));
+            AssemblerLabel result = m_buffer.label();
+            if (result.m_offset != (m_indexOfTailOfLastWatchpoint - maxJumpReplacementSize()))
+                result = label();
+            m_indexOfTailOfLastWatchpoint = result.m_offset + maxJumpReplacementSize();
+            return label();
+        }
+
+        AssemblerLabel label()
+        {
+            AssemblerLabel result = labelIgnoringWatchpoints();
+            while (result.m_offset + 1 < m_indexOfTailOfLastWatchpoint) {
+                nop();
+                // The available number of instructions are ensured by labelForWatchpoint.
+                result = m_buffer.label();
+            }
+            return result;
+        }
+
+        AssemblerLabel align(int alignment)
         {
             while (!m_buffer.isAligned(alignment))
         {
             while (!m_buffer.isAligned(alignment))
-                mov_r(ARMRegisters::r0, ARMRegisters::r0);
+                mov(ARMRegisters::r0, ARMRegisters::r0);
 
             return label();
         }
 
 
             return label();
         }
 
-        JmpSrc loadBranchTarget(int rd, Condition cc = AL, int useConstantPool = 0)
+        AssemblerLabel loadBranchTarget(int rd, Condition cc = AL, int useConstantPool = 0)
         {
             ensureSpace(sizeof(ARMWord), sizeof(ARMWord));
         {
             ensureSpace(sizeof(ARMWord), sizeof(ARMWord));
-            int s = m_buffer.uncheckedSize();
-            ldr_un_imm(rd, InvalidBranchTarget, cc);
-            m_jumps.append(s | (useConstantPool & 0x1));
-            return JmpSrc(s);
+            m_jumps.append(m_buffer.codeSize() | (useConstantPool & 0x1));
+            ldrUniqueImmediate(rd, InvalidBranchTarget, cc);
+            return m_buffer.label();
         }
 
         }
 
-        JmpSrc jmp(Condition cc = AL, int useConstantPool = 0)
+        AssemblerLabel jmp(Condition cc = AL, int useConstantPool = 0)
         {
             return loadBranchTarget(ARMRegisters::pc, cc, useConstantPool);
         }
 
         {
             return loadBranchTarget(ARMRegisters::pc, cc, useConstantPool);
         }
 
-        void* executableCopy(ExecutablePool* allocator);
+        void prepareExecutableCopy(void* to);
+
+        unsigned debugOffset() { return m_buffer.debugOffset(); }
+
+        // DFG assembly helpers for moving data between fp and registers.
+        void vmov(RegisterID rd1, RegisterID rd2, FPRegisterID rn)
+        {
+            vmov_arm64(rd1, rd2, rn);
+        }
+
+        void vmov(FPRegisterID rd, RegisterID rn1, RegisterID rn2)
+        {
+            vmov_vfp64(rd, rn1, rn2);
+        }
 
         // Patching helpers
 
         static ARMWord* getLdrImmAddress(ARMWord* insn)
         {
 
         // Patching helpers
 
         static ARMWord* getLdrImmAddress(ARMWord* insn)
         {
-#if WTF_ARM_ARCH_AT_LEAST(5)
             // Check for call
             // Check for call
-            if ((*insn & 0x0f7f0000) != 0x051f0000) {
+            if ((*insn & LdrPcImmediateInstructionMask) != LdrPcImmediateInstruction) {
                 // Must be BLX
                 // Must be BLX
-                ASSERT((*insn & 0x012fff30) == 0x012fff30);
+                ASSERT((*insn & BlxInstructionMask) == BlxInstruction);
                 insn--;
             }
                 insn--;
             }
-#endif
+
             // Must be an ldr ..., [pc +/- imm]
             // Must be an ldr ..., [pc +/- imm]
-            ASSERT((*insn & 0x0f7f0000) == 0x051f0000);
+            ASSERT((*insn & LdrPcImmediateInstructionMask) == LdrPcImmediateInstruction);
 
 
-            ARMWord addr = reinterpret_cast<ARMWord>(insn) + DefaultPrefetching * sizeof(ARMWord);
-            if (*insn & DT_UP)
-                return reinterpret_cast<ARMWord*>(addr + (*insn & SDT_OFFSET_MASK));
-            return reinterpret_cast<ARMWord*>(addr - (*insn & SDT_OFFSET_MASK));
+            ARMWord addr = reinterpret_cast<ARMWord>(insn) + DefaultPrefetchOffset * sizeof(ARMWord);
+            if (*insn & DataTransferUp)
+                return reinterpret_cast<ARMWord*>(addr + (*insn & DataTransferOffsetMask));
+            return reinterpret_cast<ARMWord*>(addr - (*insn & DataTransferOffsetMask));
         }
 
         static ARMWord* getLdrImmAddressOnPool(ARMWord* insn, uint32_t* constPool)
         {
             // Must be an ldr ..., [pc +/- imm]
         }
 
         static ARMWord* getLdrImmAddressOnPool(ARMWord* insn, uint32_t* constPool)
         {
             // Must be an ldr ..., [pc +/- imm]
-            ASSERT((*insn & 0x0f7f0000) == 0x051f0000);
+            ASSERT((*insn & LdrPcImmediateInstructionMask) == LdrPcImmediateInstruction);
 
             if (*insn & 0x1)
 
             if (*insn & 0x1)
-                return reinterpret_cast<ARMWord*>(constPool + ((*insn & SDT_OFFSET_MASK) >> 1));
+                return reinterpret_cast<ARMWord*>(constPool + ((*insn & DataTransferOffsetMask) >> 1));
             return getLdrImmAddress(insn);
         }
 
             return getLdrImmAddress(insn);
         }
 
@@ -711,114 +875,189 @@ namespace JSC {
         static ARMWord patchConstantPoolLoad(ARMWord load, ARMWord value)
         {
             value = (value << 1) + 1;
         static ARMWord patchConstantPoolLoad(ARMWord load, ARMWord value)
         {
             value = (value << 1) + 1;
-            ASSERT(!(value & ~0xfff));
-            return (load & ~0xfff) | value;
+            ASSERT(!(value & ~DataTransferOffsetMask));
+            return (load & ~DataTransferOffsetMask) | value;
         }
 
         static void patchConstantPoolLoad(void* loadAddr, void* constPoolAddr);
 
         }
 
         static void patchConstantPoolLoad(void* loadAddr, void* constPoolAddr);
 
+        // Read pointers
+        static void* readPointer(void* from)
+        {
+            ARMWord* instruction = reinterpret_cast<ARMWord*>(from);
+            ARMWord* address = getLdrImmAddress(instruction);
+            return *reinterpret_cast<void**>(address);
+        }
+
         // Patch pointers
 
         // Patch pointers
 
-        static void linkPointer(void* code, JmpDst from, void* to)
+        static void linkPointer(void* code, AssemblerLabel from, void* to)
         {
             patchPointerInternal(reinterpret_cast<intptr_t>(code) + from.m_offset, to);
         }
 
         {
             patchPointerInternal(reinterpret_cast<intptr_t>(code) + from.m_offset, to);
         }
 
-        static void repatchInt32(void* from, int32_t to)
+        static void repatchInt32(void* where, int32_t to)
         {
         {
-            patchPointerInternal(reinterpret_cast<intptr_t>(from), reinterpret_cast<void*>(to));
+            patchPointerInternal(reinterpret_cast<intptr_t>(where), reinterpret_cast<void*>(to));
         }
 
         }
 
-        static void repatchPointer(void* from, void* to)
+        static void repatchCompact(void* where, int32_t value)
         {
         {
-            patchPointerInternal(reinterpret_cast<intptr_t>(from), to);
+            ARMWord* instruction = reinterpret_cast<ARMWord*>(where);
+            ASSERT((*instruction & 0x0f700000) == LoadUint32);
+            if (value >= 0)
+                *instruction = (*instruction & 0xff7ff000) | DataTransferUp | value;
+            else
+                *instruction = (*instruction & 0xff7ff000) | -value;
+            cacheFlush(instruction, sizeof(ARMWord));
         }
 
         }
 
-        static void repatchLoadPtrToLEA(void* from)
+        static void repatchPointer(void* from, void* to)
         {
         {
-            // On arm, this is a patch from LDR to ADD. It is restricted conversion,
-            // from special case to special case, altough enough for its purpose
-            ARMWord* insn = reinterpret_cast<ARMWord*>(from);
-            ASSERT((*insn & 0x0ff00f00) == 0x05900000);
-
-            *insn = (*insn & 0xf00ff0ff) | 0x02800000;
-            ExecutableAllocator::cacheFlush(insn, sizeof(ARMWord));
+            patchPointerInternal(reinterpret_cast<intptr_t>(from), to);
         }
 
         // Linkers
         }
 
         // Linkers
+        static intptr_t getAbsoluteJumpAddress(void* base, int offset = 0)
+        {
+            return reinterpret_cast<intptr_t>(base) + offset - sizeof(ARMWord);
+        }
 
 
-        void linkJump(JmpSrc from, JmpDst to)
+        void linkJump(AssemblerLabel from, AssemblerLabel to)
         {
         {
-            ARMWord* insn = reinterpret_cast<ARMWord*>(m_buffer.data()) + (from.m_offset / sizeof(ARMWord));
+            ARMWord* insn = reinterpret_cast<ARMWord*>(getAbsoluteJumpAddress(m_buffer.data(), from.m_offset));
             ARMWord* addr = getLdrImmAddressOnPool(insn, m_buffer.poolAddress());
             ARMWord* addr = getLdrImmAddressOnPool(insn, m_buffer.poolAddress());
-            *addr = static_cast<ARMWord>(to.m_offset);
+            *addr = toARMWord(to.m_offset);
         }
 
         }
 
-        static void linkJump(void* code, JmpSrc from, void* to)
+        static void linkJump(void* code, AssemblerLabel from, void* to)
         {
         {
-            patchPointerInternal(reinterpret_cast<intptr_t>(code) + from.m_offset, to);
+            patchPointerInternal(getAbsoluteJumpAddress(code, from.m_offset), to);
         }
 
         static void relinkJump(void* from, void* to)
         {
         }
 
         static void relinkJump(void* from, void* to)
         {
-            patchPointerInternal(reinterpret_cast<intptr_t>(from) - sizeof(ARMWord), to);
+            patchPointerInternal(getAbsoluteJumpAddress(from), to);
         }
 
         }
 
-        static void linkCall(void* code, JmpSrc from, void* to)
+        static void linkCall(void* code, AssemblerLabel from, void* to)
         {
         {
-            patchPointerInternal(reinterpret_cast<intptr_t>(code) + from.m_offset, to);
+            patchPointerInternal(getAbsoluteJumpAddress(code, from.m_offset), to);
         }
 
         static void relinkCall(void* from, void* to)
         {
         }
 
         static void relinkCall(void* from, void* to)
         {
-            patchPointerInternal(reinterpret_cast<intptr_t>(from) - sizeof(ARMWord), to);
+            patchPointerInternal(getAbsoluteJumpAddress(from), to);
         }
 
         }
 
-        // Address operations
+        static void* readCallTarget(void* from)
+        {
+            return reinterpret_cast<void*>(readPointer(reinterpret_cast<void*>(getAbsoluteJumpAddress(from))));
+        }
 
 
-        static void* getRelocatedAddress(void* code, JmpSrc jump)
+        static void replaceWithJump(void* instructionStart, void* to)
         {
         {
-            return reinterpret_cast<void*>(reinterpret_cast<ARMWord*>(code) + jump.m_offset / sizeof(ARMWord) + 1);
+            ARMWord* instruction = reinterpret_cast<ARMWord*>(instructionStart);
+            intptr_t difference = reinterpret_cast<intptr_t>(to) - (reinterpret_cast<intptr_t>(instruction) + DefaultPrefetchOffset * sizeof(ARMWord));
+
+            if (!(difference & 1)) {
+                difference >>= 2;
+                if ((difference <= MaximumBranchOffsetDistance && difference >= MinimumBranchOffsetDistance)) {
+                     // Direct branch.
+                     instruction[0] = B | AL | (difference & BranchOffsetMask);
+                     cacheFlush(instruction, sizeof(ARMWord));
+                     return;
+                }
+            }
+
+            // Load target.
+            instruction[0] = LoadUint32 | AL | RN(ARMRegisters::pc) | RD(ARMRegisters::pc) | 4;
+            instruction[1] = reinterpret_cast<ARMWord>(to);
+            cacheFlush(instruction, sizeof(ARMWord) * 2);
         }
 
         }
 
-        static void* getRelocatedAddress(void* code, JmpDst label)
+        static ptrdiff_t maxJumpReplacementSize()
         {
         {
-            return reinterpret_cast<void*>(reinterpret_cast<ARMWord*>(code) + label.m_offset / sizeof(ARMWord));
+            return sizeof(ARMWord) * 2;
         }
 
         }
 
-        // Address differences
+        static void replaceWithLoad(void* instructionStart)
+        {
+            ARMWord* instruction = reinterpret_cast<ARMWord*>(instructionStart);
+            cacheFlush(instruction, sizeof(ARMWord));
 
 
-        static int getDifferenceBetweenLabels(JmpDst from, JmpSrc to)
+            ASSERT((*instruction & LdrOrAddInstructionMask) == AddImmediateInstruction || (*instruction & LdrOrAddInstructionMask) == LdrImmediateInstruction);
+            if ((*instruction & LdrOrAddInstructionMask) == AddImmediateInstruction) {
+                 *instruction = (*instruction & ~LdrOrAddInstructionMask) | LdrImmediateInstruction;
+                 cacheFlush(instruction, sizeof(ARMWord));
+            }
+        }
+
+        static void replaceWithAddressComputation(void* instructionStart)
         {
         {
-            return (to.m_offset + sizeof(ARMWord)) - from.m_offset;
+            ARMWord* instruction = reinterpret_cast<ARMWord*>(instructionStart);
+            cacheFlush(instruction, sizeof(ARMWord));
+
+            ASSERT((*instruction & LdrOrAddInstructionMask) == AddImmediateInstruction || (*instruction & LdrOrAddInstructionMask) == LdrImmediateInstruction);
+            if ((*instruction & LdrOrAddInstructionMask) == LdrImmediateInstruction) {
+                 *instruction = (*instruction & ~LdrOrAddInstructionMask) | AddImmediateInstruction;
+                 cacheFlush(instruction, sizeof(ARMWord));
+            }
+        }
+
+        static void revertBranchPtrWithPatch(void* instructionStart, RegisterID rn, ARMWord imm)
+        {
+            ARMWord* instruction = reinterpret_cast<ARMWord*>(instructionStart);
+
+            ASSERT((instruction[2] & LdrPcImmediateInstructionMask) == LdrPcImmediateInstruction);
+            instruction[0] = toARMWord(AL) | ((instruction[2] & 0x0fff0fff) + sizeof(ARMWord)) | RD(ARMRegisters::S1);
+            *getLdrImmAddress(instruction) = imm;
+            instruction[1] = toARMWord(AL) | CMP | SetConditionalCodes | RN(rn) | RM(ARMRegisters::S1);
+            cacheFlush(instruction, 2 * sizeof(ARMWord));
+        }
+
+        // Address operations
+
+        static void* getRelocatedAddress(void* code, AssemblerLabel label)
+        {
+            return reinterpret_cast<void*>(reinterpret_cast<char*>(code) + label.m_offset);
         }
 
         }
 
-        static int getDifferenceBetweenLabels(JmpDst from, JmpDst to)
+        // Address differences
+
+        static int getDifferenceBetweenLabels(AssemblerLabel a, AssemblerLabel b)
         {
         {
-            return to.m_offset - from.m_offset;
+            return b.m_offset - a.m_offset;
         }
 
         }
 
-        static unsigned getCallReturnOffset(JmpSrc call)
+        static unsigned getCallReturnOffset(AssemblerLabel call)
         {
         {
-            return call.m_offset + sizeof(ARMWord);
+            return call.m_offset;
         }
 
         // Handle immediates
 
         }
 
         // Handle immediates
 
+        static ARMWord getOp2(ARMWord imm);
+
+        // Fast case if imm is known to be between 0 and 0xff
         static ARMWord getOp2Byte(ARMWord imm)
         {
             ASSERT(imm <= 0xff);
         static ARMWord getOp2Byte(ARMWord imm)
         {
             ASSERT(imm <= 0xff);
-            return OP2_IMMh | (imm & 0x0f) | ((imm & 0xf0) << 4) ;
+            return Op2Immediate | imm;
         }
 
         }
 
-        static ARMWord getOp2(ARMWord imm);
+        static ARMWord getOp2Half(ARMWord imm)
+        {
+            ASSERT(imm <= 0xff);
+            return ImmediateForHalfWordTransfer | (imm & 0x0f) | ((imm & 0xf0) << 4);
+        }
 
 #if WTF_ARM_ARCH_AT_LEAST(7)
         static ARMWord getImm16Op2(ARMWord imm)
         {
             if (imm <= 0xffff)
                 return (imm & 0xf000) << 4 | (imm & 0xfff);
 
 #if WTF_ARM_ARCH_AT_LEAST(7)
         static ARMWord getImm16Op2(ARMWord imm)
         {
             if (imm <= 0xffff)
                 return (imm & 0xf000) << 4 | (imm & 0xfff);
-            return INVALID_IMM;
+            return InvalidImmediate;
         }
 #endif
         ARMWord getImm(ARMWord imm, int tmpReg, bool invert = false);
         }
 #endif
         ARMWord getImm(ARMWord imm, int tmpReg, bool invert = false);
@@ -827,39 +1066,86 @@ namespace JSC {
 
         // Memory load/store helpers
 
 
         // Memory load/store helpers
 
-        void dataTransfer32(bool isLoad, RegisterID srcDst, RegisterID base, int32_t offset, bool bytes = false);
-        void baseIndexTransfer32(bool isLoad, RegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset);
-        void doubleTransfer(bool isLoad, FPRegisterID srcDst, RegisterID base, int32_t offset);
+        void dataTransfer32(DataTransferTypeA, RegisterID srcDst, RegisterID base, int32_t offset);
+        void baseIndexTransfer32(DataTransferTypeA, RegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset);
+        void dataTransfer16(DataTransferTypeB, RegisterID srcDst, RegisterID base, int32_t offset);
+        void baseIndexTransfer16(DataTransferTypeB, RegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset);
+        void dataTransferFloat(DataTransferTypeFloat, FPRegisterID srcDst, RegisterID base, int32_t offset);
+        void baseIndexTransferFloat(DataTransferTypeFloat, FPRegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset);
 
         // Constant pool hnadlers
 
         static ARMWord placeConstantPoolBarrier(int offset)
         {
             offset = (offset - sizeof(ARMWord)) >> 2;
 
         // Constant pool hnadlers
 
         static ARMWord placeConstantPoolBarrier(int offset)
         {
             offset = (offset - sizeof(ARMWord)) >> 2;
-            ASSERT((offset <= BOFFSET_MAX && offset >= BOFFSET_MIN));
-            return AL | B | (offset & BRANCH_MASK);
+            ASSERT((offset <= MaximumBranchOffsetDistance && offset >= MinimumBranchOffsetDistance));
+            return AL | B | (offset & BranchOffsetMask);
+        }
+
+#if OS(LINUX) && COMPILER(GCC)
+        static inline void linuxPageFlush(uintptr_t begin, uintptr_t end)
+        {
+            asm volatile(
+                "push    {r7}\n"
+                "mov     r0, %0\n"
+                "mov     r1, %1\n"
+                "mov     r7, #0xf0000\n"
+                "add     r7, r7, #0x2\n"
+                "mov     r2, #0x0\n"
+                "svc     0x0\n"
+                "pop     {r7}\n"
+                :
+                : "r" (begin), "r" (end)
+                : "r0", "r1", "r2");
+        }
+#endif
+
+        static void cacheFlush(void* code, size_t size)
+        {
+#if OS(LINUX) && COMPILER(GCC)
+            size_t page = pageSize();
+            uintptr_t current = reinterpret_cast<uintptr_t>(code);
+            uintptr_t end = current + size;
+            uintptr_t firstPageEnd = (current & ~(page - 1)) + page;
+
+            if (end <= firstPageEnd) {
+                linuxPageFlush(current, end);
+                return;
+            }
+
+            linuxPageFlush(current, firstPageEnd);
+
+            for (current = firstPageEnd; current + page < end; current += page)
+                linuxPageFlush(current, current + page);
+
+            linuxPageFlush(current, end);
+#elif OS(WINCE)
+            CacheRangeFlush(code, size, CACHE_SYNC_ALL);
+#else
+#error "The cacheFlush support is missing on this platform."
+#endif
         }
 
     private:
         }
 
     private:
-        ARMWord RM(int reg)
+        static ARMWord RM(int reg)
         {
             ASSERT(reg <= ARMRegisters::pc);
             return reg;
         }
 
         {
             ASSERT(reg <= ARMRegisters::pc);
             return reg;
         }
 
-        ARMWord RS(int reg)
+        static ARMWord RS(int reg)
         {
             ASSERT(reg <= ARMRegisters::pc);
             return reg << 8;
         }
 
         {
             ASSERT(reg <= ARMRegisters::pc);
             return reg << 8;
         }
 
-        ARMWord RD(int reg)
+        static ARMWord RD(int reg)
         {
             ASSERT(reg <= ARMRegisters::pc);
             return reg << 12;
         }
 
         {
             ASSERT(reg <= ARMRegisters::pc);
             return reg << 12;
         }
 
-        ARMWord RN(int reg)
+        static ARMWord RN(int reg)
         {
             ASSERT(reg <= ARMRegisters::pc);
             return reg << 16;
         {
             ASSERT(reg <= ARMRegisters::pc);
             return reg << 16;
@@ -867,13 +1153,24 @@ namespace JSC {
 
         static ARMWord getConditionalField(ARMWord i)
         {
 
         static ARMWord getConditionalField(ARMWord i)
         {
-            return i & 0xf0000000;
+            return i & ConditionalFieldMask;
+        }
+
+        static ARMWord toARMWord(Condition cc)
+        {
+            return static_cast<ARMWord>(cc);
+        }
+
+        static ARMWord toARMWord(uint32_t u)
+        {
+            return static_cast<ARMWord>(u);
         }
 
         int genInt(int reg, ARMWord imm, bool positive);
 
         ARMBuffer m_buffer;
         Jumps m_jumps;
         }
 
         int genInt(int reg, ARMWord imm, bool positive);
 
         ARMBuffer m_buffer;
         Jumps m_jumps;
+        uint32_t m_indexOfTailOfLastWatchpoint;
     };
 
 } // namespace JSC
     };
 
 } // namespace JSC
mirror of JavaScriptCore