r0 = 0,
r1,
r2,
- r3, S0 = r3, /* Same as thumb assembler. */
+ r3,
r4,
r5,
- r6,
+ r6, S0 = r6,
r7,
r8,
r9,
r10,
- r11,
- r12, S1 = r12,
+ r11, fp = r11, // frame pointer
+ r12, ip = r12, S1 = r12,
r13, sp = r13,
r14, lr = r14,
r15, pc = r15
d31
} FPRegisterID;
+#if USE(MASM_PROBE)
+ #define FOR_EACH_CPU_REGISTER(V) \
+ FOR_EACH_CPU_GPREGISTER(V) \
+ FOR_EACH_CPU_SPECIAL_REGISTER(V) \
+ FOR_EACH_CPU_FPREGISTER(V)
+
+ #define FOR_EACH_CPU_GPREGISTER(V) \
+ V(void*, r0) \
+ V(void*, r1) \
+ V(void*, r2) \
+ V(void*, r3) \
+ V(void*, r4) \
+ V(void*, r5) \
+ V(void*, r6) \
+ V(void*, r7) \
+ V(void*, r8) \
+ V(void*, r9) \
+ V(void*, r10) \
+ V(void*, r11) \
+ V(void*, ip) \
+ V(void*, sp) \
+ V(void*, lr) \
+ V(void*, pc)
+
+ #define FOR_EACH_CPU_SPECIAL_REGISTER(V) \
+ V(void*, apsr) \
+ V(void*, fpscr) \
+
+ #define FOR_EACH_CPU_FPREGISTER(V) \
+ V(double, d0) \
+ V(double, d1) \
+ V(double, d2) \
+ V(double, d3) \
+ V(double, d4) \
+ V(double, d5) \
+ V(double, d6) \
+ V(double, d7) \
+ V(double, d8) \
+ V(double, d9) \
+ V(double, d10) \
+ V(double, d11) \
+ V(double, d12) \
+ V(double, d13) \
+ V(double, d14) \
+ V(double, d15)
+#endif // USE(MASM_PROBE)
} // namespace ARMRegisters
class ARMAssembler {
{
}
+ ARMBuffer& buffer() { return m_buffer; }
+
+ static RegisterID firstRegister() { return ARMRegisters::r0; }
+ static RegisterID lastRegister() { return ARMRegisters::r15; }
+
+ static FPRegisterID firstFPRegister() { return ARMRegisters::d0; }
+ static FPRegisterID lastFPRegister() { return ARMRegisters::d31; }
+
// ARM conditional constants
typedef enum {
EQ = 0x00000000, // Zero / Equal.
MOVT = 0x03400000,
#endif
NOP = 0xe1a00000,
+ DMB_SY = 0xf57ff05f,
};
enum {
m_buffer.putInt(NOP);
}
+ void dmbSY()
+ {
+ m_buffer.putInt(DMB_SY);
+ }
+
void bx(int rm, Condition cc = AL)
{
emitInstruction(toARMWord(cc) | BX, 0, 0, RM(rm));
return loadBranchTarget(ARMRegisters::pc, cc, useConstantPool);
}
- PassRefPtr<ExecutableMemoryHandle> executableCopy(VM&, void* ownerUID, JITCompilationEffort);
+ void prepareExecutableCopy(void* to);
unsigned debugOffset() { return m_buffer.debugOffset(); }
}
#endif
-#if OS(LINUX) && COMPILER(RVCT)
- static __asm void cacheFlush(void* code, size_t);
-#else
static void cacheFlush(void* code, size_t size)
{
#if OS(LINUX) && COMPILER(GCC)
linuxPageFlush(current, end);
#elif OS(WINCE)
CacheRangeFlush(code, size, CACHE_SYNC_ALL);
-#elif OS(QNX) && ENABLE(ASSEMBLER_WX_EXCLUSIVE)
- UNUSED_PARAM(code);
- UNUSED_PARAM(size);
-#elif OS(QNX)
- msync(code, size, MS_INVALIDATE_ICACHE);
#else
#error "The cacheFlush support is missing on this platform."
#endif
}
-#endif
private:
static ARMWord RM(int reg)