/*
+ * Copyright (C) 2013 Cisco Systems, Inc. All rights reserved.
* Copyright (C) 2009-2011 STMicroelectronics. All rights reserved.
* Copyright (C) 2008 Apple Inc. All rights reserved.
*
#if ENABLE(ASSEMBLER) && CPU(SH4)
-#include "AbstractMacroAssembler.h"
#include "SH4Assembler.h"
+#include "AbstractMacroAssembler.h"
#include <wtf/Assertions.h>
namespace JSC {
typedef SH4Assembler::FPRegisterID FPRegisterID;
static const Scale ScalePtr = TimesFour;
- static const FPRegisterID fscratch = SH4Registers::fr10;
+ static const FPRegisterID fscratch = SH4Registers::dr10;
static const RegisterID stackPointerRegister = SH4Registers::sp;
+ static const RegisterID framePointerRegister = SH4Registers::fp;
static const RegisterID linkRegister = SH4Registers::pr;
static const RegisterID scratchReg3 = SH4Registers::r13;
- static const int MaximumCompactPtrAlignedAddressOffset = 0x7FFFFFFF;
+ static const int MaximumCompactPtrAlignedAddressOffset = 60;
+
+ static bool isCompactPtrAlignedAddressOffset(ptrdiff_t value)
+ {
+ return (value >= 0) && (value <= MaximumCompactPtrAlignedAddressOffset) && (!(value & 3));
+ }
enum RelationalCondition {
Equal = SH4Assembler::EQ,
enum ResultCondition {
Overflow = SH4Assembler::OF,
Signed = SH4Assembler::SI,
+ PositiveOrZero = SH4Assembler::NS,
Zero = SH4Assembler::EQ,
NonZero = SH4Assembler::NE
};
m_assembler.releaseScratch(reg);
}
+ static RelationalCondition invert(RelationalCondition cond)
+ {
+ switch (cond) {
+ case Equal:
+ return NotEqual;
+ case NotEqual:
+ return Equal;
+ case Above:
+ return BelowOrEqual;
+ case AboveOrEqual:
+ return Below;
+ case Below:
+ return AboveOrEqual;
+ case BelowOrEqual:
+ return Above;
+ case GreaterThan:
+ return LessThanOrEqual;
+ case GreaterThanOrEqual:
+ return LessThan;
+ case LessThan:
+ return GreaterThanOrEqual;
+ case LessThanOrEqual:
+ return GreaterThan;
+ default:
+ RELEASE_ASSERT_NOT_REACHED();
+ }
+ }
+
// Integer arithmetic operations
void add32(RegisterID src, RegisterID dest)
m_assembler.addlRegReg(src, dest);
}
+ void add32(RegisterID src1, RegisterID src2, RegisterID dest)
+ {
+ if (src1 == dest)
+ add32(src2, dest);
+ else {
+ move(src2, dest);
+ add32(src1, dest);
+ }
+ }
+
void add32(TrustedImm32 imm, RegisterID dest)
{
+ if (!imm.m_value)
+ return;
+
if (m_assembler.isImmediate(imm.m_value)) {
m_assembler.addlImm8r(imm.m_value, dest);
return;
void add32(TrustedImm32 imm, RegisterID src, RegisterID dest)
{
- if (src != dest)
- m_assembler.movlRegReg(src, dest);
+ move(src, dest);
add32(imm, dest);
}
void add32(TrustedImm32 imm, Address address)
{
+ if (!imm.m_value)
+ return;
+
RegisterID scr = claimScratch();
load32(address, scr);
add32(imm, scr);
releaseScratch(scr);
}
+ void add32(AbsoluteAddress src, RegisterID dest)
+ {
+ RegisterID scr = claimScratch();
+ load32(src.m_ptr, scr);
+ m_assembler.addlRegReg(scr, dest);
+ releaseScratch(scr);
+ }
+
void and32(RegisterID src, RegisterID dest)
{
m_assembler.andlRegReg(src, dest);
}
+ void and32(RegisterID src1, RegisterID src2, RegisterID dest)
+ {
+ if (src1 == dest)
+ and32(src2, dest);
+ else {
+ move(src2, dest);
+ and32(src1, dest);
+ }
+ }
+
+ void and32(Address src, RegisterID dest)
+ {
+ RegisterID scr = claimScratch();
+ load32(src, scr);
+ and32(scr, dest);
+ releaseScratch(scr);
+ }
+
void and32(TrustedImm32 imm, RegisterID dest)
{
+ if (!imm.m_value) {
+ m_assembler.movImm8(0, dest);
+ return;
+ }
+
if ((imm.m_value <= 255) && (imm.m_value >= 0) && (dest == SH4Registers::r0)) {
m_assembler.andlImm8r(imm.m_value, dest);
return;
}
RegisterID scr = claimScratch();
- m_assembler.loadConstant((imm.m_value), scr);
+ m_assembler.loadConstant(imm.m_value, scr);
m_assembler.andlRegReg(scr, dest);
releaseScratch(scr);
}
+ void and32(TrustedImm32 imm, RegisterID src, RegisterID dest)
+ {
+ if (src != dest) {
+ move(imm, dest);
+ and32(src, dest);
+ return;
+ }
+
+ and32(imm, dest);
+ }
+
void lshift32(RegisterID shiftamount, RegisterID dest)
{
- m_assembler.shllRegReg(dest, shiftamount);
+ RegisterID shiftTmp = claimScratch();
+ m_assembler.loadConstant(0x1f, shiftTmp);
+ m_assembler.andlRegReg(shiftamount, shiftTmp);
+ m_assembler.shldRegReg(dest, shiftTmp);
+ releaseScratch(shiftTmp);
}
- void rshift32(int imm, RegisterID dest)
+ void lshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
{
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(-imm, scr);
- m_assembler.shaRegReg(dest, scr);
- releaseScratch(scr);
+ move(src, dest);
+ lshift32(shiftAmount, dest);
}
void lshift32(TrustedImm32 imm, RegisterID dest)
{
- if ((imm.m_value == 1) || (imm.m_value == 2) || (imm.m_value == 8) || (imm.m_value == 16)) {
- m_assembler.shllImm8r(imm.m_value, dest);
+ int immMasked = imm.m_value & 0x1f;
+ if (!immMasked)
+ return;
+
+ if ((immMasked == 1) || (immMasked == 2) || (immMasked == 8) || (immMasked == 16)) {
+ m_assembler.shllImm8r(immMasked, dest);
return;
}
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(imm.m_value, scr);
- m_assembler.shllRegReg(dest, scr);
- releaseScratch(scr);
+ RegisterID shiftTmp = claimScratch();
+ m_assembler.loadConstant(immMasked, shiftTmp);
+ m_assembler.shldRegReg(dest, shiftTmp);
+ releaseScratch(shiftTmp);
+ }
+
+ void lshift32(RegisterID src, TrustedImm32 shiftamount, RegisterID dest)
+ {
+ move(src, dest);
+ lshift32(shiftamount, dest);
}
void mul32(RegisterID src, RegisterID dest)
{
- m_assembler.imullRegReg(src, dest);
- m_assembler.stsmacl(dest);
+ mul32(src, dest, dest);
}
- void mul32(TrustedImm32 imm, RegisterID src, RegisterID dest)
+ void mul32(RegisterID src1, RegisterID src2, RegisterID dest)
{
- RegisterID scr = claimScratch();
- move(imm, scr);
- if (src != dest)
- move(src, dest);
- mul32(scr, dest);
- releaseScratch(scr);
+ m_assembler.imullRegReg(src1, src2);
+ m_assembler.stsmacl(dest);
}
- void not32(RegisterID src, RegisterID dest)
+ void mul32(TrustedImm32 imm, RegisterID src, RegisterID dest)
{
- m_assembler.notlReg(src, dest);
+ if (src == dest) {
+ RegisterID immval = claimScratch();
+ move(imm, immval);
+ mul32(immval, dest);
+ releaseScratch(immval);
+ } else {
+ move(imm, dest);
+ mul32(src, dest);
+ }
}
void or32(RegisterID src, RegisterID dest)
releaseScratch(scr);
}
- void rshift32(RegisterID shiftamount, RegisterID dest)
+ void or32(RegisterID op1, RegisterID op2, RegisterID dest)
{
- compare32(32, shiftamount, Equal);
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 4);
- m_assembler.branch(BT_OPCODE, 1);
- m_assembler.neg(shiftamount, shiftamount);
- m_assembler.shaRegReg(dest, shiftamount);
+ if (op1 == op2)
+ move(op1, dest);
+ else if (op1 == dest)
+ or32(op2, dest);
+ else {
+ move(op2, dest);
+ or32(op1, dest);
+ }
}
- void rshift32(TrustedImm32 imm, RegisterID dest)
+ void or32(TrustedImm32 imm, RegisterID src, RegisterID dest)
{
- if (imm.m_value & 0x1f)
- rshift32(imm.m_value & 0x1f, dest);
+ if (src != dest) {
+ move(imm, dest);
+ or32(src, dest);
+ return;
+ }
+
+ or32(imm, dest);
}
- void sub32(RegisterID src, RegisterID dest)
+ void or32(RegisterID src, AbsoluteAddress address)
{
- m_assembler.sublRegReg(src, dest);
+ RegisterID destptr = claimScratch();
+ move(TrustedImmPtr(address.m_ptr), destptr);
+ RegisterID destval = claimScratch();
+ m_assembler.movlMemReg(destptr, destval);
+ m_assembler.orlRegReg(src, destval);
+ m_assembler.movlRegMem(destval, destptr);
+ releaseScratch(destval);
+ releaseScratch(destptr);
}
- void sub32(TrustedImm32 imm, AbsoluteAddress address, RegisterID scratchReg)
+ void xor32(TrustedImm32 imm, RegisterID src, RegisterID dest)
{
- RegisterID result = claimScratch();
+ if (src != dest) {
+ move(imm, dest);
+ xor32(src, dest);
+ return;
+ }
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(address.m_ptr), scratchReg);
- m_assembler.movlMemReg(scratchReg, result);
+ xor32(imm, dest);
+ }
- if (m_assembler.isImmediate(-imm.m_value))
- m_assembler.addlImm8r(-imm.m_value, result);
- else {
- m_assembler.loadConstant(imm.m_value, scratchReg3);
- m_assembler.sublRegReg(scratchReg3, result);
+ void rshift32(RegisterID shiftamount, RegisterID dest)
+ {
+ RegisterID shiftTmp = claimScratch();
+ m_assembler.loadConstant(0x1f, shiftTmp);
+ m_assembler.andlRegReg(shiftamount, shiftTmp);
+ m_assembler.neg(shiftTmp, shiftTmp);
+ m_assembler.shadRegReg(dest, shiftTmp);
+ releaseScratch(shiftTmp);
+ }
+
+ void rshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
+ {
+ move(src, dest);
+ rshift32(shiftAmount, dest);
+ }
+
+ void rshift32(TrustedImm32 imm, RegisterID dest)
+ {
+ int immMasked = imm.m_value & 0x1f;
+ if (!immMasked)
+ return;
+
+ if (immMasked == 1) {
+ m_assembler.sharImm8r(immMasked, dest);
+ return;
}
- store32(result, scratchReg);
- releaseScratch(result);
+ RegisterID shiftTmp = claimScratch();
+ m_assembler.loadConstant(-immMasked, shiftTmp);
+ m_assembler.shadRegReg(dest, shiftTmp);
+ releaseScratch(shiftTmp);
+ }
+
+ void rshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
+ {
+ move(src, dest);
+ rshift32(imm, dest);
+ }
+
+ void sub32(RegisterID src, RegisterID dest)
+ {
+ m_assembler.sublRegReg(src, dest);
}
void sub32(TrustedImm32 imm, AbsoluteAddress address)
{
+ if (!imm.m_value)
+ return;
+
RegisterID result = claimScratch();
RegisterID scratchReg = claimScratch();
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(address.m_ptr), scratchReg);
+ move(TrustedImmPtr(address.m_ptr), scratchReg);
m_assembler.movlMemReg(scratchReg, result);
if (m_assembler.isImmediate(-imm.m_value))
releaseScratch(scratchReg);
}
- void add32(TrustedImm32 imm, AbsoluteAddress address, RegisterID scratchReg)
+ void sub32(TrustedImm32 imm, Address address)
{
- RegisterID result = claimScratch();
-
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(address.m_ptr), scratchReg);
- m_assembler.movlMemReg(scratchReg, result);
-
- if (m_assembler.isImmediate(imm.m_value))
- m_assembler.addlImm8r(imm.m_value, result);
- else {
- m_assembler.loadConstant(imm.m_value, scratchReg3);
- m_assembler.addlRegReg(scratchReg3, result);
- }
-
- store32(result, scratchReg);
- releaseScratch(result);
+ add32(TrustedImm32(-imm.m_value), address);
}
void add32(TrustedImm32 imm, AbsoluteAddress address)
{
+ if (!imm.m_value)
+ return;
+
RegisterID result = claimScratch();
RegisterID scratchReg = claimScratch();
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(address.m_ptr), scratchReg);
+ move(TrustedImmPtr(address.m_ptr), scratchReg);
m_assembler.movlMemReg(scratchReg, result);
if (m_assembler.isImmediate(imm.m_value))
releaseScratch(scratchReg);
}
+ void add64(TrustedImm32 imm, AbsoluteAddress address)
+ {
+ RegisterID scr1 = claimScratch();
+ RegisterID scr2 = claimScratch();
+
+ // Add 32-bit LSB first.
+ move(TrustedImmPtr(address.m_ptr), scratchReg3);
+ m_assembler.movlMemReg(scratchReg3, scr1); // scr1 = 32-bit LSB of int64 @ address
+ m_assembler.loadConstant(imm.m_value, scr2);
+ m_assembler.clrt();
+ m_assembler.addclRegReg(scr1, scr2);
+ m_assembler.movlRegMem(scr2, scratchReg3); // Update address with 32-bit LSB result.
+
+ // Then add 32-bit MSB.
+ m_assembler.addlImm8r(4, scratchReg3);
+ m_assembler.movlMemReg(scratchReg3, scr1); // scr1 = 32-bit MSB of int64 @ address
+ m_assembler.movt(scr2);
+ if (imm.m_value < 0)
+ m_assembler.addlImm8r(-1, scr2); // Sign extend imm value if needed.
+ m_assembler.addvlRegReg(scr2, scr1);
+ m_assembler.movlRegMem(scr1, scratchReg3); // Update (address + 4) with 32-bit MSB result.
+
+ releaseScratch(scr2);
+ releaseScratch(scr1);
+ }
+
void sub32(TrustedImm32 imm, RegisterID dest)
{
+ if (!imm.m_value)
+ return;
+
if (m_assembler.isImmediate(-imm.m_value)) {
m_assembler.addlImm8r(-imm.m_value, dest);
return;
m_assembler.xorlRegReg(src, dest);
}
+ void xor32(RegisterID src1, RegisterID src2, RegisterID dest)
+ {
+ if (src1 == dest)
+ xor32(src2, dest);
+ else {
+ move(src2, dest);
+ xor32(src1, dest);
+ }
+ }
+
void xor32(TrustedImm32 imm, RegisterID srcDest)
{
+ if (imm.m_value == -1) {
+ m_assembler.notlReg(srcDest, srcDest);
+ return;
+ }
+
if ((srcDest != SH4Registers::r0) || (imm.m_value > 255) || (imm.m_value < 0)) {
RegisterID scr = claimScratch();
- m_assembler.loadConstant((imm.m_value), scr);
+ m_assembler.loadConstant(imm.m_value, scr);
m_assembler.xorlRegReg(scr, srcDest);
releaseScratch(scr);
return;
return;
}
+ if (((cond == Equal) || (cond == NotEqual)) && !imm) {
+ m_assembler.testlRegReg(dst, dst);
+ return;
+ }
+
RegisterID scr = claimScratch();
m_assembler.loadConstant(imm, scr);
m_assembler.cmplRegReg(scr, dst, SH4Condition(cond));
void testImm(int imm, int offset, RegisterID base)
{
RegisterID scr = claimScratch();
- RegisterID scr1 = claimScratch();
+ load32(base, offset, scr);
- if ((offset < 0) || (offset >= 64)) {
- m_assembler.loadConstant(offset, scr);
- m_assembler.addlRegReg(base, scr);
- m_assembler.movlMemReg(scr, scr);
- } else if (offset)
- m_assembler.movlMemReg(offset >> 2, base, scr);
- else
- m_assembler.movlMemReg(base, scr);
- if (m_assembler.isImmediate(imm))
- m_assembler.movImm8(imm, scr1);
- else
- m_assembler.loadConstant(imm, scr1);
+ RegisterID scr1 = claimScratch();
+ move(TrustedImm32(imm), scr1);
m_assembler.testlRegReg(scr, scr1);
releaseScratch(scr);
void compare32(int imm, int offset, RegisterID base, RelationalCondition cond)
{
- if (!offset) {
- RegisterID scr = claimScratch();
- RegisterID scr1 = claimScratch();
- m_assembler.movlMemReg(base, scr);
- m_assembler.loadConstant(imm, scr1);
- m_assembler.cmplRegReg(scr1, scr, SH4Condition(cond));
- releaseScratch(scr1);
- releaseScratch(scr);
- return;
- }
-
- if ((offset < 0) || (offset >= 64)) {
- RegisterID scr = claimScratch();
- RegisterID scr1 = claimScratch();
- m_assembler.loadConstant(offset, scr);
- m_assembler.addlRegReg(base, scr);
- m_assembler.movlMemReg(scr, scr);
- m_assembler.loadConstant(imm, scr1);
- m_assembler.cmplRegReg(scr1, scr, SH4Condition(cond));
- releaseScratch(scr1);
- releaseScratch(scr);
- return;
- }
-
RegisterID scr = claimScratch();
+ load32(base, offset, scr);
+
RegisterID scr1 = claimScratch();
- m_assembler.movlMemReg(offset >> 2, base, scr);
- m_assembler.loadConstant(imm, scr1);
+ move(TrustedImm32(imm), scr1);
+
m_assembler.cmplRegReg(scr1, scr, SH4Condition(cond));
+
releaseScratch(scr1);
releaseScratch(scr);
}
// Memory access operation
+ ALWAYS_INLINE void loadEffectiveAddress(BaseIndex address, RegisterID dest, int extraoffset = 0)
+ {
+ if (dest == address.base) {
+ RegisterID scaledIndex = claimScratch();
+ move(address.index, scaledIndex);
+ lshift32(TrustedImm32(address.scale), scaledIndex);
+ add32(scaledIndex, dest);
+ releaseScratch(scaledIndex);
+ } else {
+ move(address.index, dest);
+ lshift32(TrustedImm32(address.scale), dest);
+ add32(address.base, dest);
+ }
+
+ add32(TrustedImm32(address.offset + extraoffset), dest);
+ }
+
void load32(ImplicitAddress address, RegisterID dest)
{
load32(address.base, address.offset, dest);
load8(address.base, address.offset, dest);
}
+ void load8(BaseIndex address, RegisterID dest)
+ {
+ RegisterID scr = claimScratch();
+ move(address.index, scr);
+ lshift32(TrustedImm32(address.scale), scr);
+ add32(address.base, scr);
+ load8(scr, address.offset, dest);
+ releaseScratch(scr);
+ }
+
+ void load8(AbsoluteAddress address, RegisterID dest)
+ {
+ move(TrustedImmPtr(address.m_ptr), dest);
+ m_assembler.movbMemReg(dest, dest);
+ m_assembler.extub(dest, dest);
+ }
+
+ void load8(const void* address, RegisterID dest)
+ {
+ load8(AbsoluteAddress(address), dest);
+ }
+
+ void load8PostInc(RegisterID base, RegisterID dest)
+ {
+ m_assembler.movbMemRegIn(base, dest);
+ m_assembler.extub(dest, dest);
+ }
+
+ void load8Signed(BaseIndex address, RegisterID dest)
+ {
+ RegisterID scr = claimScratch();
+ move(address.index, scr);
+ lshift32(TrustedImm32(address.scale), scr);
+ add32(address.base, scr);
+ load8Signed(scr, address.offset, dest);
+ releaseScratch(scr);
+ }
+
void load32(BaseIndex address, RegisterID dest)
{
RegisterID scr = claimScratch();
releaseScratch(scr);
}
- void load32(void* address, RegisterID dest)
+ void load32(const void* address, RegisterID dest)
{
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(address), dest);
+ move(TrustedImmPtr(address), dest);
m_assembler.movlMemReg(dest, dest);
}
return;
}
- if ((dest == SH4Registers::r0) && (dest != base)) {
- m_assembler.loadConstant((offset), dest);
- m_assembler.movlR0mr(base, dest);
- return;
- }
+ RegisterID scr = (dest == base) ? claimScratch() : dest;
- RegisterID scr;
- if (dest == base)
- scr = claimScratch();
- else
- scr = dest;
- m_assembler.loadConstant((offset), scr);
- m_assembler.addlRegReg(base, scr);
- m_assembler.movlMemReg(scr, dest);
+ m_assembler.loadConstant(offset, scr);
+ if (base == SH4Registers::r0)
+ m_assembler.movlR0mr(scr, dest);
+ else {
+ m_assembler.addlRegReg(base, scr);
+ m_assembler.movlMemReg(scr, dest);
+ }
if (dest == base)
releaseScratch(scr);
}
- void load8(RegisterID base, int offset, RegisterID dest)
+ void load8Signed(RegisterID base, int offset, RegisterID dest)
{
if (!offset) {
m_assembler.movbMemReg(base, dest);
return;
}
- if ((offset > 0) && (offset < 64) && (dest == SH4Registers::r0)) {
+ if ((offset > 0) && (offset <= 15) && (dest == SH4Registers::r0)) {
m_assembler.movbMemReg(offset, base, dest);
return;
}
- if (base != dest) {
- m_assembler.loadConstant((offset), dest);
- m_assembler.addlRegReg(base, dest);
- m_assembler.movbMemReg(dest, dest);
- return;
+ RegisterID scr = (dest == base) ? claimScratch() : dest;
+
+ m_assembler.loadConstant(offset, scr);
+ if (base == SH4Registers::r0)
+ m_assembler.movbR0mr(scr, dest);
+ else {
+ m_assembler.addlRegReg(base, scr);
+ m_assembler.movbMemReg(scr, dest);
}
- RegisterID scr = claimScratch();
- m_assembler.loadConstant((offset), scr);
- m_assembler.addlRegReg(base, scr);
- m_assembler.movbMemReg(scr, dest);
- releaseScratch(scr);
+ if (dest == base)
+ releaseScratch(scr);
}
- void load32(RegisterID r0, RegisterID src, RegisterID dst)
+ void load8(RegisterID base, int offset, RegisterID dest)
{
- ASSERT(r0 == SH4Registers::r0);
- m_assembler.movlR0mr(src, dst);
+ load8Signed(base, offset, dest);
+ m_assembler.extub(dest, dest);
}
void load32(RegisterID src, RegisterID dst)
{
if (!address.offset) {
m_assembler.movwMemReg(address.base, dest);
+ m_assembler.extuw(dest, dest);
return;
}
- if ((address.offset > 0) && (address.offset < 64) && (dest == SH4Registers::r0)) {
- m_assembler.movwMemReg(address.offset, address.base, dest);
+ if ((address.offset > 0) && (address.offset <= 30) && (dest == SH4Registers::r0)) {
+ m_assembler.movwMemReg(address.offset >> 1, address.base, dest);
+ m_assembler.extuw(dest, dest);
return;
}
- if (address.base != dest) {
- m_assembler.loadConstant((address.offset), dest);
- m_assembler.addlRegReg(address.base, dest);
- m_assembler.movwMemReg(dest, dest);
- return;
+ RegisterID scr = (dest == address.base) ? claimScratch() : dest;
+
+ m_assembler.loadConstant(address.offset, scr);
+ if (address.base == SH4Registers::r0)
+ m_assembler.movwR0mr(scr, dest);
+ else {
+ m_assembler.addlRegReg(address.base, scr);
+ m_assembler.movwMemReg(scr, dest);
}
+ m_assembler.extuw(dest, dest);
+ if (dest == address.base)
+ releaseScratch(scr);
+ }
+
+ void load16Unaligned(BaseIndex address, RegisterID dest)
+ {
RegisterID scr = claimScratch();
- m_assembler.loadConstant((address.offset), scr);
- m_assembler.addlRegReg(address.base, scr);
- m_assembler.movwMemReg(scr, dest);
+
+ loadEffectiveAddress(address, scr);
+
+ RegisterID scr1 = claimScratch();
+ load8PostInc(scr, scr1);
+ load8(scr, dest);
+ m_assembler.shllImm8r(8, dest);
+ or32(scr1, dest);
+
releaseScratch(scr);
+ releaseScratch(scr1);
}
void load16(RegisterID src, RegisterID dest)
{
m_assembler.movwMemReg(src, dest);
+ m_assembler.extuw(dest, dest);
}
- void load16(RegisterID r0, RegisterID src, RegisterID dest)
+ void load16Signed(RegisterID src, RegisterID dest)
{
- ASSERT(r0 == SH4Registers::r0);
- m_assembler.movwR0mr(src, dest);
+ m_assembler.movwMemReg(src, dest);
}
void load16(BaseIndex address, RegisterID dest)
+ {
+ load16Signed(address, dest);
+ m_assembler.extuw(dest, dest);
+ }
+
+ void load16PostInc(RegisterID base, RegisterID dest)
+ {
+ m_assembler.movwMemRegIn(base, dest);
+ m_assembler.extuw(dest, dest);
+ }
+
+ void load16Signed(BaseIndex address, RegisterID dest)
{
RegisterID scr = claimScratch();
move(address.index, scr);
lshift32(TrustedImm32(address.scale), scr);
+ add32(TrustedImm32(address.offset), scr);
- if (address.offset)
- add32(TrustedImm32(address.offset), scr);
- if (scr == SH4Registers::r0)
- m_assembler.movwR0mr(address.base, scr);
+ if (address.base == SH4Registers::r0)
+ m_assembler.movwR0mr(scr, dest);
else {
add32(address.base, scr);
- load16(scr, scr);
+ load16Signed(scr, dest);
}
- extuw(scr, dest);
releaseScratch(scr);
}
- void store32(RegisterID src, ImplicitAddress address)
+ void store8(RegisterID src, BaseIndex address)
{
RegisterID scr = claimScratch();
- store32(src, address.offset, address.base, scr);
+
+ move(address.index, scr);
+ lshift32(TrustedImm32(address.scale), scr);
+ add32(TrustedImm32(address.offset), scr);
+
+ if (address.base == SH4Registers::r0)
+ m_assembler.movbRegMemr0(src, scr);
+ else {
+ add32(address.base, scr);
+ m_assembler.movbRegMem(src, scr);
+ }
+
releaseScratch(scr);
}
- void store32(RegisterID src, int offset, RegisterID base, RegisterID scr)
+ void store8(RegisterID src, void* address)
{
- if (!offset) {
- m_assembler.movlRegMem(src, base);
- return;
+ RegisterID destptr = claimScratch();
+ move(TrustedImmPtr(address), destptr);
+ m_assembler.movbRegMem(src, destptr);
+ releaseScratch(destptr);
+ }
+
+ void store8(TrustedImm32 imm, void* address)
+ {
+ ASSERT((imm.m_value >= -128) && (imm.m_value <= 127));
+ RegisterID dstptr = claimScratch();
+ move(TrustedImmPtr(address), dstptr);
+ RegisterID srcval = claimScratch();
+ move(imm, srcval);
+ m_assembler.movbRegMem(srcval, dstptr);
+ releaseScratch(dstptr);
+ releaseScratch(srcval);
+ }
+
+ void store16(RegisterID src, BaseIndex address)
+ {
+ RegisterID scr = claimScratch();
+
+ move(address.index, scr);
+ lshift32(TrustedImm32(address.scale), scr);
+ add32(TrustedImm32(address.offset), scr);
+
+ if (address.base == SH4Registers::r0)
+ m_assembler.movwRegMemr0(src, scr);
+ else {
+ add32(address.base, scr);
+ m_assembler.movwRegMem(src, scr);
}
- if ((offset >=0) && (offset < 64)) {
- m_assembler.movlRegMem(src, offset >> 2, base);
+ releaseScratch(scr);
+ }
+
+ void store32(RegisterID src, ImplicitAddress address)
+ {
+ if (!address.offset) {
+ m_assembler.movlRegMem(src, address.base);
return;
}
- m_assembler.loadConstant((offset), scr);
- if (scr == SH4Registers::r0) {
- m_assembler.movlRegMemr0(src, base);
+ if ((address.offset >= 0) && (address.offset < 64)) {
+ m_assembler.movlRegMem(src, address.offset >> 2, address.base);
return;
}
- m_assembler.addlRegReg(base, scr);
- m_assembler.movlRegMem(src, scr);
- }
-
- void store32(RegisterID src, RegisterID offset, RegisterID base)
- {
- ASSERT(offset == SH4Registers::r0);
- m_assembler.movlRegMemr0(src, base);
+ RegisterID scr = claimScratch();
+ m_assembler.loadConstant(address.offset, scr);
+ if (address.base == SH4Registers::r0)
+ m_assembler.movlRegMemr0(src, scr);
+ else {
+ m_assembler.addlRegReg(address.base, scr);
+ m_assembler.movlRegMem(src, scr);
+ }
+ releaseScratch(scr);
}
void store32(RegisterID src, RegisterID dst)
void store32(TrustedImm32 imm, ImplicitAddress address)
{
RegisterID scr = claimScratch();
- RegisterID scr1 = claimScratch();
- m_assembler.loadConstant((imm.m_value), scr);
- store32(scr, address.offset, address.base, scr1);
+ m_assembler.loadConstant(imm.m_value, scr);
+ store32(scr, address);
releaseScratch(scr);
- releaseScratch(scr1);
}
void store32(RegisterID src, BaseIndex address)
{
RegisterID scr = claimScratch();
RegisterID scr1 = claimScratch();
- m_assembler.loadConstant((imm.m_value), scr);
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(address), scr1);
- m_assembler.movlMemReg(scr, scr1);
+ m_assembler.loadConstant(imm.m_value, scr);
+ move(TrustedImmPtr(address), scr1);
+ m_assembler.movlRegMem(scr, scr1);
releaseScratch(scr);
releaseScratch(scr1);
}
void store32(RegisterID src, void* address)
{
RegisterID scr = claimScratch();
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(address), scr);
- m_assembler.movlMemReg(src, scr);
+ move(TrustedImmPtr(address), scr);
+ m_assembler.movlRegMem(src, scr);
releaseScratch(scr);
}
+ void store32(TrustedImm32 imm, BaseIndex address)
+ {
+ RegisterID destptr = claimScratch();
+
+ loadEffectiveAddress(address, destptr);
+
+ RegisterID srcval = claimScratch();
+ move(imm, srcval);
+ m_assembler.movlRegMem(srcval, destptr);
+ releaseScratch(srcval);
+ releaseScratch(destptr);
+ }
+
DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest)
{
RegisterID scr = claimScratch();
return label;
}
- DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest)
+ DataLabel32 store32WithAddressOffsetPatch(RegisterID src, Address address)
{
RegisterID scr = claimScratch();
- DataLabelCompact label(this);
+ DataLabel32 label(this);
m_assembler.loadConstantUnReusable(address.offset, scr);
m_assembler.addlRegReg(address.base, scr);
- m_assembler.movlMemReg(scr, dest);
+ m_assembler.movlRegMem(src, scr);
releaseScratch(scr);
return label;
}
- DataLabel32 store32WithAddressOffsetPatch(RegisterID src, Address address)
+ DataLabelCompact load32WithCompactAddressOffsetPatch(Address address, RegisterID dest)
+ {
+ DataLabelCompact dataLabel(this);
+ ASSERT(isCompactPtrAlignedAddressOffset(address.offset));
+ m_assembler.movlMemRegCompact(address.offset >> 2, address.base, dest);
+ return dataLabel;
+ }
+
+ ConvertibleLoadLabel convertibleLoadPtr(Address address, RegisterID dest)
{
+ ConvertibleLoadLabel result(this);
+
RegisterID scr = claimScratch();
- DataLabel32 label(this);
- m_assembler.loadConstantUnReusable(address.offset, scr);
+ m_assembler.movImm8(address.offset, scr);
m_assembler.addlRegReg(address.base, scr);
- m_assembler.movlRegMem(src, scr);
+ m_assembler.movlMemReg(scr, dest);
releaseScratch(scr);
- return label;
+
+ return result;
+ }
+
+ // Floating-point operations
+
+ static bool supportsFloatingPoint() { return true; }
+ static bool supportsFloatingPointTruncate() { return true; }
+ static bool supportsFloatingPointSqrt() { return true; }
+ static bool supportsFloatingPointAbs() { return true; }
+
+ void moveDoubleToInts(FPRegisterID src, RegisterID dest1, RegisterID dest2)
+ {
+ m_assembler.fldsfpul((FPRegisterID)(src + 1));
+ m_assembler.stsfpulReg(dest1);
+ m_assembler.fldsfpul(src);
+ m_assembler.stsfpulReg(dest2);
+ }
+
+ void moveIntsToDouble(RegisterID src1, RegisterID src2, FPRegisterID dest, FPRegisterID)
+ {
+ m_assembler.ldsrmfpul(src1);
+ m_assembler.fstsfpul((FPRegisterID)(dest + 1));
+ m_assembler.ldsrmfpul(src2);
+ m_assembler.fstsfpul(dest);
}
- // Floating-point operations
+ void moveDouble(FPRegisterID src, FPRegisterID dest)
+ {
+ if (src != dest) {
+ m_assembler.fmovsRegReg((FPRegisterID)(src + 1), (FPRegisterID)(dest + 1));
+ m_assembler.fmovsRegReg(src, dest);
+ }
+ }
+
+ void swapDouble(FPRegisterID fr1, FPRegisterID fr2)
+ {
+ if (fr1 != fr2) {
+ m_assembler.fldsfpul((FPRegisterID)(fr1 + 1));
+ m_assembler.fmovsRegReg((FPRegisterID)(fr2 + 1), (FPRegisterID)(fr1 + 1));
+ m_assembler.fstsfpul((FPRegisterID)(fr2 + 1));
+ m_assembler.fldsfpul(fr1);
+ m_assembler.fmovsRegReg(fr2, fr1);
+ m_assembler.fstsfpul(fr2);
+ }
+ }
+
+ void loadFloat(BaseIndex address, FPRegisterID dest)
+ {
+ RegisterID scr = claimScratch();
- bool supportsFloatingPoint() const { return true; }
- bool supportsFloatingPointTruncate() const { return true; }
- bool supportsFloatingPointSqrt() const { return true; }
+ loadEffectiveAddress(address, scr);
+
+ m_assembler.fmovsReadrm(scr, dest);
+ releaseScratch(scr);
+ }
+
+ void loadDouble(BaseIndex address, FPRegisterID dest)
+ {
+ RegisterID scr = claimScratch();
+
+ loadEffectiveAddress(address, scr);
+
+ m_assembler.fmovsReadrminc(scr, (FPRegisterID)(dest + 1));
+ m_assembler.fmovsReadrm(scr, dest);
+ releaseScratch(scr);
+ }
void loadDouble(ImplicitAddress address, FPRegisterID dest)
{
releaseScratch(scr);
}
- void loadDouble(const void* address, FPRegisterID dest)
+ void loadDouble(TrustedImmPtr address, FPRegisterID dest)
{
RegisterID scr = claimScratch();
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(address), scr);
+ move(address, scr);
m_assembler.fmovsReadrminc(scr, (FPRegisterID)(dest + 1));
m_assembler.fmovsReadrm(scr, dest);
releaseScratch(scr);
}
+ void storeFloat(FPRegisterID src, BaseIndex address)
+ {
+ RegisterID scr = claimScratch();
+ loadEffectiveAddress(address, scr);
+ m_assembler.fmovsWriterm(src, scr);
+ releaseScratch(scr);
+ }
+
void storeDouble(FPRegisterID src, ImplicitAddress address)
{
RegisterID scr = claimScratch();
- m_assembler.loadConstant(address.offset, scr);
+ m_assembler.loadConstant(address.offset + 8, scr);
m_assembler.addlRegReg(address.base, scr);
- m_assembler.fmovsWriterm((FPRegisterID)(src + 1), scr);
- m_assembler.addlImm8r(4, scr);
- m_assembler.fmovsWriterm(src, scr);
+ m_assembler.fmovsWriterndec(src, scr);
+ m_assembler.fmovsWriterndec((FPRegisterID)(src + 1), scr);
+ releaseScratch(scr);
+ }
+
+ void storeDouble(FPRegisterID src, BaseIndex address)
+ {
+ RegisterID scr = claimScratch();
+
+ loadEffectiveAddress(address, scr, 8);
+
+ m_assembler.fmovsWriterndec(src, scr);
+ m_assembler.fmovsWriterndec((FPRegisterID)(src + 1), scr);
+
+ releaseScratch(scr);
+ }
+
+ void addDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+ {
+ if (op1 == dest)
+ addDouble(op2, dest);
+ else {
+ moveDouble(op2, dest);
+ addDouble(op1, dest);
+ }
+ }
+
+ void storeDouble(FPRegisterID src, TrustedImmPtr address)
+ {
+ RegisterID scr = claimScratch();
+ m_assembler.loadConstant(reinterpret_cast<uint32_t>(const_cast<void*>(address.m_value)) + 8, scr);
+ m_assembler.fmovsWriterndec(src, scr);
+ m_assembler.fmovsWriterndec((FPRegisterID)(src + 1), scr);
releaseScratch(scr);
}
m_assembler.daddRegReg(src, dest);
}
+ void addDouble(AbsoluteAddress address, FPRegisterID dest)
+ {
+ loadDouble(TrustedImmPtr(address.m_ptr), fscratch);
+ addDouble(fscratch, dest);
+ }
+
void addDouble(Address address, FPRegisterID dest)
{
loadDouble(address, fscratch);
m_assembler.dsubRegReg(src, dest);
}
+ void subDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+ {
+ if (op2 == dest) {
+ moveDouble(op1, fscratch);
+ subDouble(op2, fscratch);
+ moveDouble(fscratch, dest);
+ } else {
+ moveDouble(op1, dest);
+ subDouble(op2, dest);
+ }
+ }
+
void subDouble(Address address, FPRegisterID dest)
{
loadDouble(address, fscratch);
m_assembler.dmulRegReg(src, dest);
}
+ void mulDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+ {
+ if (op1 == dest)
+ mulDouble(op2, dest);
+ else {
+ moveDouble(op2, dest);
+ mulDouble(op1, dest);
+ }
+ }
+
void mulDouble(Address address, FPRegisterID dest)
{
loadDouble(address, fscratch);
m_assembler.ddivRegReg(src, dest);
}
+ void divDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+ {
+ if (op2 == dest) {
+ moveDouble(op1, fscratch);
+ divDouble(op2, fscratch);
+ moveDouble(fscratch, dest);
+ } else {
+ moveDouble(op1, dest);
+ divDouble(op2, dest);
+ }
+ }
+
+ void negateDouble(FPRegisterID src, FPRegisterID dest)
+ {
+ moveDouble(src, dest);
+ m_assembler.dneg(dest);
+ }
+
+ void convertFloatToDouble(FPRegisterID src, FPRegisterID dst)
+ {
+ m_assembler.fldsfpul(src);
+ m_assembler.dcnvsd(dst);
+ }
+
+ void convertDoubleToFloat(FPRegisterID src, FPRegisterID dst)
+ {
+ m_assembler.dcnvds(src);
+ m_assembler.fstsfpul(dst);
+ }
+
void convertInt32ToDouble(RegisterID src, FPRegisterID dest)
{
m_assembler.ldsrmfpul(src);
void convertInt32ToDouble(AbsoluteAddress src, FPRegisterID dest)
{
RegisterID scr = claimScratch();
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(src.m_ptr), scr);
+ load32(src.m_ptr, scr);
convertInt32ToDouble(scr, dest);
releaseScratch(scr);
}
void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest)
{
RegisterID scr = claimScratch();
+ Jump m_jump;
+ JumpList end;
- move(address.index, scr);
- lshift32(TrustedImm32(address.scale), scr);
- add32(address.base, scr);
-
- if (address.offset)
- add32(TrustedImm32(address.offset), scr);
+ loadEffectiveAddress(address, scr);
RegisterID scr1 = claimScratch();
- load16(scr, scr1);
- add32(TrustedImm32(2), scr);
+ if (dest != SH4Registers::r0)
+ move(SH4Registers::r0, scr1);
+
+ m_assembler.ensureSpace(m_assembler.maxInstructionSize + 58, sizeof(uint32_t));
+ move(scr, SH4Registers::r0);
+ m_assembler.testlImm8r(0x3, SH4Registers::r0);
+ m_jump = Jump(m_assembler.jne(), SH4Assembler::JumpNear);
+
+ if (dest != SH4Registers::r0)
+ move(scr1, SH4Registers::r0);
+
+ load32(scr, dest);
+ end.append(Jump(m_assembler.bra(), SH4Assembler::JumpNear));
+ m_assembler.nop();
+ m_jump.link(this);
+ m_assembler.testlImm8r(0x1, SH4Registers::r0);
+
+ if (dest != SH4Registers::r0)
+ move(scr1, SH4Registers::r0);
+
+ m_jump = Jump(m_assembler.jne(), SH4Assembler::JumpNear);
+ load16PostInc(scr, scr1);
load16(scr, dest);
- move(TrustedImm32(16), scr);
- m_assembler.shllRegReg(dest, scr);
+ m_assembler.shllImm8r(16, dest);
+ or32(scr1, dest);
+ end.append(Jump(m_assembler.bra(), SH4Assembler::JumpNear));
+ m_assembler.nop();
+ m_jump.link(this);
+ load8PostInc(scr, scr1);
+ load16PostInc(scr, dest);
+ m_assembler.shllImm8r(8, dest);
+ or32(dest, scr1);
+ load8(scr, dest);
+ m_assembler.shllImm8r(8, dest);
+ m_assembler.shllImm8r(16, dest);
or32(scr1, dest);
+ end.link(this);
releaseScratch(scr);
releaseScratch(scr1);
}
if (cond == DoubleNotEqual) {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(0x7fbfffff, scratchReg3);
- m_assembler.dcnvds(right);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
+ JumpList end;
+ m_assembler.dcmppeq(left, left);
m_assembler.ensureSpace(m_assembler.maxInstructionSize + 22, sizeof(uint32_t));
- m_assembler.branch(BT_OPCODE, 8);
- m_assembler.dcnvds(left);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- m_assembler.branch(BT_OPCODE, 4);
+ end.append(Jump(m_assembler.jne(), SH4Assembler::JumpNear));
+ m_assembler.dcmppeq(right, right);
+ end.append(Jump(m_assembler.jne(), SH4Assembler::JumpNear));
m_assembler.dcmppeq(right, left);
- releaseScratch(scr);
- return branchFalse();
+ Jump m_jump = branchFalse();
+ end.link(this);
+ return m_jump;
}
if (cond == DoubleGreaterThan) {
}
if (cond == DoubleGreaterThanOrEqual) {
+ JumpList end;
+ m_assembler.dcmppeq(left, left);
+ m_assembler.ensureSpace(m_assembler.maxInstructionSize + 22, sizeof(uint32_t));
+ end.append(Jump(m_assembler.jne(), SH4Assembler::JumpNear));
+ m_assembler.dcmppeq(right, right);
+ end.append(Jump(m_assembler.jne(), SH4Assembler::JumpNear));
m_assembler.dcmppgt(left, right);
- return branchFalse();
+ Jump m_jump = branchFalse();
+ end.link(this);
+ return m_jump;
}
if (cond == DoubleLessThan) {
}
if (cond == DoubleLessThanOrEqual) {
+ JumpList end;
+ m_assembler.dcmppeq(left, left);
+ m_assembler.ensureSpace(m_assembler.maxInstructionSize + 22, sizeof(uint32_t));
+ end.append(Jump(m_assembler.jne(), SH4Assembler::JumpNear));
+ m_assembler.dcmppeq(right, right);
+ end.append(Jump(m_assembler.jne(), SH4Assembler::JumpNear));
m_assembler.dcmppgt(right, left);
- return branchFalse();
+ Jump m_jump = branchFalse();
+ end.link(this);
+ return m_jump;
}
if (cond == DoubleEqualOrUnordered) {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(0x7fbfffff, scratchReg3);
- m_assembler.dcnvds(right);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
+ JumpList takeBranch;
+ m_assembler.dcmppeq(left, left);
m_assembler.ensureSpace(m_assembler.maxInstructionSize + 22, sizeof(uint32_t));
- m_assembler.branch(BT_OPCODE, 5);
- m_assembler.dcnvds(left);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- m_assembler.branch(BT_OPCODE, 1);
+ takeBranch.append(Jump(m_assembler.jne(), SH4Assembler::JumpNear));
+ m_assembler.dcmppeq(right, right);
+ takeBranch.append(Jump(m_assembler.jne(), SH4Assembler::JumpNear));
m_assembler.dcmppeq(left, right);
- releaseScratch(scr);
- return branchTrue();
+ m_assembler.branch(BF_OPCODE, 2);
+ takeBranch.link(this);
+ return Jump(m_assembler.extraInstrForBranch(scratchReg3));
}
if (cond == DoubleGreaterThanOrUnordered) {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(0x7fbfffff, scratchReg3);
- m_assembler.dcnvds(right);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
+ JumpList takeBranch;
+ m_assembler.dcmppeq(left, left);
m_assembler.ensureSpace(m_assembler.maxInstructionSize + 22, sizeof(uint32_t));
- m_assembler.branch(BT_OPCODE, 5);
- m_assembler.dcnvds(left);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- m_assembler.branch(BT_OPCODE, 1);
+ takeBranch.append(Jump(m_assembler.jne(), SH4Assembler::JumpNear));
+ m_assembler.dcmppeq(right, right);
+ takeBranch.append(Jump(m_assembler.jne(), SH4Assembler::JumpNear));
m_assembler.dcmppgt(right, left);
- releaseScratch(scr);
- return branchTrue();
+ m_assembler.branch(BF_OPCODE, 2);
+ takeBranch.link(this);
+ return Jump(m_assembler.extraInstrForBranch(scratchReg3));
}
if (cond == DoubleGreaterThanOrEqualOrUnordered) {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(0x7fbfffff, scratchReg3);
- m_assembler.dcnvds(right);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 22, sizeof(uint32_t));
- m_assembler.branch(BT_OPCODE, 5);
- m_assembler.dcnvds(left);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- m_assembler.branch(BT_OPCODE, 1);
m_assembler.dcmppgt(left, right);
- releaseScratch(scr);
return branchFalse();
}
if (cond == DoubleLessThanOrUnordered) {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(0x7fbfffff, scratchReg3);
- m_assembler.dcnvds(right);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
+ JumpList takeBranch;
+ m_assembler.dcmppeq(left, left);
m_assembler.ensureSpace(m_assembler.maxInstructionSize + 22, sizeof(uint32_t));
- m_assembler.branch(BT_OPCODE, 5);
- m_assembler.dcnvds(left);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- m_assembler.branch(BT_OPCODE, 1);
+ takeBranch.append(Jump(m_assembler.jne(), SH4Assembler::JumpNear));
+ m_assembler.dcmppeq(right, right);
+ takeBranch.append(Jump(m_assembler.jne(), SH4Assembler::JumpNear));
m_assembler.dcmppgt(left, right);
- releaseScratch(scr);
- return branchTrue();
+ m_assembler.branch(BF_OPCODE, 2);
+ takeBranch.link(this);
+ return Jump(m_assembler.extraInstrForBranch(scratchReg3));
}
if (cond == DoubleLessThanOrEqualOrUnordered) {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(0x7fbfffff, scratchReg3);
- m_assembler.dcnvds(right);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 22, sizeof(uint32_t));
- m_assembler.branch(BT_OPCODE, 5);
- m_assembler.dcnvds(left);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- m_assembler.branch(BT_OPCODE, 1);
m_assembler.dcmppgt(right, left);
- releaseScratch(scr);
return branchFalse();
}
ASSERT(cond == DoubleNotEqualOrUnordered);
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(0x7fbfffff, scratchReg3);
- m_assembler.dcnvds(right);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 22, sizeof(uint32_t));
- m_assembler.branch(BT_OPCODE, 5);
- m_assembler.dcnvds(left);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- m_assembler.branch(BT_OPCODE, 1);
m_assembler.dcmppeq(right, left);
- releaseScratch(scr);
return branchFalse();
}
Jump branchTrue()
{
m_assembler.ensureSpace(m_assembler.maxInstructionSize + 6, sizeof(uint32_t));
- Jump m_jump = Jump(m_assembler.je());
- m_assembler.loadConstantUnReusable(0x0, scratchReg3);
- m_assembler.nop();
- m_assembler.nop();
- return m_jump;
+ m_assembler.branch(BF_OPCODE, 2);
+ return Jump(m_assembler.extraInstrForBranch(scratchReg3));
}
Jump branchFalse()
{
m_assembler.ensureSpace(m_assembler.maxInstructionSize + 6, sizeof(uint32_t));
- Jump m_jump = Jump(m_assembler.jne());
- m_assembler.loadConstantUnReusable(0x0, scratchReg3);
- m_assembler.nop();
- m_assembler.nop();
- return m_jump;
+ m_assembler.branch(BT_OPCODE, 2);
+ return Jump(m_assembler.extraInstrForBranch(scratchReg3));
}
Jump branch32(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
void sqrtDouble(FPRegisterID src, FPRegisterID dest)
{
- if (dest != src)
- m_assembler.dmovRegReg(src, dest);
+ moveDouble(src, dest);
m_assembler.dsqrt(dest);
}
+
+ void absDouble(FPRegisterID src, FPRegisterID dest)
+ {
+ moveDouble(src, dest);
+ m_assembler.dabs(dest);
+ }
Jump branchTest8(ResultCondition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))
{
return jmp;
}
+ Jump branchTest8(ResultCondition cond, BaseIndex address, TrustedImm32 mask = TrustedImm32(-1))
+ {
+ RegisterID addressTempRegister = claimScratch();
+ load8(address, addressTempRegister);
+ Jump jmp = branchTest32(cond, addressTempRegister, mask);
+ releaseScratch(addressTempRegister);
+ return jmp;
+ }
+
+ Jump branchTest8(ResultCondition cond, AbsoluteAddress address, TrustedImm32 mask = TrustedImm32(-1))
+ {
+ RegisterID addressTempRegister = claimScratch();
+ move(TrustedImmPtr(address.m_ptr), addressTempRegister);
+ load8(Address(addressTempRegister), addressTempRegister);
+ Jump jmp = branchTest32(cond, addressTempRegister, mask);
+ releaseScratch(addressTempRegister);
+ return jmp;
+ }
+
void signExtend32ToPtr(RegisterID src, RegisterID dest)
{
- if (src != dest)
- move(src, dest);
+ move(src, dest);
+ }
+
+ void zeroExtend32ToPtr(RegisterID src, RegisterID dest)
+ {
+ move(src, dest);
}
Jump branch8(RelationalCondition cond, Address left, TrustedImm32 right)
return jmp;
}
- Jump branchTruncateDoubleToInt32(FPRegisterID src, RegisterID dest)
+ Jump branch8(RelationalCondition cond, AbsoluteAddress left, TrustedImm32 right)
+ {
+ RegisterID addressTempRegister = claimScratch();
+ load8(left, addressTempRegister);
+ Jump jmp = branch32(cond, addressTempRegister, right);
+ releaseScratch(addressTempRegister);
+ return jmp;
+ }
+
+ void compare8(RelationalCondition cond, Address left, TrustedImm32 right, RegisterID dest)
+ {
+ RegisterID addressTempRegister = claimScratch();
+ load8(left, addressTempRegister);
+ compare32(cond, addressTempRegister, right, dest);
+ releaseScratch(addressTempRegister);
+ }
+
+ enum BranchTruncateType { BranchIfTruncateFailed, BranchIfTruncateSuccessful };
+ Jump branchTruncateDoubleToInt32(FPRegisterID src, RegisterID dest, BranchTruncateType branchType = BranchIfTruncateFailed)
+ {
+ Jump result;
+ truncateDoubleToInt32(src, dest);
+ RegisterID intscr = claimScratch();
+ m_assembler.loadConstant(0x7fffffff, intscr);
+ m_assembler.cmplRegReg(dest, intscr, SH4Condition(Equal));
+ m_assembler.ensureSpace(m_assembler.maxInstructionSize + 12, sizeof(uint32_t));
+ if (branchType == BranchIfTruncateFailed) {
+ m_assembler.branch(BT_OPCODE, 2);
+ m_assembler.addlImm8r(1, intscr);
+ m_assembler.cmplRegReg(dest, intscr, SH4Condition(Equal));
+ result = branchTrue();
+ } else {
+ Jump out = Jump(m_assembler.je(), SH4Assembler::JumpNear);
+ m_assembler.addlImm8r(1, intscr);
+ m_assembler.cmplRegReg(dest, intscr, SH4Condition(Equal));
+ result = branchFalse();
+ out.link(this);
+ }
+ releaseScratch(intscr);
+ return result;
+ }
+
+ Jump branchTruncateDoubleToUint32(FPRegisterID src, RegisterID dest, BranchTruncateType branchType = BranchIfTruncateFailed)
+ {
+ Jump result;
+ RegisterID intscr = claimScratch();
+ m_assembler.loadConstant(0x80000000, intscr);
+ convertInt32ToDouble(intscr, fscratch);
+ addDouble(src, fscratch);
+ truncateDoubleToInt32(fscratch, dest);
+ m_assembler.cmplRegReg(dest, intscr, SH4Condition(Equal));
+ m_assembler.ensureSpace(m_assembler.maxInstructionSize + 16, sizeof(uint32_t));
+ if (branchType == BranchIfTruncateFailed) {
+ m_assembler.branch(BT_OPCODE, 4);
+ m_assembler.addlImm8r(-1, intscr);
+ m_assembler.cmplRegReg(dest, intscr, SH4Condition(Equal));
+ m_assembler.addlImm8r(1, intscr);
+ m_assembler.sublRegReg(intscr, dest);
+ result = branchTrue();
+ } else {
+ Jump out = Jump(m_assembler.je(), SH4Assembler::JumpNear);
+ m_assembler.addlImm8r(-1, intscr);
+ m_assembler.cmplRegReg(dest, intscr, SH4Condition(Equal));
+ m_assembler.addlImm8r(1, intscr);
+ m_assembler.sublRegReg(intscr, dest);
+ result = branchFalse();
+ out.link(this);
+ }
+ releaseScratch(intscr);
+ return result;
+ }
+
+ void truncateDoubleToInt32(FPRegisterID src, RegisterID dest)
{
m_assembler.ftrcdrmfpul(src);
m_assembler.stsfpulReg(dest);
- m_assembler.loadConstant(0x7fffffff, scratchReg3);
- m_assembler.cmplRegReg(dest, scratchReg3, SH4Condition(Equal));
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 14, sizeof(uint32_t));
- m_assembler.branch(BT_OPCODE, 2);
- m_assembler.addlImm8r(1, scratchReg3);
- m_assembler.cmplRegReg(dest, scratchReg3, SH4Condition(Equal));
- return branchTrue();
+ }
+
+ void truncateDoubleToUint32(FPRegisterID src, RegisterID dest)
+ {
+ RegisterID intscr = claimScratch();
+ m_assembler.loadConstant(0x80000000, intscr);
+ convertInt32ToDouble(intscr, fscratch);
+ addDouble(src, fscratch);
+ m_assembler.ftrcdrmfpul(fscratch);
+ m_assembler.stsfpulReg(dest);
+ m_assembler.sublRegReg(intscr, dest);
+ releaseScratch(intscr);
}
// Stack manipulation operations
m_assembler.pushReg(src);
}
- void push(Address address)
- {
- if (!address.offset) {
- push(address.base);
- return;
- }
-
- if ((address.offset < 0) || (address.offset >= 64)) {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(address.offset, scr);
- m_assembler.addlRegReg(address.base, scr);
- m_assembler.movlMemReg(scr, SH4Registers::sp);
- m_assembler.addlImm8r(-4, SH4Registers::sp);
- releaseScratch(scr);
- return;
- }
-
- m_assembler.movlMemReg(address.offset >> 2, address.base, SH4Registers::sp);
- m_assembler.addlImm8r(-4, SH4Registers::sp);
- }
-
void push(TrustedImm32 imm)
{
RegisterID scr = claimScratch();
DataLabelPtr moveWithPatch(TrustedImmPtr initialValue, RegisterID dest)
{
+ m_assembler.ensureSpace(m_assembler.maxInstructionSize, sizeof(uint32_t));
DataLabelPtr dataLabel(this);
- m_assembler.loadConstantUnReusable(reinterpret_cast<uint32_t>(initialValue.m_value), dest, true);
+ m_assembler.loadConstantUnReusable(reinterpret_cast<uint32_t>(initialValue.m_value), dest);
return dataLabel;
}
void move(RegisterID src, RegisterID dest)
{
- m_assembler.movlRegReg(src, dest);
+ if (src != dest)
+ m_assembler.movlRegReg(src, dest);
}
void move(TrustedImmPtr imm, RegisterID dest)
m_assembler.loadConstant(imm.asIntptr(), dest);
}
- void extuw(RegisterID src, RegisterID dst)
+ void swap(RegisterID reg1, RegisterID reg2)
{
- m_assembler.extuw(src, dst);
+ if (reg1 != reg2) {
+ xor32(reg1, reg2);
+ xor32(reg2, reg1);
+ xor32(reg1, reg2);
+ }
}
void compare32(RelationalCondition cond, RegisterID left, RegisterID right, RegisterID dest)
m_assembler.movImm8(1, dest);
}
+ void test32(ResultCondition cond, Address address, TrustedImm32 mask, RegisterID dest)
+ {
+ ASSERT((cond == Zero) || (cond == NonZero));
+
+ load32(address, dest);
+ if (mask.m_value == -1)
+ compare32(0, dest, static_cast<RelationalCondition>(cond));
+ else
+ testlImm(mask.m_value, dest);
+ if (cond != NonZero) {
+ m_assembler.movt(dest);
+ return;
+ }
+
+ m_assembler.ensureSpace(m_assembler.maxInstructionSize + 4);
+ m_assembler.movImm8(0, dest);
+ m_assembler.branch(BT_OPCODE, 0);
+ m_assembler.movImm8(1, dest);
+ }
+
void loadPtrLinkReg(ImplicitAddress address)
{
RegisterID scr = claimScratch();
{
RegisterID scr = claimScratch();
- move(TrustedImm32(reinterpret_cast<uint32_t>(left.m_ptr)), scr);
+ load32(left.m_ptr, scr);
m_assembler.cmplRegReg(right, scr, SH4Condition(cond));
releaseScratch(scr);
{
RegisterID addressTempRegister = claimScratch();
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(left.m_ptr), addressTempRegister);
+ move(TrustedImmPtr(left.m_ptr), addressTempRegister);
m_assembler.movlMemReg(addressTempRegister, addressTempRegister);
compare32(right.m_value, addressTempRegister, cond);
releaseScratch(addressTempRegister);
return branchTrue();
}
- Jump branch16(RelationalCondition cond, BaseIndex left, RegisterID right)
- {
- RegisterID scr = claimScratch();
-
- move(left.index, scr);
- lshift32(TrustedImm32(left.scale), scr);
-
- if (left.offset)
- add32(TrustedImm32(left.offset), scr);
- add32(left.base, scr);
- load16(scr, scr);
- extuw(scr, scr);
- releaseScratch(scr);
-
- return branch32(cond, scr, right);
- }
-
- Jump branch16(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
+ Jump branch8(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
{
- RegisterID scr = claimScratch();
+ ASSERT(!(right.m_value & 0xFFFFFF00));
+ RegisterID lefttmp = claimScratch();
- move(left.index, scr);
- lshift32(TrustedImm32(left.scale), scr);
+ loadEffectiveAddress(left, lefttmp);
- if (left.offset)
- add32(TrustedImm32(left.offset), scr);
- add32(left.base, scr);
- load16(scr, scr);
- extuw(scr, scr);
- RegisterID scr1 = claimScratch();
- m_assembler.loadConstant(right.m_value, scr1);
- releaseScratch(scr);
- releaseScratch(scr1);
+ load8(lefttmp, lefttmp);
+ RegisterID righttmp = claimScratch();
+ m_assembler.loadConstant(right.m_value, righttmp);
- return branch32(cond, scr, scr1);
+ Jump result = branch32(cond, lefttmp, righttmp);
+ releaseScratch(lefttmp);
+ releaseScratch(righttmp);
+ return result;
}
Jump branchTest32(ResultCondition cond, RegisterID reg, RegisterID mask)
m_assembler.testlRegReg(reg, mask);
- if (cond == NotEqual)
+ if (cond == NonZero) // NotEqual
return branchFalse();
return branchTrue();
}
else
testlImm(mask.m_value, reg);
- if (cond == NotEqual)
+ if (cond == NonZero) // NotEqual
return branchFalse();
return branchTrue();
}
else
testImm(mask.m_value, address.offset, address.base);
- if (cond == NotEqual)
+ if (cond == NonZero) // NotEqual
return branchFalse();
return branchTrue();
}
Jump branchTest32(ResultCondition cond, BaseIndex address, TrustedImm32 mask = TrustedImm32(-1))
{
+ ASSERT((cond == Zero) || (cond == NonZero));
+
RegisterID scr = claimScratch();
move(address.index, scr);
releaseScratch(scr);
- if (cond == NotEqual)
+ if (cond == NonZero) // NotEqual
return branchFalse();
return branchTrue();
}
void jump(Address address)
{
RegisterID scr = claimScratch();
-
- if ((address.offset < 0) || (address.offset >= 64)) {
- m_assembler.loadConstant(address.offset, scr);
- m_assembler.addlRegReg(address.base, scr);
- m_assembler.movlMemReg(scr, scr);
- } else if (address.offset)
- m_assembler.movlMemReg(address.offset >> 2, address.base, scr);
- else
- m_assembler.movlMemReg(address.base, scr);
+ load32(address, scr);
m_assembler.jmpReg(scr);
+ releaseScratch(scr);
+ }
+
+ void jump(AbsoluteAddress address)
+ {
+ RegisterID scr = claimScratch();
+ move(TrustedImmPtr(address.m_ptr), scr);
+ m_assembler.movlMemReg(scr, scr);
+ m_assembler.jmpReg(scr);
releaseScratch(scr);
}
// Arithmetic control flow operations
- Jump branchAdd32(ResultCondition cond, RegisterID src, RegisterID dest)
+ Jump branchNeg32(ResultCondition cond, RegisterID srcDest)
{
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
+ if (cond == Overflow)
+ return branchMul32(cond, TrustedImm32(-1), srcDest, srcDest);
+
+ neg32(srcDest);
+
+ if (cond == Signed) {
+ m_assembler.cmppz(srcDest);
+ return branchFalse();
+ }
+
+ compare32(0, srcDest, Equal);
+ return (cond == NonZero) ? branchFalse() : branchTrue();
+ }
+
+ Jump branchAdd32(ResultCondition cond, RegisterID src, RegisterID dest)
+ {
+ ASSERT((cond == Overflow) || (cond == Signed) || (cond == PositiveOrZero) || (cond == Zero) || (cond == NonZero));
+
if (cond == Overflow) {
m_assembler.addvlRegReg(src, dest);
return branchTrue();
}
- if (cond == Signed) {
- m_assembler.addlRegReg(src, dest);
- // Check if dest is negative
+ m_assembler.addlRegReg(src, dest);
+
+ if ((cond == Signed) || (cond == PositiveOrZero)) {
m_assembler.cmppz(dest);
- return branchFalse();
+ return (cond == Signed) ? branchFalse() : branchTrue();
}
- m_assembler.addlRegReg(src, dest);
compare32(0, dest, Equal);
+ return (cond == NonZero) ? branchFalse() : branchTrue();
+ }
- if (cond == NotEqual)
- return branchFalse();
- return branchTrue();
+ Jump branchAdd32(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest)
+ {
+ ASSERT((cond == Overflow) || (cond == Signed) || (cond == PositiveOrZero) || (cond == Zero) || (cond == NonZero));
+
+ if (cond == Overflow) {
+ if (src1 == dest)
+ m_assembler.addvlRegReg(src2, dest);
+ else {
+ move(src2, dest);
+ m_assembler.addvlRegReg(src1, dest);
+ }
+ return branchTrue();
+ }
+
+ add32(src1, src2, dest);
+
+ if ((cond == Signed) || (cond == PositiveOrZero)) {
+ m_assembler.cmppz(dest);
+ return (cond == Signed) ? branchFalse() : branchTrue();
+ }
+
+ compare32(0, dest, Equal);
+ return (cond == NonZero) ? branchFalse() : branchTrue();
}
Jump branchAdd32(ResultCondition cond, TrustedImm32 imm, RegisterID dest)
{
- ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
+ ASSERT((cond == Overflow) || (cond == Signed) || (cond == PositiveOrZero) || (cond == Zero) || (cond == NonZero));
+
+ RegisterID immval = claimScratch();
+ move(imm, immval);
+ Jump result = branchAdd32(cond, immval, dest);
+ releaseScratch(immval);
+ return result;
+ }
+
+ Jump branchAdd32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest)
+ {
+ ASSERT((cond == Overflow) || (cond == Signed) || (cond == PositiveOrZero) || (cond == Zero) || (cond == NonZero));
+
+ move(src, dest);
+
+ if (cond == Overflow) {
+ move(imm, scratchReg3);
+ m_assembler.addvlRegReg(scratchReg3, dest);
+ return branchTrue();
+ }
+
+ add32(imm, dest);
+
+ if ((cond == Signed) || (cond == PositiveOrZero)) {
+ m_assembler.cmppz(dest);
+ return (cond == Signed) ? branchFalse() : branchTrue();
+ }
+
+ compare32(0, dest, Equal);
+ return (cond == NonZero) ? branchFalse() : branchTrue();
+ }
+
+ Jump branchAdd32(ResultCondition cond, TrustedImm32 imm, AbsoluteAddress dest)
+ {
+ ASSERT((cond == Overflow) || (cond == Signed) || (cond == PositiveOrZero) || (cond == Zero) || (cond == NonZero));
+ bool result;
move(imm, scratchReg3);
- return branchAdd32(cond, scratchReg3, dest);
+ RegisterID destptr = claimScratch();
+ RegisterID destval = claimScratch();
+ move(TrustedImmPtr(dest.m_ptr), destptr);
+ m_assembler.movlMemReg(destptr, destval);
+ if (cond == Overflow) {
+ m_assembler.addvlRegReg(scratchReg3, destval);
+ result = true;
+ } else {
+ m_assembler.addlRegReg(scratchReg3, destval);
+ if ((cond == Signed) || (cond == PositiveOrZero)) {
+ m_assembler.cmppz(destval);
+ result = (cond == PositiveOrZero);
+ } else {
+ m_assembler.testlRegReg(destval, destval);
+ result = (cond != NonZero);
+ }
+ }
+ m_assembler.movlRegMem(destval, destptr);
+ releaseScratch(destval);
+ releaseScratch(destptr);
+ return result ? branchTrue() : branchFalse();
}
Jump branchMul32(ResultCondition cond, RegisterID src, RegisterID dest)
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
if (cond == Overflow) {
- RegisterID scr1 = claimScratch();
- RegisterID scr = claimScratch();
- m_assembler.dmullRegReg(src, dest);
+ RegisterID scrsign = claimScratch();
+ RegisterID msbres = claimScratch();
+ m_assembler.dmulslRegReg(src, dest);
m_assembler.stsmacl(dest);
- m_assembler.movImm8(-31, scr);
- m_assembler.movlRegReg(dest, scr1);
- m_assembler.shaRegReg(scr1, scr);
- m_assembler.stsmach(scr);
- m_assembler.cmplRegReg(scr, scr1, SH4Condition(Equal));
- releaseScratch(scr1);
- releaseScratch(scr);
+ m_assembler.cmppz(dest);
+ m_assembler.movt(scrsign);
+ m_assembler.addlImm8r(-1, scrsign);
+ m_assembler.stsmach(msbres);
+ m_assembler.cmplRegReg(msbres, scrsign, SH4Condition(Equal));
+ releaseScratch(msbres);
+ releaseScratch(scrsign);
return branchFalse();
}
- m_assembler.imullRegReg(src, dest);
- m_assembler.stsmacl(dest);
+ mul32(src, dest);
+
if (cond == Signed) {
- // Check if dest is negative
m_assembler.cmppz(dest);
return branchFalse();
}
compare32(0, dest, static_cast<RelationalCondition>(cond));
+ return (cond == NonZero) ? branchFalse() : branchTrue();
+ }
- if (cond == NotEqual)
+ Jump branchMul32(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest)
+ {
+ ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
+
+ if (cond == Overflow) {
+ RegisterID scrsign = claimScratch();
+ RegisterID msbres = claimScratch();
+ m_assembler.dmulslRegReg(src1, src2);
+ m_assembler.stsmacl(dest);
+ m_assembler.cmppz(dest);
+ m_assembler.movt(scrsign);
+ m_assembler.addlImm8r(-1, scrsign);
+ m_assembler.stsmach(msbres);
+ m_assembler.cmplRegReg(msbres, scrsign, SH4Condition(Equal));
+ releaseScratch(msbres);
+ releaseScratch(scrsign);
return branchFalse();
- return branchTrue();
+ }
+
+ mul32(src1, src2, dest);
+
+ if (cond == Signed) {
+ m_assembler.cmppz(dest);
+ return branchFalse();
+ }
+
+ compare32(0, dest, Equal);
+ return (cond == NonZero) ? branchFalse() : branchTrue();
}
Jump branchMul32(ResultCondition cond, TrustedImm32 imm, RegisterID src, RegisterID dest)
{
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
- move(imm, scratchReg3);
- if (src != dest)
- move(src, dest);
+ if (src == dest) {
+ move(imm, scratchReg3);
+ return branchMul32(cond, scratchReg3, dest);
+ }
- return branchMul32(cond, scratchReg3, dest);
+ move(imm, dest);
+ return branchMul32(cond, src, dest);
}
Jump branchSub32(ResultCondition cond, RegisterID src, RegisterID dest)
return branchTrue();
}
+ sub32(src, dest);
+
if (cond == Signed) {
- // Check if dest is negative
- m_assembler.sublRegReg(src, dest);
- compare32(0, dest, LessThan);
- return branchTrue();
+ m_assembler.cmppz(dest);
+ return branchFalse();
}
- sub32(src, dest);
compare32(0, dest, static_cast<RelationalCondition>(cond));
-
- if (cond == NotEqual)
- return branchFalse();
- return branchTrue();
+ return (cond == NonZero) ? branchFalse() : branchTrue();
}
Jump branchSub32(ResultCondition cond, TrustedImm32 imm, RegisterID dest)
{
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
- move(imm, scratchReg3);
- return branchSub32(cond, scratchReg3, dest);
+ RegisterID immval = claimScratch();
+ move(imm, immval);
+ Jump result = branchSub32(cond, immval, dest);
+ releaseScratch(immval);
+ return result;
}
- Jump branchOr32(ResultCondition cond, RegisterID src, RegisterID dest)
+ Jump branchSub32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest)
{
- ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero));
+ ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
- if (cond == Signed) {
- or32(src, dest);
- compare32(0, dest, static_cast<RelationalCondition>(LessThan));
+ move(src, dest);
+ return branchSub32(cond, imm, dest);
+ }
+
+ Jump branchSub32(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest)
+ {
+ ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
+
+ if (src2 != dest) {
+ move(src1, dest);
+ return branchSub32(cond, src2, dest);
+ }
+
+ if (cond == Overflow) {
+ RegisterID tmpval = claimScratch();
+ move(src1, tmpval);
+ m_assembler.subvlRegReg(src2, tmpval);
+ move(tmpval, dest);
+ releaseScratch(tmpval);
return branchTrue();
}
- or32(src, dest);
+ RegisterID tmpval = claimScratch();
+ move(src1, tmpval);
+ sub32(src2, tmpval);
+ move(tmpval, dest);
+ releaseScratch(tmpval);
+
+ if (cond == Signed) {
+ m_assembler.cmppz(dest);
+ return branchFalse();
+ }
+
compare32(0, dest, static_cast<RelationalCondition>(cond));
+ return (cond == NonZero) ? branchFalse() : branchTrue();
+ }
- if (cond == NotEqual)
+ Jump branchOr32(ResultCondition cond, RegisterID src, RegisterID dest)
+ {
+ ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero));
+
+ or32(src, dest);
+
+ if (cond == Signed) {
+ m_assembler.cmppz(dest);
return branchFalse();
- return branchTrue();
+ }
+
+ compare32(0, dest, static_cast<RelationalCondition>(cond));
+ return (cond == NonZero) ? branchFalse() : branchTrue();
}
- void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID fpTemp)
+ void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID, bool negZeroCheck = true)
{
- m_assembler.ftrcdrmfpul(src);
- m_assembler.stsfpulReg(dest);
+ truncateDoubleToInt32(src, dest);
convertInt32ToDouble(dest, fscratch);
failureCases.append(branchDouble(DoubleNotEqualOrUnordered, fscratch, src));
- if (dest == SH4Registers::r0)
- m_assembler.cmpEqImmR0(0, dest);
- else {
- m_assembler.movImm8(0, scratchReg3);
- m_assembler.cmplRegReg(scratchReg3, dest, SH4Condition(Equal));
- }
- failureCases.append(branchTrue());
+ if (negZeroCheck)
+ failureCases.append(branch32(Equal, dest, TrustedImm32(0)));
}
void neg32(RegisterID dst)
m_assembler.neg(dst, dst);
}
- void not32(RegisterID dst)
+ void urshift32(RegisterID shiftamount, RegisterID dest)
{
- m_assembler.notlReg(dst, dst);
+ RegisterID shiftTmp = claimScratch();
+ m_assembler.loadConstant(0x1f, shiftTmp);
+ m_assembler.andlRegReg(shiftamount, shiftTmp);
+ m_assembler.neg(shiftTmp, shiftTmp);
+ m_assembler.shldRegReg(dest, shiftTmp);
+ releaseScratch(shiftTmp);
}
- void urshift32(RegisterID shiftamount, RegisterID dest)
+ void urshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
{
- compare32(32, shiftamount, Equal);
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 4);
- m_assembler.branch(BT_OPCODE, 1);
- m_assembler.neg(shiftamount, shiftamount);
- m_assembler.shllRegReg(dest, shiftamount);
+ move(src, dest);
+ urshift32(shiftAmount, dest);
}
void urshift32(TrustedImm32 imm, RegisterID dest)
{
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(-(imm.m_value), scr);
- m_assembler.shaRegReg(dest, scr);
- releaseScratch(scr);
+ int immMasked = imm.m_value & 0x1f;
+ if (!immMasked)
+ return;
+
+ if ((immMasked == 1) || (immMasked == 2) || (immMasked == 8) || (immMasked == 16)) {
+ m_assembler.shlrImm8r(immMasked, dest);
+ return;
+ }
+
+ RegisterID shiftTmp = claimScratch();
+ m_assembler.loadConstant(-immMasked, shiftTmp);
+ m_assembler.shldRegReg(dest, shiftTmp);
+ releaseScratch(shiftTmp);
+ }
+
+ void urshift32(RegisterID src, TrustedImm32 shiftamount, RegisterID dest)
+ {
+ move(src, dest);
+ urshift32(shiftamount, dest);
}
Call call()
return Call(m_assembler.call(target), Call::None);
}
- void call(Address address, RegisterID target)
+ void call(Address address)
{
+ RegisterID target = claimScratch();
load32(address.base, address.offset, target);
m_assembler.ensureSpace(m_assembler.maxInstructionSize + 2);
m_assembler.branch(JSR_OPCODE, target);
m_assembler.nop();
+ releaseScratch(target);
}
void breakpoint()
{
+ m_assembler.ensureSpace(m_assembler.maxInstructionSize + 2);
m_assembler.bkpt();
m_assembler.nop();
}
{
RegisterID dataTempRegister = claimScratch();
+ m_assembler.ensureSpace(m_assembler.maxInstructionSize + 10, 2 * sizeof(uint32_t));
dataLabel = moveWithPatch(initialRightValue, dataTempRegister);
m_assembler.cmplRegReg(dataTempRegister, left, SH4Condition(cond));
releaseScratch(dataTempRegister);
m_assembler.addlRegReg(left.base, scr);
m_assembler.movlMemReg(scr, scr);
RegisterID scr1 = claimScratch();
+ m_assembler.ensureSpace(m_assembler.maxInstructionSize + 10, 2 * sizeof(uint32_t));
dataLabel = moveWithPatch(initialRightValue, scr1);
m_assembler.cmplRegReg(scr1, scr, SH4Condition(cond));
releaseScratch(scr);
m_assembler.nop();
}
+ void memoryFence()
+ {
+ m_assembler.synco();
+ }
+
+ static FunctionPtr readCallTarget(CodeLocationCall call)
+ {
+ return FunctionPtr(reinterpret_cast<void(*)()>(SH4Assembler::readCallTarget(call.dataLocation())));
+ }
+
+ static void replaceWithJump(CodeLocationLabel instructionStart, CodeLocationLabel destination)
+ {
+ SH4Assembler::replaceWithJump(instructionStart.dataLocation(), destination.dataLocation());
+ }
+
+ static ptrdiff_t maxJumpReplacementSize()
+ {
+ return SH4Assembler::maxJumpReplacementSize();
+ }
+
+ static bool canJumpReplacePatchableBranchPtrWithPatch() { return false; }
+
+ static CodeLocationLabel startOfBranchPtrWithPatchOnRegister(CodeLocationDataLabelPtr label)
+ {
+ return label.labelAtOffset(0);
+ }
+
+ static void revertJumpReplacementToBranchPtrWithPatch(CodeLocationLabel instructionStart, RegisterID rd, void* initialValue)
+ {
+ SH4Assembler::revertJumpReplacementToBranchPtrWithPatch(instructionStart.dataLocation(), rd, reinterpret_cast<int>(initialValue));
+ }
+
+ static CodeLocationLabel startOfPatchableBranchPtrWithPatchOnAddress(CodeLocationDataLabelPtr)
+ {
+ UNREACHABLE_FOR_PLATFORM();
+ return CodeLocationLabel();
+ }
+
+ static void revertJumpReplacementToPatchableBranchPtrWithPatch(CodeLocationLabel, Address, void*)
+ {
+ UNREACHABLE_FOR_PLATFORM();
+ }
+
protected:
SH4Assembler::Condition SH4Condition(RelationalCondition cond)
{
friend class LinkBuffer;
friend class RepatchBuffer;
- static void linkCall(void*, Call, FunctionPtr);
- static void repatchCall(CodeLocationCall, CodeLocationLabel);
- static void repatchCall(CodeLocationCall, FunctionPtr);
+ static void linkCall(void* code, Call call, FunctionPtr function)
+ {
+ SH4Assembler::linkCall(code, call.m_label, function.value());
+ }
+
+ static void repatchCall(CodeLocationCall call, CodeLocationLabel destination)
+ {
+ SH4Assembler::relinkCall(call.dataLocation(), destination.executableAddress());
+ }
+
+ static void repatchCall(CodeLocationCall call, FunctionPtr destination)
+ {
+ SH4Assembler::relinkCall(call.dataLocation(), destination.executableAddress());
+ }
};
} // namespace JSC
projects / apple / javascriptcore.git / blobdiff