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1 /*
2 * Copyright (C) 2009, 2010 University of Szeged
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY UNIVERSITY OF SZEGED ``AS IS'' AND ANY
15 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL UNIVERSITY OF SZEGED OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
22 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
24 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #ifndef ARMAssembler_h
28 #define ARMAssembler_h
29
30 #if ENABLE(ASSEMBLER) && CPU(ARM_TRADITIONAL)
31
32 #include "AssemblerBufferWithConstantPool.h"
33 #include "JITCompilationEffort.h"
34 #include <wtf/Assertions.h>
35 namespace JSC {
36
37 typedef uint32_t ARMWord;
38
39 #define FOR_EACH_CPU_REGISTER(V) \
40 FOR_EACH_CPU_GPREGISTER(V) \
41 FOR_EACH_CPU_SPECIAL_REGISTER(V) \
42 FOR_EACH_CPU_FPREGISTER(V)
43
44 #define FOR_EACH_CPU_GPREGISTER(V) \
45 V(void*, r0) \
46 V(void*, r1) \
47 V(void*, r2) \
48 V(void*, r3) \
49 V(void*, r4) \
50 V(void*, r5) \
51 V(void*, r6) \
52 V(void*, r7) \
53 V(void*, r8) \
54 V(void*, r9) \
55 V(void*, r10) \
56 V(void*, fp) \
57 V(void*, ip) \
58 V(void*, sp) \
59 V(void*, lr) \
60 V(void*, pc) \
61
62 #define FOR_EACH_CPU_SPECIAL_REGISTER(V) \
63 V(void*, apsr) \
64 V(void*, fpscr) \
65
66 #define FOR_EACH_CPU_FPREGISTER(V) \
67 V(double, d0) \
68 V(double, d1) \
69 V(double, d2) \
70 V(double, d3) \
71 V(double, d4) \
72 V(double, d5) \
73 V(double, d6) \
74 V(double, d7) \
75 V(double, d8) \
76 V(double, d9) \
77 V(double, d10) \
78 V(double, d11) \
79 V(double, d12) \
80 V(double, d13) \
81 V(double, d14) \
82 V(double, d15) \
83 V(double, d16) \
84 V(double, d17) \
85 V(double, d18) \
86 V(double, d19) \
87 V(double, d20) \
88 V(double, d21) \
89 V(double, d22) \
90 V(double, d23) \
91 V(double, d24) \
92 V(double, d25) \
93 V(double, d26) \
94 V(double, d27) \
95 V(double, d28) \
96 V(double, d29) \
97 V(double, d30) \
98 V(double, d31) \
99
100 namespace ARMRegisters {
101
102 typedef enum {
103 #define DECLARE_REGISTER(_type, _regName) _regName,
104 FOR_EACH_CPU_GPREGISTER(DECLARE_REGISTER)
105 #undef DECLARE_REGISTER
106
107 // Pseudonyms for some of the registers.
108 S0 = r6,
109 r11 = fp, // frame pointer
110 r12 = ip, S1 = ip,
111 r13 = sp,
112 r14 = lr,
113 r15 = pc
114 } RegisterID;
115
116 typedef enum {
117 #define DECLARE_REGISTER(_type, _regName) _regName,
118 FOR_EACH_CPU_FPREGISTER(DECLARE_REGISTER)
119 #undef DECLARE_REGISTER
120
121 // Pseudonyms for some of the registers.
122 SD0 = d7, /* Same as thumb assembler. */
123 } FPRegisterID;
124
125 } // namespace ARMRegisters
126
127 class ARMAssembler {
128 public:
129 typedef ARMRegisters::RegisterID RegisterID;
130 typedef ARMRegisters::FPRegisterID FPRegisterID;
131 typedef AssemblerBufferWithConstantPool<2048, 4, 4, ARMAssembler> ARMBuffer;
132 typedef SegmentedVector<AssemblerLabel, 64> Jumps;
133
134 ARMAssembler()
135 : m_indexOfTailOfLastWatchpoint(1)
136 {
137 }
138
139 ARMBuffer& buffer() { return m_buffer; }
140
141 static RegisterID firstRegister() { return ARMRegisters::r0; }
142 static RegisterID lastRegister() { return ARMRegisters::r15; }
143
144 static FPRegisterID firstFPRegister() { return ARMRegisters::d0; }
145 static FPRegisterID lastFPRegister() { return ARMRegisters::d31; }
146
147 // ARM conditional constants
148 typedef enum {
149 EQ = 0x00000000, // Zero / Equal.
150 NE = 0x10000000, // Non-zero / Not equal.
151 CS = 0x20000000, // Unsigned higher or same.
152 CC = 0x30000000, // Unsigned lower.
153 MI = 0x40000000, // Negative.
154 PL = 0x50000000, // Positive or zero.
155 VS = 0x60000000, // Overflowed.
156 VC = 0x70000000, // Not overflowed.
157 HI = 0x80000000, // Unsigned higher.
158 LS = 0x90000000, // Unsigned lower or same.
159 GE = 0xa0000000, // Signed greater than or equal.
160 LT = 0xb0000000, // Signed less than.
161 GT = 0xc0000000, // Signed greater than.
162 LE = 0xd0000000, // Signed less than or equal.
163 AL = 0xe0000000 // Unconditional / Always execute.
164 } Condition;
165
166 // ARM instruction constants
167 enum {
168 AND = (0x0 << 21),
169 EOR = (0x1 << 21),
170 SUB = (0x2 << 21),
171 RSB = (0x3 << 21),
172 ADD = (0x4 << 21),
173 ADC = (0x5 << 21),
174 SBC = (0x6 << 21),
175 RSC = (0x7 << 21),
176 TST = (0x8 << 21),
177 TEQ = (0x9 << 21),
178 CMP = (0xa << 21),
179 CMN = (0xb << 21),
180 ORR = (0xc << 21),
181 MOV = (0xd << 21),
182 BIC = (0xe << 21),
183 MVN = (0xf << 21),
184 MUL = 0x00000090,
185 MULL = 0x00c00090,
186 VMOV_F64 = 0x0eb00b40,
187 VADD_F64 = 0x0e300b00,
188 VDIV_F64 = 0x0e800b00,
189 VSUB_F64 = 0x0e300b40,
190 VMUL_F64 = 0x0e200b00,
191 VCMP_F64 = 0x0eb40b40,
192 VSQRT_F64 = 0x0eb10bc0,
193 VABS_F64 = 0x0eb00bc0,
194 VNEG_F64 = 0x0eb10b40,
195 STMDB = 0x09200000,
196 LDMIA = 0x08b00000,
197 B = 0x0a000000,
198 BL = 0x0b000000,
199 BX = 0x012fff10,
200 VMOV_VFP64 = 0x0c400a10,
201 VMOV_ARM64 = 0x0c500a10,
202 VMOV_VFP32 = 0x0e000a10,
203 VMOV_ARM32 = 0x0e100a10,
204 VCVT_F64_S32 = 0x0eb80bc0,
205 VCVT_S32_F64 = 0x0ebd0bc0,
206 VCVT_U32_F64 = 0x0ebc0bc0,
207 VCVT_F32_F64 = 0x0eb70bc0,
208 VCVT_F64_F32 = 0x0eb70ac0,
209 VMRS_APSR = 0x0ef1fa10,
210 CLZ = 0x016f0f10,
211 BKPT = 0xe1200070,
212 BLX = 0x012fff30,
213 #if WTF_ARM_ARCH_AT_LEAST(7)
214 MOVW = 0x03000000,
215 MOVT = 0x03400000,
216 #endif
217 NOP = 0xe1a00000,
218 DMB_SY = 0xf57ff05f,
219 #if HAVE(ARM_IDIV_INSTRUCTIONS)
220 SDIV = 0x0710f010,
221 UDIV = 0x0730f010,
222 #endif
223 };
224
225 enum {
226 Op2Immediate = (1 << 25),
227 ImmediateForHalfWordTransfer = (1 << 22),
228 Op2InvertedImmediate = (1 << 26),
229 SetConditionalCodes = (1 << 20),
230 Op2IsRegisterArgument = (1 << 25),
231 // Data transfer flags.
232 DataTransferUp = (1 << 23),
233 DataTransferWriteBack = (1 << 21),
234 DataTransferPostUpdate = (1 << 24),
235 DataTransferLoad = (1 << 20),
236 ByteDataTransfer = (1 << 22),
237 };
238
239 enum DataTransferTypeA {
240 LoadUint32 = 0x05000000 | DataTransferLoad,
241 LoadUint8 = 0x05400000 | DataTransferLoad,
242 StoreUint32 = 0x05000000,
243 StoreUint8 = 0x05400000,
244 };
245
246 enum DataTransferTypeB {
247 LoadUint16 = 0x010000b0 | DataTransferLoad,
248 LoadInt16 = 0x010000f0 | DataTransferLoad,
249 LoadInt8 = 0x010000d0 | DataTransferLoad,
250 StoreUint16 = 0x010000b0,
251 };
252
253 enum DataTransferTypeFloat {
254 LoadFloat = 0x0d000a00 | DataTransferLoad,
255 LoadDouble = 0x0d000b00 | DataTransferLoad,
256 StoreFloat = 0x0d000a00,
257 StoreDouble = 0x0d000b00,
258 };
259
260 // Masks of ARM instructions
261 enum {
262 BranchOffsetMask = 0x00ffffff,
263 ConditionalFieldMask = 0xf0000000,
264 DataTransferOffsetMask = 0xfff,
265 };
266
267 enum {
268 MinimumBranchOffsetDistance = -0x00800000,
269 MaximumBranchOffsetDistance = 0x007fffff,
270 };
271
272 enum {
273 padForAlign8 = 0x00,
274 padForAlign16 = 0x0000,
275 padForAlign32 = 0xe12fff7f // 'bkpt 0xffff' instruction.
276 };
277
278 static const ARMWord InvalidImmediate = 0xf0000000;
279 static const ARMWord InvalidBranchTarget = 0xffffffff;
280 static const int DefaultPrefetchOffset = 2;
281
282 static const ARMWord BlxInstructionMask = 0x012fff30;
283 static const ARMWord LdrOrAddInstructionMask = 0x0ff00000;
284 static const ARMWord LdrPcImmediateInstructionMask = 0x0f7f0000;
285
286 static const ARMWord AddImmediateInstruction = 0x02800000;
287 static const ARMWord BlxInstruction = 0x012fff30;
288 static const ARMWord LdrImmediateInstruction = 0x05900000;
289 static const ARMWord LdrPcImmediateInstruction = 0x051f0000;
290
291 // Instruction formating
292
293 void emitInstruction(ARMWord op, int rd, int rn, ARMWord op2)
294 {
295 ASSERT(((op2 & ~Op2Immediate) <= 0xfff) || (((op2 & ~ImmediateForHalfWordTransfer) <= 0xfff)));
296 m_buffer.putInt(op | RN(rn) | RD(rd) | op2);
297 }
298
299 void emitDoublePrecisionInstruction(ARMWord op, int dd, int dn, int dm)
300 {
301 ASSERT((dd >= 0 && dd <= 31) && (dn >= 0 && dn <= 31) && (dm >= 0 && dm <= 31));
302 m_buffer.putInt(op | ((dd & 0xf) << 12) | ((dd & 0x10) << (22 - 4))
303 | ((dn & 0xf) << 16) | ((dn & 0x10) << (7 - 4))
304 | (dm & 0xf) | ((dm & 0x10) << (5 - 4)));
305 }
306
307 void emitSinglePrecisionInstruction(ARMWord op, int sd, int sn, int sm)
308 {
309 ASSERT((sd >= 0 && sd <= 31) && (sn >= 0 && sn <= 31) && (sm >= 0 && sm <= 31));
310 m_buffer.putInt(op | ((sd >> 1) << 12) | ((sd & 0x1) << 22)
311 | ((sn >> 1) << 16) | ((sn & 0x1) << 7)
312 | (sm >> 1) | ((sm & 0x1) << 5));
313 }
314
315 void bitAnd(int rd, int rn, ARMWord op2, Condition cc = AL)
316 {
317 emitInstruction(toARMWord(cc) | AND, rd, rn, op2);
318 }
319
320 void bitAnds(int rd, int rn, ARMWord op2, Condition cc = AL)
321 {
322 emitInstruction(toARMWord(cc) | AND | SetConditionalCodes, rd, rn, op2);
323 }
324
325 void eor(int rd, int rn, ARMWord op2, Condition cc = AL)
326 {
327 emitInstruction(toARMWord(cc) | EOR, rd, rn, op2);
328 }
329
330 void eors(int rd, int rn, ARMWord op2, Condition cc = AL)
331 {
332 emitInstruction(toARMWord(cc) | EOR | SetConditionalCodes, rd, rn, op2);
333 }
334
335 void sub(int rd, int rn, ARMWord op2, Condition cc = AL)
336 {
337 emitInstruction(toARMWord(cc) | SUB, rd, rn, op2);
338 }
339
340 void subs(int rd, int rn, ARMWord op2, Condition cc = AL)
341 {
342 emitInstruction(toARMWord(cc) | SUB | SetConditionalCodes, rd, rn, op2);
343 }
344
345 void rsb(int rd, int rn, ARMWord op2, Condition cc = AL)
346 {
347 emitInstruction(toARMWord(cc) | RSB, rd, rn, op2);
348 }
349
350 void rsbs(int rd, int rn, ARMWord op2, Condition cc = AL)
351 {
352 emitInstruction(toARMWord(cc) | RSB | SetConditionalCodes, rd, rn, op2);
353 }
354
355 void add(int rd, int rn, ARMWord op2, Condition cc = AL)
356 {
357 emitInstruction(toARMWord(cc) | ADD, rd, rn, op2);
358 }
359
360 void adds(int rd, int rn, ARMWord op2, Condition cc = AL)
361 {
362 emitInstruction(toARMWord(cc) | ADD | SetConditionalCodes, rd, rn, op2);
363 }
364
365 void adc(int rd, int rn, ARMWord op2, Condition cc = AL)
366 {
367 emitInstruction(toARMWord(cc) | ADC, rd, rn, op2);
368 }
369
370 void adcs(int rd, int rn, ARMWord op2, Condition cc = AL)
371 {
372 emitInstruction(toARMWord(cc) | ADC | SetConditionalCodes, rd, rn, op2);
373 }
374
375 void sbc(int rd, int rn, ARMWord op2, Condition cc = AL)
376 {
377 emitInstruction(toARMWord(cc) | SBC, rd, rn, op2);
378 }
379
380 void sbcs(int rd, int rn, ARMWord op2, Condition cc = AL)
381 {
382 emitInstruction(toARMWord(cc) | SBC | SetConditionalCodes, rd, rn, op2);
383 }
384
385 void rsc(int rd, int rn, ARMWord op2, Condition cc = AL)
386 {
387 emitInstruction(toARMWord(cc) | RSC, rd, rn, op2);
388 }
389
390 void rscs(int rd, int rn, ARMWord op2, Condition cc = AL)
391 {
392 emitInstruction(toARMWord(cc) | RSC | SetConditionalCodes, rd, rn, op2);
393 }
394
395 void tst(int rn, ARMWord op2, Condition cc = AL)
396 {
397 emitInstruction(toARMWord(cc) | TST | SetConditionalCodes, 0, rn, op2);
398 }
399
400 void teq(int rn, ARMWord op2, Condition cc = AL)
401 {
402 emitInstruction(toARMWord(cc) | TEQ | SetConditionalCodes, 0, rn, op2);
403 }
404
405 void cmp(int rn, ARMWord op2, Condition cc = AL)
406 {
407 emitInstruction(toARMWord(cc) | CMP | SetConditionalCodes, 0, rn, op2);
408 }
409
410 void cmn(int rn, ARMWord op2, Condition cc = AL)
411 {
412 emitInstruction(toARMWord(cc) | CMN | SetConditionalCodes, 0, rn, op2);
413 }
414
415 void orr(int rd, int rn, ARMWord op2, Condition cc = AL)
416 {
417 emitInstruction(toARMWord(cc) | ORR, rd, rn, op2);
418 }
419
420 void orrs(int rd, int rn, ARMWord op2, Condition cc = AL)
421 {
422 emitInstruction(toARMWord(cc) | ORR | SetConditionalCodes, rd, rn, op2);
423 }
424
425 void mov(int rd, ARMWord op2, Condition cc = AL)
426 {
427 emitInstruction(toARMWord(cc) | MOV, rd, ARMRegisters::r0, op2);
428 }
429
430 #if WTF_ARM_ARCH_AT_LEAST(7)
431 void movw(int rd, ARMWord op2, Condition cc = AL)
432 {
433 ASSERT((op2 | 0xf0fff) == 0xf0fff);
434 m_buffer.putInt(toARMWord(cc) | MOVW | RD(rd) | op2);
435 }
436
437 void movt(int rd, ARMWord op2, Condition cc = AL)
438 {
439 ASSERT((op2 | 0xf0fff) == 0xf0fff);
440 m_buffer.putInt(toARMWord(cc) | MOVT | RD(rd) | op2);
441 }
442 #endif
443
444 void movs(int rd, ARMWord op2, Condition cc = AL)
445 {
446 emitInstruction(toARMWord(cc) | MOV | SetConditionalCodes, rd, ARMRegisters::r0, op2);
447 }
448
449 void bic(int rd, int rn, ARMWord op2, Condition cc = AL)
450 {
451 emitInstruction(toARMWord(cc) | BIC, rd, rn, op2);
452 }
453
454 void bics(int rd, int rn, ARMWord op2, Condition cc = AL)
455 {
456 emitInstruction(toARMWord(cc) | BIC | SetConditionalCodes, rd, rn, op2);
457 }
458
459 void mvn(int rd, ARMWord op2, Condition cc = AL)
460 {
461 emitInstruction(toARMWord(cc) | MVN, rd, ARMRegisters::r0, op2);
462 }
463
464 void mvns(int rd, ARMWord op2, Condition cc = AL)
465 {
466 emitInstruction(toARMWord(cc) | MVN | SetConditionalCodes, rd, ARMRegisters::r0, op2);
467 }
468
469 void mul(int rd, int rn, int rm, Condition cc = AL)
470 {
471 m_buffer.putInt(toARMWord(cc) | MUL | RN(rd) | RS(rn) | RM(rm));
472 }
473
474 void muls(int rd, int rn, int rm, Condition cc = AL)
475 {
476 m_buffer.putInt(toARMWord(cc) | MUL | SetConditionalCodes | RN(rd) | RS(rn) | RM(rm));
477 }
478
479 void mull(int rdhi, int rdlo, int rn, int rm, Condition cc = AL)
480 {
481 m_buffer.putInt(toARMWord(cc) | MULL | RN(rdhi) | RD(rdlo) | RS(rn) | RM(rm));
482 }
483
484 #if HAVE(ARM_IDIV_INSTRUCTIONS)
485 template<int datasize>
486 void sdiv(int rd, int rn, int rm, Condition cc = AL)
487 {
488 static_assert(datasize == 32, "sdiv datasize must be 32 for armv7s");
489 ASSERT(rd != ARMRegisters::pc);
490 ASSERT(rn != ARMRegisters::pc);
491 ASSERT(rm != ARMRegisters::pc);
492 m_buffer.putInt(toARMWord(cc) | SDIV | RN(rd) | RM(rn) | RS(rm));
493 }
494
495 void udiv(int rd, int rn, int rm, Condition cc = AL)
496 {
497 ASSERT(rd != ARMRegisters::pc);
498 ASSERT(rn != ARMRegisters::pc);
499 ASSERT(rm != ARMRegisters::pc);
500 m_buffer.putInt(toARMWord(cc) | UDIV | RN(rd) | RM(rn) | RS(rm));
501 }
502 #endif
503
504 void vmov_f64(int dd, int dm, Condition cc = AL)
505 {
506 emitDoublePrecisionInstruction(toARMWord(cc) | VMOV_F64, dd, 0, dm);
507 }
508
509 void vadd_f64(int dd, int dn, int dm, Condition cc = AL)
510 {
511 emitDoublePrecisionInstruction(toARMWord(cc) | VADD_F64, dd, dn, dm);
512 }
513
514 void vdiv_f64(int dd, int dn, int dm, Condition cc = AL)
515 {
516 emitDoublePrecisionInstruction(toARMWord(cc) | VDIV_F64, dd, dn, dm);
517 }
518
519 void vsub_f64(int dd, int dn, int dm, Condition cc = AL)
520 {
521 emitDoublePrecisionInstruction(toARMWord(cc) | VSUB_F64, dd, dn, dm);
522 }
523
524 void vmul_f64(int dd, int dn, int dm, Condition cc = AL)
525 {
526 emitDoublePrecisionInstruction(toARMWord(cc) | VMUL_F64, dd, dn, dm);
527 }
528
529 void vcmp_f64(int dd, int dm, Condition cc = AL)
530 {
531 emitDoublePrecisionInstruction(toARMWord(cc) | VCMP_F64, dd, 0, dm);
532 }
533
534 void vsqrt_f64(int dd, int dm, Condition cc = AL)
535 {
536 emitDoublePrecisionInstruction(toARMWord(cc) | VSQRT_F64, dd, 0, dm);
537 }
538
539 void vabs_f64(int dd, int dm, Condition cc = AL)
540 {
541 emitDoublePrecisionInstruction(toARMWord(cc) | VABS_F64, dd, 0, dm);
542 }
543
544 void vneg_f64(int dd, int dm, Condition cc = AL)
545 {
546 emitDoublePrecisionInstruction(toARMWord(cc) | VNEG_F64, dd, 0, dm);
547 }
548
549 void ldrImmediate(int rd, ARMWord imm, Condition cc = AL)
550 {
551 m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm, true);
552 }
553
554 void ldrUniqueImmediate(int rd, ARMWord imm, Condition cc = AL)
555 {
556 m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm);
557 }
558
559 void dtrUp(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
560 {
561 emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rb, op2);
562 }
563
564 void dtrUpRegister(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)
565 {
566 emitInstruction(toARMWord(cc) | transferType | DataTransferUp | Op2IsRegisterArgument, rd, rb, rm);
567 }
568
569 void dtrDown(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
570 {
571 emitInstruction(toARMWord(cc) | transferType, rd, rb, op2);
572 }
573
574 void dtrDownRegister(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)
575 {
576 emitInstruction(toARMWord(cc) | transferType | Op2IsRegisterArgument, rd, rb, rm);
577 }
578
579 void halfDtrUp(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
580 {
581 emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rb, op2);
582 }
583
584 void halfDtrUpRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL)
585 {
586 emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rn, rm);
587 }
588
589 void halfDtrDown(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
590 {
591 emitInstruction(toARMWord(cc) | transferType, rd, rb, op2);
592 }
593
594 void halfDtrDownRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL)
595 {
596 emitInstruction(toARMWord(cc) | transferType, rd, rn, rm);
597 }
598
599 void doubleDtrUp(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL)
600 {
601 ASSERT(op2 <= 0xff && rd <= 15);
602 /* Only d0-d15 and s0, s2, s4 ... s30 are supported. */
603 m_buffer.putInt(toARMWord(cc) | DataTransferUp | type | (rd << 12) | RN(rb) | op2);
604 }
605
606 void doubleDtrDown(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL)
607 {
608 ASSERT(op2 <= 0xff && rd <= 15);
609 /* Only d0-d15 and s0, s2, s4 ... s30 are supported. */
610 m_buffer.putInt(toARMWord(cc) | type | (rd << 12) | RN(rb) | op2);
611 }
612
613 void push(int reg, Condition cc = AL)
614 {
615 ASSERT(ARMWord(reg) <= 0xf);
616 m_buffer.putInt(toARMWord(cc) | StoreUint32 | DataTransferWriteBack | RN(ARMRegisters::sp) | RD(reg) | 0x4);
617 }
618
619 void pop(int reg, Condition cc = AL)
620 {
621 ASSERT(ARMWord(reg) <= 0xf);
622 m_buffer.putInt(toARMWord(cc) | (LoadUint32 ^ DataTransferPostUpdate) | DataTransferUp | RN(ARMRegisters::sp) | RD(reg) | 0x4);
623 }
624
625 inline void poke(int reg, Condition cc = AL)
626 {
627 dtrDown(StoreUint32, ARMRegisters::sp, 0, reg, cc);
628 }
629
630 inline void peek(int reg, Condition cc = AL)
631 {
632 dtrUp(LoadUint32, reg, ARMRegisters::sp, 0, cc);
633 }
634
635 void vmov_vfp64(int sm, int rt, int rt2, Condition cc = AL)
636 {
637 ASSERT(rt != rt2);
638 m_buffer.putInt(toARMWord(cc) | VMOV_VFP64 | RN(rt2) | RD(rt) | (sm & 0xf) | ((sm & 0x10) << (5 - 4)));
639 }
640
641 void vmov_arm64(int rt, int rt2, int sm, Condition cc = AL)
642 {
643 ASSERT(rt != rt2);
644 m_buffer.putInt(toARMWord(cc) | VMOV_ARM64 | RN(rt2) | RD(rt) | (sm & 0xf) | ((sm & 0x10) << (5 - 4)));
645 }
646
647 void vmov_vfp32(int sn, int rt, Condition cc = AL)
648 {
649 ASSERT(rt <= 15);
650 emitSinglePrecisionInstruction(toARMWord(cc) | VMOV_VFP32, rt << 1, sn, 0);
651 }
652
653 void vmov_arm32(int rt, int sn, Condition cc = AL)
654 {
655 ASSERT(rt <= 15);
656 emitSinglePrecisionInstruction(toARMWord(cc) | VMOV_ARM32, rt << 1, sn, 0);
657 }
658
659 void vcvt_f64_s32(int dd, int sm, Condition cc = AL)
660 {
661 ASSERT(!(sm & 0x1)); // sm must be divisible by 2
662 emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_F64_S32, dd, 0, (sm >> 1));
663 }
664
665 void vcvt_s32_f64(int sd, int dm, Condition cc = AL)
666 {
667 ASSERT(!(sd & 0x1)); // sd must be divisible by 2
668 emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_S32_F64, (sd >> 1), 0, dm);
669 }
670
671 void vcvt_u32_f64(int sd, int dm, Condition cc = AL)
672 {
673 ASSERT(!(sd & 0x1)); // sd must be divisible by 2
674 emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_U32_F64, (sd >> 1), 0, dm);
675 }
676
677 void vcvt_f64_f32(int dd, int sm, Condition cc = AL)
678 {
679 ASSERT(dd <= 15 && sm <= 15);
680 emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_F64_F32, dd, 0, sm);
681 }
682
683 void vcvt_f32_f64(int dd, int sm, Condition cc = AL)
684 {
685 ASSERT(dd <= 15 && sm <= 15);
686 emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_F32_F64, dd, 0, sm);
687 }
688
689 void vmrs_apsr(Condition cc = AL)
690 {
691 m_buffer.putInt(toARMWord(cc) | VMRS_APSR);
692 }
693
694 void clz(int rd, int rm, Condition cc = AL)
695 {
696 m_buffer.putInt(toARMWord(cc) | CLZ | RD(rd) | RM(rm));
697 }
698
699 void bkpt(ARMWord value)
700 {
701 m_buffer.putInt(BKPT | ((value & 0xff0) << 4) | (value & 0xf));
702 }
703
704 void nop()
705 {
706 m_buffer.putInt(NOP);
707 }
708
709 void dmbSY()
710 {
711 m_buffer.putInt(DMB_SY);
712 }
713
714 void bx(int rm, Condition cc = AL)
715 {
716 emitInstruction(toARMWord(cc) | BX, 0, 0, RM(rm));
717 }
718
719 AssemblerLabel blx(int rm, Condition cc = AL)
720 {
721 emitInstruction(toARMWord(cc) | BLX, 0, 0, RM(rm));
722 return m_buffer.label();
723 }
724
725 static ARMWord lsl(int reg, ARMWord value)
726 {
727 ASSERT(reg <= ARMRegisters::pc);
728 ASSERT(value <= 0x1f);
729 return reg | (value << 7) | 0x00;
730 }
731
732 static ARMWord lsr(int reg, ARMWord value)
733 {
734 ASSERT(reg <= ARMRegisters::pc);
735 ASSERT(value <= 0x1f);
736 return reg | (value << 7) | 0x20;
737 }
738
739 static ARMWord asr(int reg, ARMWord value)
740 {
741 ASSERT(reg <= ARMRegisters::pc);
742 ASSERT(value <= 0x1f);
743 return reg | (value << 7) | 0x40;
744 }
745
746 static ARMWord lslRegister(int reg, int shiftReg)
747 {
748 ASSERT(reg <= ARMRegisters::pc);
749 ASSERT(shiftReg <= ARMRegisters::pc);
750 return reg | (shiftReg << 8) | 0x10;
751 }
752
753 static ARMWord lsrRegister(int reg, int shiftReg)
754 {
755 ASSERT(reg <= ARMRegisters::pc);
756 ASSERT(shiftReg <= ARMRegisters::pc);
757 return reg | (shiftReg << 8) | 0x30;
758 }
759
760 static ARMWord asrRegister(int reg, int shiftReg)
761 {
762 ASSERT(reg <= ARMRegisters::pc);
763 ASSERT(shiftReg <= ARMRegisters::pc);
764 return reg | (shiftReg << 8) | 0x50;
765 }
766
767 // General helpers
768
769 size_t codeSize() const
770 {
771 return m_buffer.codeSize();
772 }
773
774 void ensureSpace(int insnSpace, int constSpace)
775 {
776 m_buffer.ensureSpace(insnSpace, constSpace);
777 }
778
779 int sizeOfConstantPool()
780 {
781 return m_buffer.sizeOfConstantPool();
782 }
783
784 AssemblerLabel labelIgnoringWatchpoints()
785 {
786 m_buffer.ensureSpaceForAnyInstruction();
787 return m_buffer.label();
788 }
789
790 AssemblerLabel labelForWatchpoint()
791 {
792 m_buffer.ensureSpaceForAnyInstruction(maxJumpReplacementSize() / sizeof(ARMWord));
793 AssemblerLabel result = m_buffer.label();
794 if (result.m_offset != (m_indexOfTailOfLastWatchpoint - maxJumpReplacementSize()))
795 result = label();
796 m_indexOfTailOfLastWatchpoint = result.m_offset + maxJumpReplacementSize();
797 return label();
798 }
799
800 AssemblerLabel label()
801 {
802 AssemblerLabel result = labelIgnoringWatchpoints();
803 while (result.m_offset + 1 < m_indexOfTailOfLastWatchpoint) {
804 nop();
805 // The available number of instructions are ensured by labelForWatchpoint.
806 result = m_buffer.label();
807 }
808 return result;
809 }
810
811 AssemblerLabel align(int alignment)
812 {
813 while (!m_buffer.isAligned(alignment))
814 mov(ARMRegisters::r0, ARMRegisters::r0);
815
816 return label();
817 }
818
819 AssemblerLabel loadBranchTarget(int rd, Condition cc = AL, int useConstantPool = 0)
820 {
821 ensureSpace(sizeof(ARMWord), sizeof(ARMWord));
822 m_jumps.append(m_buffer.codeSize() | (useConstantPool & 0x1));
823 ldrUniqueImmediate(rd, InvalidBranchTarget, cc);
824 return m_buffer.label();
825 }
826
827 AssemblerLabel jmp(Condition cc = AL, int useConstantPool = 0)
828 {
829 return loadBranchTarget(ARMRegisters::pc, cc, useConstantPool);
830 }
831
832 void prepareExecutableCopy(void* to);
833
834 unsigned debugOffset() { return m_buffer.debugOffset(); }
835
836 // DFG assembly helpers for moving data between fp and registers.
837 void vmov(RegisterID rd1, RegisterID rd2, FPRegisterID rn)
838 {
839 vmov_arm64(rd1, rd2, rn);
840 }
841
842 void vmov(FPRegisterID rd, RegisterID rn1, RegisterID rn2)
843 {
844 vmov_vfp64(rd, rn1, rn2);
845 }
846
847 // Patching helpers
848
849 static ARMWord* getLdrImmAddress(ARMWord* insn)
850 {
851 // Check for call
852 if ((*insn & LdrPcImmediateInstructionMask) != LdrPcImmediateInstruction) {
853 // Must be BLX
854 ASSERT((*insn & BlxInstructionMask) == BlxInstruction);
855 insn--;
856 }
857
858 // Must be an ldr ..., [pc +/- imm]
859 ASSERT((*insn & LdrPcImmediateInstructionMask) == LdrPcImmediateInstruction);
860
861 ARMWord addr = reinterpret_cast<ARMWord>(insn) + DefaultPrefetchOffset * sizeof(ARMWord);
862 if (*insn & DataTransferUp)
863 return reinterpret_cast<ARMWord*>(addr + (*insn & DataTransferOffsetMask));
864 return reinterpret_cast<ARMWord*>(addr - (*insn & DataTransferOffsetMask));
865 }
866
867 static ARMWord* getLdrImmAddressOnPool(ARMWord* insn, uint32_t* constPool)
868 {
869 // Must be an ldr ..., [pc +/- imm]
870 ASSERT((*insn & LdrPcImmediateInstructionMask) == LdrPcImmediateInstruction);
871
872 if (*insn & 0x1)
873 return reinterpret_cast<ARMWord*>(constPool + ((*insn & DataTransferOffsetMask) >> 1));
874 return getLdrImmAddress(insn);
875 }
876
877 static void patchPointerInternal(intptr_t from, void* to)
878 {
879 ARMWord* insn = reinterpret_cast<ARMWord*>(from);
880 ARMWord* addr = getLdrImmAddress(insn);
881 *addr = reinterpret_cast<ARMWord>(to);
882 }
883
884 static ARMWord patchConstantPoolLoad(ARMWord load, ARMWord value)
885 {
886 value = (value << 1) + 1;
887 ASSERT(!(value & ~DataTransferOffsetMask));
888 return (load & ~DataTransferOffsetMask) | value;
889 }
890
891 static void patchConstantPoolLoad(void* loadAddr, void* constPoolAddr);
892
893 // Read pointers
894 static void* readPointer(void* from)
895 {
896 ARMWord* instruction = reinterpret_cast<ARMWord*>(from);
897 ARMWord* address = getLdrImmAddress(instruction);
898 return *reinterpret_cast<void**>(address);
899 }
900
901 // Patch pointers
902
903 static void linkPointer(void* code, AssemblerLabel from, void* to)
904 {
905 patchPointerInternal(reinterpret_cast<intptr_t>(code) + from.m_offset, to);
906 }
907
908 static void repatchInt32(void* where, int32_t to)
909 {
910 patchPointerInternal(reinterpret_cast<intptr_t>(where), reinterpret_cast<void*>(to));
911 }
912
913 static void repatchCompact(void* where, int32_t value)
914 {
915 ARMWord* instruction = reinterpret_cast<ARMWord*>(where);
916 ASSERT((*instruction & 0x0f700000) == LoadUint32);
917 if (value >= 0)
918 *instruction = (*instruction & 0xff7ff000) | DataTransferUp | value;
919 else
920 *instruction = (*instruction & 0xff7ff000) | -value;
921 cacheFlush(instruction, sizeof(ARMWord));
922 }
923
924 static void repatchPointer(void* from, void* to)
925 {
926 patchPointerInternal(reinterpret_cast<intptr_t>(from), to);
927 }
928
929 // Linkers
930 static intptr_t getAbsoluteJumpAddress(void* base, int offset = 0)
931 {
932 return reinterpret_cast<intptr_t>(base) + offset - sizeof(ARMWord);
933 }
934
935 void linkJump(AssemblerLabel from, AssemblerLabel to)
936 {
937 ARMWord* insn = reinterpret_cast<ARMWord*>(getAbsoluteJumpAddress(m_buffer.data(), from.m_offset));
938 ARMWord* addr = getLdrImmAddressOnPool(insn, m_buffer.poolAddress());
939 *addr = toARMWord(to.m_offset);
940 }
941
942 static void linkJump(void* code, AssemblerLabel from, void* to)
943 {
944 patchPointerInternal(getAbsoluteJumpAddress(code, from.m_offset), to);
945 }
946
947 static void relinkJump(void* from, void* to)
948 {
949 patchPointerInternal(getAbsoluteJumpAddress(from), to);
950 }
951
952 static void linkCall(void* code, AssemblerLabel from, void* to)
953 {
954 patchPointerInternal(getAbsoluteJumpAddress(code, from.m_offset), to);
955 }
956
957 static void relinkCall(void* from, void* to)
958 {
959 patchPointerInternal(getAbsoluteJumpAddress(from), to);
960 }
961
962 static void* readCallTarget(void* from)
963 {
964 return reinterpret_cast<void*>(readPointer(reinterpret_cast<void*>(getAbsoluteJumpAddress(from))));
965 }
966
967 static void replaceWithJump(void* instructionStart, void* to)
968 {
969 ARMWord* instruction = reinterpret_cast<ARMWord*>(instructionStart);
970 intptr_t difference = reinterpret_cast<intptr_t>(to) - (reinterpret_cast<intptr_t>(instruction) + DefaultPrefetchOffset * sizeof(ARMWord));
971
972 if (!(difference & 1)) {
973 difference >>= 2;
974 if ((difference <= MaximumBranchOffsetDistance && difference >= MinimumBranchOffsetDistance)) {
975 // Direct branch.
976 instruction[0] = B | AL | (difference & BranchOffsetMask);
977 cacheFlush(instruction, sizeof(ARMWord));
978 return;
979 }
980 }
981
982 // Load target.
983 instruction[0] = LoadUint32 | AL | RN(ARMRegisters::pc) | RD(ARMRegisters::pc) | 4;
984 instruction[1] = reinterpret_cast<ARMWord>(to);
985 cacheFlush(instruction, sizeof(ARMWord) * 2);
986 }
987
988 static ptrdiff_t maxJumpReplacementSize()
989 {
990 return sizeof(ARMWord) * 2;
991 }
992
993 static void replaceWithLoad(void* instructionStart)
994 {
995 ARMWord* instruction = reinterpret_cast<ARMWord*>(instructionStart);
996 cacheFlush(instruction, sizeof(ARMWord));
997
998 ASSERT((*instruction & LdrOrAddInstructionMask) == AddImmediateInstruction || (*instruction & LdrOrAddInstructionMask) == LdrImmediateInstruction);
999 if ((*instruction & LdrOrAddInstructionMask) == AddImmediateInstruction) {
1000 *instruction = (*instruction & ~LdrOrAddInstructionMask) | LdrImmediateInstruction;
1001 cacheFlush(instruction, sizeof(ARMWord));
1002 }
1003 }
1004
1005 static void replaceWithAddressComputation(void* instructionStart)
1006 {
1007 ARMWord* instruction = reinterpret_cast<ARMWord*>(instructionStart);
1008 cacheFlush(instruction, sizeof(ARMWord));
1009
1010 ASSERT((*instruction & LdrOrAddInstructionMask) == AddImmediateInstruction || (*instruction & LdrOrAddInstructionMask) == LdrImmediateInstruction);
1011 if ((*instruction & LdrOrAddInstructionMask) == LdrImmediateInstruction) {
1012 *instruction = (*instruction & ~LdrOrAddInstructionMask) | AddImmediateInstruction;
1013 cacheFlush(instruction, sizeof(ARMWord));
1014 }
1015 }
1016
1017 static void revertBranchPtrWithPatch(void* instructionStart, RegisterID rn, ARMWord imm)
1018 {
1019 ARMWord* instruction = reinterpret_cast<ARMWord*>(instructionStart);
1020
1021 ASSERT((instruction[2] & LdrPcImmediateInstructionMask) == LdrPcImmediateInstruction);
1022 instruction[0] = toARMWord(AL) | ((instruction[2] & 0x0fff0fff) + sizeof(ARMWord)) | RD(ARMRegisters::S1);
1023 *getLdrImmAddress(instruction) = imm;
1024 instruction[1] = toARMWord(AL) | CMP | SetConditionalCodes | RN(rn) | RM(ARMRegisters::S1);
1025 cacheFlush(instruction, 2 * sizeof(ARMWord));
1026 }
1027
1028 // Address operations
1029
1030 static void* getRelocatedAddress(void* code, AssemblerLabel label)
1031 {
1032 return reinterpret_cast<void*>(reinterpret_cast<char*>(code) + label.m_offset);
1033 }
1034
1035 // Address differences
1036
1037 static int getDifferenceBetweenLabels(AssemblerLabel a, AssemblerLabel b)
1038 {
1039 return b.m_offset - a.m_offset;
1040 }
1041
1042 static unsigned getCallReturnOffset(AssemblerLabel call)
1043 {
1044 return call.m_offset;
1045 }
1046
1047 // Handle immediates
1048
1049 static ARMWord getOp2(ARMWord imm);
1050
1051 // Fast case if imm is known to be between 0 and 0xff
1052 static ARMWord getOp2Byte(ARMWord imm)
1053 {
1054 ASSERT(imm <= 0xff);
1055 return Op2Immediate | imm;
1056 }
1057
1058 static ARMWord getOp2Half(ARMWord imm)
1059 {
1060 ASSERT(imm <= 0xff);
1061 return ImmediateForHalfWordTransfer | (imm & 0x0f) | ((imm & 0xf0) << 4);
1062 }
1063
1064 #if WTF_ARM_ARCH_AT_LEAST(7)
1065 static ARMWord getImm16Op2(ARMWord imm)
1066 {
1067 if (imm <= 0xffff)
1068 return (imm & 0xf000) << 4 | (imm & 0xfff);
1069 return InvalidImmediate;
1070 }
1071 #endif
1072 ARMWord getImm(ARMWord imm, int tmpReg, bool invert = false);
1073 void moveImm(ARMWord imm, int dest);
1074 ARMWord encodeComplexImm(ARMWord imm, int dest);
1075
1076 // Memory load/store helpers
1077
1078 void dataTransfer32(DataTransferTypeA, RegisterID srcDst, RegisterID base, int32_t offset);
1079 void baseIndexTransfer32(DataTransferTypeA, RegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset);
1080 void dataTransfer16(DataTransferTypeB, RegisterID srcDst, RegisterID base, int32_t offset);
1081 void baseIndexTransfer16(DataTransferTypeB, RegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset);
1082 void dataTransferFloat(DataTransferTypeFloat, FPRegisterID srcDst, RegisterID base, int32_t offset);
1083 void baseIndexTransferFloat(DataTransferTypeFloat, FPRegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset);
1084
1085 // Constant pool hnadlers
1086
1087 static ARMWord placeConstantPoolBarrier(int offset)
1088 {
1089 offset = (offset - sizeof(ARMWord)) >> 2;
1090 ASSERT((offset <= MaximumBranchOffsetDistance && offset >= MinimumBranchOffsetDistance));
1091 return AL | B | (offset & BranchOffsetMask);
1092 }
1093
1094 #if OS(LINUX) && COMPILER(GCC)
1095 static inline void linuxPageFlush(uintptr_t begin, uintptr_t end)
1096 {
1097 asm volatile(
1098 "push {r7}\n"
1099 "mov r0, %0\n"
1100 "mov r1, %1\n"
1101 "mov r7, #0xf0000\n"
1102 "add r7, r7, #0x2\n"
1103 "mov r2, #0x0\n"
1104 "svc 0x0\n"
1105 "pop {r7}\n"
1106 :
1107 : "r" (begin), "r" (end)
1108 : "r0", "r1", "r2");
1109 }
1110 #endif
1111
1112 static void cacheFlush(void* code, size_t size)
1113 {
1114 #if OS(LINUX) && COMPILER(GCC)
1115 size_t page = pageSize();
1116 uintptr_t current = reinterpret_cast<uintptr_t>(code);
1117 uintptr_t end = current + size;
1118 uintptr_t firstPageEnd = (current & ~(page - 1)) + page;
1119
1120 if (end <= firstPageEnd) {
1121 linuxPageFlush(current, end);
1122 return;
1123 }
1124
1125 linuxPageFlush(current, firstPageEnd);
1126
1127 for (current = firstPageEnd; current + page < end; current += page)
1128 linuxPageFlush(current, current + page);
1129
1130 linuxPageFlush(current, end);
1131 #else
1132 #error "The cacheFlush support is missing on this platform."
1133 #endif
1134 }
1135
1136 private:
1137 static ARMWord RM(int reg)
1138 {
1139 ASSERT(reg <= ARMRegisters::pc);
1140 return reg;
1141 }
1142
1143 static ARMWord RS(int reg)
1144 {
1145 ASSERT(reg <= ARMRegisters::pc);
1146 return reg << 8;
1147 }
1148
1149 static ARMWord RD(int reg)
1150 {
1151 ASSERT(reg <= ARMRegisters::pc);
1152 return reg << 12;
1153 }
1154
1155 static ARMWord RN(int reg)
1156 {
1157 ASSERT(reg <= ARMRegisters::pc);
1158 return reg << 16;
1159 }
1160
1161 static ARMWord getConditionalField(ARMWord i)
1162 {
1163 return i & ConditionalFieldMask;
1164 }
1165
1166 static ARMWord toARMWord(Condition cc)
1167 {
1168 return static_cast<ARMWord>(cc);
1169 }
1170
1171 static ARMWord toARMWord(uint32_t u)
1172 {
1173 return static_cast<ARMWord>(u);
1174 }
1175
1176 int genInt(int reg, ARMWord imm, bool positive);
1177
1178 ARMBuffer m_buffer;
1179 Jumps m_jumps;
1180 uint32_t m_indexOfTailOfLastWatchpoint;
1181 };
1182
1183 } // namespace JSC
1184
1185 #endif // ENABLE(ASSEMBLER) && CPU(ARM_TRADITIONAL)
1186
1187 #endif // ARMAssembler_h
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