assembler/MacroAssembler.h

   1 /*
   2  * Copyright (C) 2008 Apple Inc. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
  14  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  16  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR
  17  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  18  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  19  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  20  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  21  * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  22  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  23  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 #ifndef MacroAssembler_h
  27 #define MacroAssembler_h
  28
  29 #if ENABLE(ASSEMBLER)
  30
  31 #if CPU(ARM_THUMB2)
  32 #include "MacroAssemblerARMv7.h"
  33 namespace JSC { typedef MacroAssemblerARMv7 MacroAssemblerBase; };
  34
  35 #elif CPU(ARM_TRADITIONAL)
  36 #include "MacroAssemblerARM.h"
  37 namespace JSC { typedef MacroAssemblerARM MacroAssemblerBase; };
  38
  39 #elif CPU(MIPS)
  40 #include "MacroAssemblerMIPS.h"
  41 namespace JSC {
  42 typedef MacroAssemblerMIPS MacroAssemblerBase;
  43 };
  44
  45 #elif CPU(X86)
  46 #include "MacroAssemblerX86.h"
  47 namespace JSC { typedef MacroAssemblerX86 MacroAssemblerBase; };
  48
  49 #elif CPU(X86_64)
  50 #include "MacroAssemblerX86_64.h"
  51 namespace JSC { typedef MacroAssemblerX86_64 MacroAssemblerBase; };
  52
  53 #else
  54 #error "The MacroAssembler is not supported on this platform."
  55 #endif
  56
  57
  58 namespace JSC {
  59
  60 class MacroAssembler : public MacroAssemblerBase {
  61 public:
  62
  63     using MacroAssemblerBase::pop;
  64     using MacroAssemblerBase::jump;
  65     using MacroAssemblerBase::branch32;
  66     using MacroAssemblerBase::branch16;
  67 #if CPU(X86_64)
  68     using MacroAssemblerBase::branchPtr;
  69     using MacroAssemblerBase::branchTestPtr;
  70 #endif
  71
  72
  73     // Platform agnostic onvenience functions,
  74     // described in terms of other macro assembly methods.
  75     void pop()
  76     {
  77         addPtr(Imm32(sizeof(void*)), stackPointerRegister);
  78     }
  79
  80     void peek(RegisterID dest, int index = 0)
  81     {
  82         loadPtr(Address(stackPointerRegister, (index * sizeof(void*))), dest);
  83     }
  84
  85     void poke(RegisterID src, int index = 0)
  86     {
  87         storePtr(src, Address(stackPointerRegister, (index * sizeof(void*))));
  88     }
  89
  90     void poke(Imm32 value, int index = 0)
  91     {
  92         store32(value, Address(stackPointerRegister, (index * sizeof(void*))));
  93     }
  94
  95     void poke(ImmPtr imm, int index = 0)
  96     {
  97         storePtr(imm, Address(stackPointerRegister, (index * sizeof(void*))));
  98     }
  99
 100
 101     // Backwards banches, these are currently all implemented using existing forwards branch mechanisms.
 102     void branchPtr(Condition cond, RegisterID op1, ImmPtr imm, Label target)
 103     {
 104         branchPtr(cond, op1, imm).linkTo(target, this);
 105     }
 106
 107     void branch32(Condition cond, RegisterID op1, RegisterID op2, Label target)
 108     {
 109         branch32(cond, op1, op2).linkTo(target, this);
 110     }
 111
 112     void branch32(Condition cond, RegisterID op1, Imm32 imm, Label target)
 113     {
 114         branch32(cond, op1, imm).linkTo(target, this);
 115     }
 116
 117     void branch32(Condition cond, RegisterID left, Address right, Label target)
 118     {
 119         branch32(cond, left, right).linkTo(target, this);
 120     }
 121
 122     void branch16(Condition cond, BaseIndex left, RegisterID right, Label target)
 123     {
 124         branch16(cond, left, right).linkTo(target, this);
 125     }
 126
 127     void branchTestPtr(Condition cond, RegisterID reg, Label target)
 128     {
 129         branchTestPtr(cond, reg).linkTo(target, this);
 130     }
 131
 132     void jump(Label target)
 133     {
 134         jump().linkTo(target, this);
 135     }
 136
 137
 138     // Ptr methods
 139     // On 32-bit platforms (i.e. x86), these methods directly map onto their 32-bit equivalents.
 140     // FIXME: should this use a test for 32-bitness instead of this specific exception?
 141 #if !CPU(X86_64)
 142     void addPtr(RegisterID src, RegisterID dest)
 143     {
 144         add32(src, dest);
 145     }
 146
 147     void addPtr(Imm32 imm, RegisterID srcDest)
 148     {
 149         add32(imm, srcDest);
 150     }
 151
 152     void addPtr(ImmPtr imm, RegisterID dest)
 153     {
 154         add32(Imm32(imm), dest);
 155     }
 156
 157     void addPtr(Imm32 imm, RegisterID src, RegisterID dest)
 158     {
 159         add32(imm, src, dest);
 160     }
 161
 162     void andPtr(RegisterID src, RegisterID dest)
 163     {
 164         and32(src, dest);
 165     }
 166
 167     void andPtr(Imm32 imm, RegisterID srcDest)
 168     {
 169         and32(imm, srcDest);
 170     }
 171
 172     void orPtr(RegisterID src, RegisterID dest)
 173     {
 174         or32(src, dest);
 175     }
 176
 177     void orPtr(ImmPtr imm, RegisterID dest)
 178     {
 179         or32(Imm32(imm), dest);
 180     }
 181
 182     void orPtr(Imm32 imm, RegisterID dest)
 183     {
 184         or32(imm, dest);
 185     }
 186
 187     void subPtr(RegisterID src, RegisterID dest)
 188     {
 189         sub32(src, dest);
 190     }
 191
 192     void subPtr(Imm32 imm, RegisterID dest)
 193     {
 194         sub32(imm, dest);
 195     }
 196
 197     void subPtr(ImmPtr imm, RegisterID dest)
 198     {
 199         sub32(Imm32(imm), dest);
 200     }
 201
 202     void xorPtr(RegisterID src, RegisterID dest)
 203     {
 204         xor32(src, dest);
 205     }
 206
 207     void xorPtr(Imm32 imm, RegisterID srcDest)
 208     {
 209         xor32(imm, srcDest);
 210     }
 211
 212
 213     void loadPtr(ImplicitAddress address, RegisterID dest)
 214     {
 215         load32(address, dest);
 216     }
 217
 218     void loadPtr(BaseIndex address, RegisterID dest)
 219     {
 220         load32(address, dest);
 221     }
 222
 223     void loadPtr(void* address, RegisterID dest)
 224     {
 225         load32(address, dest);
 226     }
 227
 228     DataLabel32 loadPtrWithAddressOffsetPatch(Address address, RegisterID dest)
 229     {
 230         return load32WithAddressOffsetPatch(address, dest);
 231     }
 232
 233     void setPtr(Condition cond, RegisterID left, Imm32 right, RegisterID dest)
 234     {
 235         set32(cond, left, right, dest);
 236     }
 237
 238     void storePtr(RegisterID src, ImplicitAddress address)
 239     {
 240         store32(src, address);
 241     }
 242
 243     void storePtr(RegisterID src, BaseIndex address)
 244     {
 245         store32(src, address);
 246     }
 247
 248     void storePtr(RegisterID src, void* address)
 249     {
 250         store32(src, address);
 251     }
 252
 253     void storePtr(ImmPtr imm, ImplicitAddress address)
 254     {
 255         store32(Imm32(imm), address);
 256     }
 257
 258     void storePtr(ImmPtr imm, void* address)
 259     {
 260         store32(Imm32(imm), address);
 261     }
 262
 263     DataLabel32 storePtrWithAddressOffsetPatch(RegisterID src, Address address)
 264     {
 265         return store32WithAddressOffsetPatch(src, address);
 266     }
 267
 268
 269     Jump branchPtr(Condition cond, RegisterID left, RegisterID right)
 270     {
 271         return branch32(cond, left, right);
 272     }
 273
 274     Jump branchPtr(Condition cond, RegisterID left, ImmPtr right)
 275     {
 276         return branch32(cond, left, Imm32(right));
 277     }
 278
 279     Jump branchPtr(Condition cond, RegisterID left, Address right)
 280     {
 281         return branch32(cond, left, right);
 282     }
 283
 284     Jump branchPtr(Condition cond, Address left, RegisterID right)
 285     {
 286         return branch32(cond, left, right);
 287     }
 288
 289     Jump branchPtr(Condition cond, AbsoluteAddress left, RegisterID right)
 290     {
 291         return branch32(cond, left, right);
 292     }
 293
 294     Jump branchPtr(Condition cond, Address left, ImmPtr right)
 295     {
 296         return branch32(cond, left, Imm32(right));
 297     }
 298
 299     Jump branchPtr(Condition cond, AbsoluteAddress left, ImmPtr right)
 300     {
 301         return branch32(cond, left, Imm32(right));
 302     }
 303
 304     Jump branchTestPtr(Condition cond, RegisterID reg, RegisterID mask)
 305     {
 306         return branchTest32(cond, reg, mask);
 307     }
 308
 309     Jump branchTestPtr(Condition cond, RegisterID reg, Imm32 mask = Imm32(-1))
 310     {
 311         return branchTest32(cond, reg, mask);
 312     }
 313
 314     Jump branchTestPtr(Condition cond, Address address, Imm32 mask = Imm32(-1))
 315     {
 316         return branchTest32(cond, address, mask);
 317     }
 318
 319     Jump branchTestPtr(Condition cond, BaseIndex address, Imm32 mask = Imm32(-1))
 320     {
 321         return branchTest32(cond, address, mask);
 322     }
 323
 324
 325     Jump branchAddPtr(Condition cond, RegisterID src, RegisterID dest)
 326     {
 327         return branchAdd32(cond, src, dest);
 328     }
 329
 330     Jump branchSubPtr(Condition cond, Imm32 imm, RegisterID dest)
 331     {
 332         return branchSub32(cond, imm, dest);
 333     }
 334     using MacroAssemblerBase::branchTest8;
 335     Jump branchTest8(Condition cond, ExtendedAddress address, Imm32 mask = Imm32(-1))
 336     {
 337         return MacroAssemblerBase::branchTest8(cond, Address(address.base, address.offset), mask);
 338     }
 339 #endif
 340
 341 };
 342
 343 } // namespace JSC
 344
 345 #endif // ENABLE(ASSEMBLER)
 346
 347 #endif // MacroAssembler_h