| | 1 | /* |
| | 2 | * Copyright (C) 2012 Apple Inc. All rights reserved. |
| | 3 | * |
| | 4 | * Redistribution and use in source and binary forms, with or without |
| | 5 | * modification, are permitted provided that the following conditions |
| | 6 | * are met: |
| | 7 | * 1. Redistributions of source code must retain the above copyright |
| | 8 | * notice, this list of conditions and the following disclaimer. |
| | 9 | * 2. Redistributions in binary form must reproduce the above copyright |
| | 10 | * notice, this list of conditions and the following disclaimer in the |
| | 11 | * documentation and/or other materials provided with the distribution. |
| | 12 | * |
| | 13 | * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY |
| | 14 | * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| | 15 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| | 16 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR |
| | 17 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| | 18 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| | 19 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
| | 20 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY |
| | 21 | * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| | 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| | 23 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| | 24 | */ |
| | 25 | |
| | 26 | #ifndef LLIntOfflineAsmConfig_h |
| | 27 | #define LLIntOfflineAsmConfig_h |
| | 28 | |
| | 29 | #include "LLIntCommon.h" |
| | 30 | #include <wtf/Assertions.h> |
| | 31 | #include <wtf/InlineASM.h> |
| | 32 | |
| | 33 | #if !ENABLE(JIT) |
| | 34 | #define OFFLINE_ASM_C_LOOP 1 |
| | 35 | #define OFFLINE_ASM_X86 0 |
| | 36 | #define OFFLINE_ASM_X86_WIN 0 |
| | 37 | #define OFFLINE_ASM_ARM 0 |
| | 38 | #define OFFLINE_ASM_ARMv7 0 |
| | 39 | #define OFFLINE_ASM_ARMv7_TRADITIONAL 0 |
| | 40 | #define OFFLINE_ASM_ARM64 0 |
| | 41 | #define OFFLINE_ASM_X86_64 0 |
| | 42 | #define OFFLINE_ASM_X86_64_WIN 0 |
| | 43 | #define OFFLINE_ASM_ARMv7k 0 |
| | 44 | #define OFFLINE_ASM_ARMv7s 0 |
| | 45 | #define OFFLINE_ASM_MIPS 0 |
| | 46 | #define OFFLINE_ASM_SH4 0 |
| | 47 | |
| | 48 | #else // ENABLE(JIT) |
| | 49 | |
| | 50 | #define OFFLINE_ASM_C_LOOP 0 |
| | 51 | |
| | 52 | #if CPU(X86) && !PLATFORM(WIN) |
| | 53 | #define OFFLINE_ASM_X86 1 |
| | 54 | #else |
| | 55 | #define OFFLINE_ASM_X86 0 |
| | 56 | #endif |
| | 57 | |
| | 58 | #if CPU(X86) && PLATFORM(WIN) |
| | 59 | #define OFFLINE_ASM_X86_WIN 1 |
| | 60 | #else |
| | 61 | #define OFFLINE_ASM_X86_WIN 0 |
| | 62 | #endif |
| | 63 | |
| | 64 | #ifdef __ARM_ARCH_7K__ |
| | 65 | #define OFFLINE_ASM_ARMv7k 1 |
| | 66 | #else |
| | 67 | #define OFFLINE_ASM_ARMv7k 0 |
| | 68 | #endif |
| | 69 | |
| | 70 | #ifdef __ARM_ARCH_7S__ |
| | 71 | #define OFFLINE_ASM_ARMv7s 1 |
| | 72 | #else |
| | 73 | #define OFFLINE_ASM_ARMv7s 0 |
| | 74 | #endif |
| | 75 | |
| | 76 | #if CPU(ARM_THUMB2) |
| | 77 | #define OFFLINE_ASM_ARMv7 1 |
| | 78 | #else |
| | 79 | #define OFFLINE_ASM_ARMv7 0 |
| | 80 | #endif |
| | 81 | |
| | 82 | #if CPU(ARM_TRADITIONAL) |
| | 83 | #if WTF_ARM_ARCH_AT_LEAST(7) |
| | 84 | #define OFFLINE_ASM_ARMv7_TRADITIONAL 1 |
| | 85 | #define OFFLINE_ASM_ARM 0 |
| | 86 | #else |
| | 87 | #define OFFLINE_ASM_ARM 1 |
| | 88 | #define OFFLINE_ASM_ARMv7_TRADITIONAL 0 |
| | 89 | #endif |
| | 90 | #else |
| | 91 | #define OFFLINE_ASM_ARMv7_TRADITIONAL 0 |
| | 92 | #define OFFLINE_ASM_ARM 0 |
| | 93 | #endif |
| | 94 | |
| | 95 | #if CPU(X86_64) && !PLATFORM(WIN) |
| | 96 | #define OFFLINE_ASM_X86_64 1 |
| | 97 | #else |
| | 98 | #define OFFLINE_ASM_X86_64 0 |
| | 99 | #endif |
| | 100 | |
| | 101 | #if CPU(X86_64) && PLATFORM(WIN) |
| | 102 | #define OFFLINE_ASM_X86_64_WIN 1 |
| | 103 | #else |
| | 104 | #define OFFLINE_ASM_X86_64_WIN 0 |
| | 105 | #endif |
| | 106 | |
| | 107 | #if CPU(MIPS) |
| | 108 | #define OFFLINE_ASM_MIPS 1 |
| | 109 | #else |
| | 110 | #define OFFLINE_ASM_MIPS 0 |
| | 111 | #endif |
| | 112 | |
| | 113 | #if CPU(SH4) |
| | 114 | #define OFFLINE_ASM_SH4 1 |
| | 115 | #else |
| | 116 | #define OFFLINE_ASM_SH4 0 |
| | 117 | #endif |
| | 118 | |
| | 119 | #if CPU(ARM64) |
| | 120 | #define OFFLINE_ASM_ARM64 1 |
| | 121 | #else |
| | 122 | #define OFFLINE_ASM_ARM64 0 |
| | 123 | #endif |
| | 124 | |
| | 125 | #if CPU(MIPS) |
| | 126 | #ifdef WTF_MIPS_PIC |
| | 127 | #define S(x) #x |
| | 128 | #define SX(x) S(x) |
| | 129 | #define OFFLINE_ASM_CPLOAD(reg) \ |
| | 130 | ".set noreorder\n" \ |
| | 131 | ".cpload " SX(reg) "\n" \ |
| | 132 | ".set reorder\n" |
| | 133 | #else |
| | 134 | #define OFFLINE_ASM_CPLOAD(reg) |
| | 135 | #endif |
| | 136 | #endif |
| | 137 | |
| | 138 | #endif // ENABLE(JIT) |
| | 139 | |
| | 140 | #if USE(JSVALUE64) |
| | 141 | #define OFFLINE_ASM_JSVALUE64 1 |
| | 142 | #else |
| | 143 | #define OFFLINE_ASM_JSVALUE64 0 |
| | 144 | #endif |
| | 145 | |
| | 146 | #if !ASSERT_DISABLED |
| | 147 | #define OFFLINE_ASM_ASSERT_ENABLED 1 |
| | 148 | #else |
| | 149 | #define OFFLINE_ASM_ASSERT_ENABLED 0 |
| | 150 | #endif |
| | 151 | |
| | 152 | #if CPU(BIG_ENDIAN) |
| | 153 | #define OFFLINE_ASM_BIG_ENDIAN 1 |
| | 154 | #else |
| | 155 | #define OFFLINE_ASM_BIG_ENDIAN 0 |
| | 156 | #endif |
| | 157 | |
| | 158 | #if LLINT_EXECUTION_TRACING |
| | 159 | #define OFFLINE_ASM_EXECUTION_TRACING 1 |
| | 160 | #else |
| | 161 | #define OFFLINE_ASM_EXECUTION_TRACING 0 |
| | 162 | #endif |
| | 163 | |
| | 164 | #if ENABLE(GGC) |
| | 165 | #define OFFLINE_ASM_GGC 1 |
| | 166 | #else |
| | 167 | #define OFFLINE_ASM_GGC 0 |
| | 168 | #endif |
| | 169 | |
| | 170 | #endif // LLIntOfflineAsmConfig_h |
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