projects / apple / javascriptcore.git / blame
| Commit | Line | Data |
|---|---|---|
| 81345200 A |
1 | /* |
| 2 | * Copyright (C) 2008, 2009, 2013 Apple Inc. All rights reserved. | |
| 3 | * Copyright (C) 2008 Cameron Zwarich <cwzwarich@uwaterloo.ca> | |
| 4 | * Copyright (C) Research In Motion Limited 2010, 2011. All rights reserved. | |
| 5 | * | |
| 6 | * Redistribution and use in source and binary forms, with or without | |
| 7 | * modification, are permitted provided that the following conditions | |
| 8 | * are met: | |
| 9 | * | |
| 10 | * 1. Redistributions of source code must retain the above copyright | |
| 11 | * notice, this list of conditions and the following disclaimer. | |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright | |
| 13 | * notice, this list of conditions and the following disclaimer in the | |
| 14 | * documentation and/or other materials provided with the distribution. | |
| 15 | * 3. Neither the name of Apple Inc. ("Apple") nor the names of | |
| 16 | * its contributors may be used to endorse or promote products derived | |
| 17 | * from this software without specific prior written permission. | |
| 18 | * | |
| 19 | * THIS SOFTWARE IS PROVIDED BY APPLE AND ITS CONTRIBUTORS "AS IS" AND ANY | |
| 20 | * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | |
| 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
| 22 | * DISCLAIMED. IN NO EVENT SHALL APPLE OR ITS CONTRIBUTORS BE LIABLE FOR ANY | |
| 23 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
| 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
| 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
| 26 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
| 28 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 29 | */ | |
| 30 | ||
| 31 | #ifndef JITStubsARMv7_h | |
| 32 | #define JITStubsARMv7_h | |
| 33 | ||
| 34 | #if !CPU(ARM_THUMB2) | |
| 35 | #error "JITStubsARMv7.h should only be #included if CPU(ARM_THUMB2)" | |
| 36 | #endif | |
| 37 | ||
| 38 | #if !USE(JSVALUE32_64) | |
| 39 | #error "JITStubsARMv7.h only implements USE(JSVALUE32_64)" | |
| 40 | #endif | |
| 41 | ||
| 42 | namespace JSC { | |
| 43 | ||
| 44 | #if COMPILER(GCC) | |
| 45 | ||
| 46 | #if USE(MASM_PROBE) | |
| 47 | // The following are offsets for MacroAssembler::ProbeContext fields accessed | |
| 48 | // by the ctiMasmProbeTrampoline stub. | |
| 49 | ||
| 50 | #define PTR_SIZE 4 | |
| 51 | #define PROBE_PROBE_FUNCTION_OFFSET (0 * PTR_SIZE) | |
| 52 | #define PROBE_ARG1_OFFSET (1 * PTR_SIZE) | |
| 53 | #define PROBE_ARG2_OFFSET (2 * PTR_SIZE) | |
| 54 | ||
| 55 | #define PROBE_FIRST_GPREG_OFFSET (3 * PTR_SIZE) | |
| 56 | ||
| 57 | #define GPREG_SIZE 4 | |
| 58 | #define PROBE_CPU_R0_OFFSET (PROBE_FIRST_GPREG_OFFSET + (0 * GPREG_SIZE)) | |
| 59 | #define PROBE_CPU_R1_OFFSET (PROBE_FIRST_GPREG_OFFSET + (1 * GPREG_SIZE)) | |
| 60 | #define PROBE_CPU_R2_OFFSET (PROBE_FIRST_GPREG_OFFSET + (2 * GPREG_SIZE)) | |
| 61 | #define PROBE_CPU_R3_OFFSET (PROBE_FIRST_GPREG_OFFSET + (3 * GPREG_SIZE)) | |
| 62 | #define PROBE_CPU_R4_OFFSET (PROBE_FIRST_GPREG_OFFSET + (4 * GPREG_SIZE)) | |
| 63 | #define PROBE_CPU_R5_OFFSET (PROBE_FIRST_GPREG_OFFSET + (5 * GPREG_SIZE)) | |
| 64 | #define PROBE_CPU_R6_OFFSET (PROBE_FIRST_GPREG_OFFSET + (6 * GPREG_SIZE)) | |
| 65 | #define PROBE_CPU_R7_OFFSET (PROBE_FIRST_GPREG_OFFSET + (7 * GPREG_SIZE)) | |
| 66 | #define PROBE_CPU_R8_OFFSET (PROBE_FIRST_GPREG_OFFSET + (8 * GPREG_SIZE)) | |
| 67 | #define PROBE_CPU_R9_OFFSET (PROBE_FIRST_GPREG_OFFSET + (9 * GPREG_SIZE)) | |
| 68 | #define PROBE_CPU_R10_OFFSET (PROBE_FIRST_GPREG_OFFSET + (10 * GPREG_SIZE)) | |
| 69 | #define PROBE_CPU_R11_OFFSET (PROBE_FIRST_GPREG_OFFSET + (11 * GPREG_SIZE)) | |
| 70 | #define PROBE_CPU_IP_OFFSET (PROBE_FIRST_GPREG_OFFSET + (12 * GPREG_SIZE)) | |
| 71 | #define PROBE_CPU_SP_OFFSET (PROBE_FIRST_GPREG_OFFSET + (13 * GPREG_SIZE)) | |
| 72 | #define PROBE_CPU_LR_OFFSET (PROBE_FIRST_GPREG_OFFSET + (14 * GPREG_SIZE)) | |
| 73 | #define PROBE_CPU_PC_OFFSET (PROBE_FIRST_GPREG_OFFSET + (15 * GPREG_SIZE)) | |
| 74 | ||
| 75 | #define PROBE_CPU_APSR_OFFSET (PROBE_FIRST_GPREG_OFFSET + (16 * GPREG_SIZE)) | |
| 76 | #define PROBE_CPU_FPSCR_OFFSET (PROBE_FIRST_GPREG_OFFSET + (17 * GPREG_SIZE)) | |
| 77 | ||
| 78 | #define PROBE_FIRST_FPREG_OFFSET (PROBE_FIRST_GPREG_OFFSET + (18 * GPREG_SIZE)) | |
| 79 | ||
| 80 | #define FPREG_SIZE 8 | |
| 81 | #define PROBE_CPU_D0_OFFSET (PROBE_FIRST_FPREG_OFFSET + (0 * FPREG_SIZE)) | |
| 82 | #define PROBE_CPU_D1_OFFSET (PROBE_FIRST_FPREG_OFFSET + (1 * FPREG_SIZE)) | |
| 83 | #define PROBE_CPU_D2_OFFSET (PROBE_FIRST_FPREG_OFFSET + (2 * FPREG_SIZE)) | |
| 84 | #define PROBE_CPU_D3_OFFSET (PROBE_FIRST_FPREG_OFFSET + (3 * FPREG_SIZE)) | |
| 85 | #define PROBE_CPU_D4_OFFSET (PROBE_FIRST_FPREG_OFFSET + (4 * FPREG_SIZE)) | |
| 86 | #define PROBE_CPU_D5_OFFSET (PROBE_FIRST_FPREG_OFFSET + (5 * FPREG_SIZE)) | |
| 87 | #define PROBE_CPU_D6_OFFSET (PROBE_FIRST_FPREG_OFFSET + (6 * FPREG_SIZE)) | |
| 88 | #define PROBE_CPU_D7_OFFSET (PROBE_FIRST_FPREG_OFFSET + (7 * FPREG_SIZE)) | |
| 89 | #define PROBE_CPU_D8_OFFSET (PROBE_FIRST_FPREG_OFFSET + (8 * FPREG_SIZE)) | |
| 90 | #define PROBE_CPU_D9_OFFSET (PROBE_FIRST_FPREG_OFFSET + (9 * FPREG_SIZE)) | |
| 91 | #define PROBE_CPU_D10_OFFSET (PROBE_FIRST_FPREG_OFFSET + (10 * FPREG_SIZE)) | |
| 92 | #define PROBE_CPU_D11_OFFSET (PROBE_FIRST_FPREG_OFFSET + (11 * FPREG_SIZE)) | |
| 93 | #define PROBE_CPU_D12_OFFSET (PROBE_FIRST_FPREG_OFFSET + (12 * FPREG_SIZE)) | |
| 94 | #define PROBE_CPU_D13_OFFSET (PROBE_FIRST_FPREG_OFFSET + (13 * FPREG_SIZE)) | |
| 95 | #define PROBE_CPU_D14_OFFSET (PROBE_FIRST_FPREG_OFFSET + (14 * FPREG_SIZE)) | |
| 96 | #define PROBE_CPU_D15_OFFSET (PROBE_FIRST_FPREG_OFFSET + (15 * FPREG_SIZE)) | |
| 97 | ||
| 98 | #if CPU(APPLE_ARMV7S) | |
| 99 | #define PROBE_CPU_D16_OFFSET (PROBE_FIRST_FPREG_OFFSET + (16 * FPREG_SIZE)) | |
| 100 | #define PROBE_CPU_D17_OFFSET (PROBE_FIRST_FPREG_OFFSET + (17 * FPREG_SIZE)) | |
| 101 | #define PROBE_CPU_D18_OFFSET (PROBE_FIRST_FPREG_OFFSET + (18 * FPREG_SIZE)) | |
| 102 | #define PROBE_CPU_D19_OFFSET (PROBE_FIRST_FPREG_OFFSET + (19 * FPREG_SIZE)) | |
| 103 | #define PROBE_CPU_D20_OFFSET (PROBE_FIRST_FPREG_OFFSET + (20 * FPREG_SIZE)) | |
| 104 | #define PROBE_CPU_D21_OFFSET (PROBE_FIRST_FPREG_OFFSET + (21 * FPREG_SIZE)) | |
| 105 | #define PROBE_CPU_D22_OFFSET (PROBE_FIRST_FPREG_OFFSET + (22 * FPREG_SIZE)) | |
| 106 | #define PROBE_CPU_D23_OFFSET (PROBE_FIRST_FPREG_OFFSET + (23 * FPREG_SIZE)) | |
| 107 | #define PROBE_CPU_D24_OFFSET (PROBE_FIRST_FPREG_OFFSET + (24 * FPREG_SIZE)) | |
| 108 | #define PROBE_CPU_D25_OFFSET (PROBE_FIRST_FPREG_OFFSET + (25 * FPREG_SIZE)) | |
| 109 | #define PROBE_CPU_D26_OFFSET (PROBE_FIRST_FPREG_OFFSET + (26 * FPREG_SIZE)) | |
| 110 | #define PROBE_CPU_D27_OFFSET (PROBE_FIRST_FPREG_OFFSET + (27 * FPREG_SIZE)) | |
| 111 | #define PROBE_CPU_D28_OFFSET (PROBE_FIRST_FPREG_OFFSET + (28 * FPREG_SIZE)) | |
| 112 | #define PROBE_CPU_D29_OFFSET (PROBE_FIRST_FPREG_OFFSET + (29 * FPREG_SIZE)) | |
| 113 | #define PROBE_CPU_D30_OFFSET (PROBE_FIRST_FPREG_OFFSET + (30 * FPREG_SIZE)) | |
| 114 | #define PROBE_CPU_D31_OFFSET (PROBE_FIRST_FPREG_OFFSET + (31 * FPREG_SIZE)) | |
| 115 | #define PROBE_SIZE (PROBE_FIRST_FPREG_OFFSET + (32 * FPREG_SIZE)) | |
| 116 | #else | |
| 117 | #define PROBE_SIZE (PROBE_FIRST_FPREG_OFFSET + (16 * FPREG_SIZE)) | |
| 118 | #endif // CPU(APPLE_ARMV7S) | |
| 119 | ||
| 120 | ||
| 121 | // These ASSERTs remind you that if you change the layout of ProbeContext, | |
| 122 | // you need to change ctiMasmProbeTrampoline offsets above to match. | |
| 123 | #define PROBE_OFFSETOF(x) offsetof(struct MacroAssembler::ProbeContext, x) | |
| 124 | COMPILE_ASSERT(PROBE_OFFSETOF(probeFunction) == PROBE_PROBE_FUNCTION_OFFSET, ProbeContext_probeFunction_offset_matches_ctiMasmProbeTrampoline); | |
| 125 | COMPILE_ASSERT(PROBE_OFFSETOF(arg1) == PROBE_ARG1_OFFSET, ProbeContext_arg1_offset_matches_ctiMasmProbeTrampoline); | |
| 126 | COMPILE_ASSERT(PROBE_OFFSETOF(arg2) == PROBE_ARG2_OFFSET, ProbeContext_arg2_offset_matches_ctiMasmProbeTrampoline); | |
| 127 | ||
| 128 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.r0) == PROBE_CPU_R0_OFFSET, ProbeContext_cpu_r0_offset_matches_ctiMasmProbeTrampoline); | |
| 129 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.r1) == PROBE_CPU_R1_OFFSET, ProbeContext_cpu_r1_offset_matches_ctiMasmProbeTrampoline); | |
| 130 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.r2) == PROBE_CPU_R2_OFFSET, ProbeContext_cpu_r2_offset_matches_ctiMasmProbeTrampoline); | |
| 131 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.r3) == PROBE_CPU_R3_OFFSET, ProbeContext_cpu_r3_offset_matches_ctiMasmProbeTrampoline); | |
| 132 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.r4) == PROBE_CPU_R4_OFFSET, ProbeContext_cpu_r4_offset_matches_ctiMasmProbeTrampoline); | |
| 133 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.r5) == PROBE_CPU_R5_OFFSET, ProbeContext_cpu_r5_offset_matches_ctiMasmProbeTrampoline); | |
| 134 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.r6) == PROBE_CPU_R6_OFFSET, ProbeContext_cpu_r6_offset_matches_ctiMasmProbeTrampoline); | |
| 135 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.r7) == PROBE_CPU_R7_OFFSET, ProbeContext_cpu_r70_offset_matches_ctiMasmProbeTrampoline); | |
| 136 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.r8) == PROBE_CPU_R8_OFFSET, ProbeContext_cpu_r8_offset_matches_ctiMasmProbeTrampoline); | |
| 137 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.r9) == PROBE_CPU_R9_OFFSET, ProbeContext_cpu_r9_offset_matches_ctiMasmProbeTrampoline); | |
| 138 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.r10) == PROBE_CPU_R10_OFFSET, ProbeContext_cpu_r10_offset_matches_ctiMasmProbeTrampoline); | |
| 139 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.r11) == PROBE_CPU_R11_OFFSET, ProbeContext_cpu_r11_offset_matches_ctiMasmProbeTrampoline); | |
| 140 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.ip) == PROBE_CPU_IP_OFFSET, ProbeContext_cpu_ip_offset_matches_ctiMasmProbeTrampoline); | |
| 141 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.sp) == PROBE_CPU_SP_OFFSET, ProbeContext_cpu_sp_offset_matches_ctiMasmProbeTrampoline); | |
| 142 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.lr) == PROBE_CPU_LR_OFFSET, ProbeContext_cpu_lr_offset_matches_ctiMasmProbeTrampoline); | |
| 143 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.pc) == PROBE_CPU_PC_OFFSET, ProbeContext_cpu_pc_offset_matches_ctiMasmProbeTrampoline); | |
| 144 | ||
| 145 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.apsr) == PROBE_CPU_APSR_OFFSET, ProbeContext_cpu_apsr_offset_matches_ctiMasmProbeTrampoline); | |
| 146 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.fpscr) == PROBE_CPU_FPSCR_OFFSET, ProbeContext_cpu_fpscr_offset_matches_ctiMasmProbeTrampoline); | |
| 147 | ||
| 148 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d0) == PROBE_CPU_D0_OFFSET, ProbeContext_cpu_d0_offset_matches_ctiMasmProbeTrampoline); | |
| 149 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d1) == PROBE_CPU_D1_OFFSET, ProbeContext_cpu_d1_offset_matches_ctiMasmProbeTrampoline); | |
| 150 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d2) == PROBE_CPU_D2_OFFSET, ProbeContext_cpu_d2_offset_matches_ctiMasmProbeTrampoline); | |
| 151 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d3) == PROBE_CPU_D3_OFFSET, ProbeContext_cpu_d3_offset_matches_ctiMasmProbeTrampoline); | |
| 152 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d4) == PROBE_CPU_D4_OFFSET, ProbeContext_cpu_d4_offset_matches_ctiMasmProbeTrampoline); | |
| 153 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d5) == PROBE_CPU_D5_OFFSET, ProbeContext_cpu_d5_offset_matches_ctiMasmProbeTrampoline); | |
| 154 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d6) == PROBE_CPU_D6_OFFSET, ProbeContext_cpu_d6_offset_matches_ctiMasmProbeTrampoline); | |
| 155 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d7) == PROBE_CPU_D7_OFFSET, ProbeContext_cpu_d7_offset_matches_ctiMasmProbeTrampoline); | |
| 156 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d8) == PROBE_CPU_D8_OFFSET, ProbeContext_cpu_d8_offset_matches_ctiMasmProbeTrampoline); | |
| 157 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d9) == PROBE_CPU_D9_OFFSET, ProbeContext_cpu_d9_offset_matches_ctiMasmProbeTrampoline); | |
| 158 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d10) == PROBE_CPU_D10_OFFSET, ProbeContext_cpu_d10_offset_matches_ctiMasmProbeTrampoline); | |
| 159 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d11) == PROBE_CPU_D11_OFFSET, ProbeContext_cpu_d11_offset_matches_ctiMasmProbeTrampoline); | |
| 160 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d12) == PROBE_CPU_D12_OFFSET, ProbeContext_cpu_d12_offset_matches_ctiMasmProbeTrampoline); | |
| 161 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d13) == PROBE_CPU_D13_OFFSET, ProbeContext_cpu_d13_offset_matches_ctiMasmProbeTrampoline); | |
| 162 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d14) == PROBE_CPU_D14_OFFSET, ProbeContext_cpu_d14_offset_matches_ctiMasmProbeTrampoline); | |
| 163 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d15) == PROBE_CPU_D15_OFFSET, ProbeContext_cpu_d15_offset_matches_ctiMasmProbeTrampoline); | |
| 164 | ||
| 165 | #if CPU(APPLE_ARMV7S) | |
| 166 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d16) == PROBE_CPU_D16_OFFSET, ProbeContext_cpu_d16_offset_matches_ctiMasmProbeTrampoline); | |
| 167 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d17) == PROBE_CPU_D17_OFFSET, ProbeContext_cpu_d17_offset_matches_ctiMasmProbeTrampoline); | |
| 168 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d18) == PROBE_CPU_D18_OFFSET, ProbeContext_cpu_d18_offset_matches_ctiMasmProbeTrampoline); | |
| 169 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d19) == PROBE_CPU_D19_OFFSET, ProbeContext_cpu_d19_offset_matches_ctiMasmProbeTrampoline); | |
| 170 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d20) == PROBE_CPU_D20_OFFSET, ProbeContext_cpu_d20_offset_matches_ctiMasmProbeTrampoline); | |
| 171 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d21) == PROBE_CPU_D21_OFFSET, ProbeContext_cpu_d21_offset_matches_ctiMasmProbeTrampoline); | |
| 172 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d22) == PROBE_CPU_D22_OFFSET, ProbeContext_cpu_d22_offset_matches_ctiMasmProbeTrampoline); | |
| 173 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d23) == PROBE_CPU_D23_OFFSET, ProbeContext_cpu_d23_offset_matches_ctiMasmProbeTrampoline); | |
| 174 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d24) == PROBE_CPU_D24_OFFSET, ProbeContext_cpu_d24_offset_matches_ctiMasmProbeTrampoline); | |
| 175 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d25) == PROBE_CPU_D25_OFFSET, ProbeContext_cpu_d25_offset_matches_ctiMasmProbeTrampoline); | |
| 176 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d26) == PROBE_CPU_D26_OFFSET, ProbeContext_cpu_d26_offset_matches_ctiMasmProbeTrampoline); | |
| 177 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d27) == PROBE_CPU_D27_OFFSET, ProbeContext_cpu_d27_offset_matches_ctiMasmProbeTrampoline); | |
| 178 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d28) == PROBE_CPU_D28_OFFSET, ProbeContext_cpu_d28_offset_matches_ctiMasmProbeTrampoline); | |
| 179 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d29) == PROBE_CPU_D29_OFFSET, ProbeContext_cpu_d29_offset_matches_ctiMasmProbeTrampoline); | |
| 180 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d30) == PROBE_CPU_D30_OFFSET, ProbeContext_cpu_d30_offset_matches_ctiMasmProbeTrampoline); | |
| 181 | COMPILE_ASSERT(PROBE_OFFSETOF(cpu.d31) == PROBE_CPU_D31_OFFSET, ProbeContext_cpu_d31_offset_matches_ctiMasmProbeTrampoline); | |
| 182 | #endif // CPU(APPLE_ARMV7S) | |
| 183 | ||
| 184 | COMPILE_ASSERT(sizeof(MacroAssembler::ProbeContext) == PROBE_SIZE, ProbeContext_size_matches_ctiMasmProbeTrampoline); | |
| 185 | ||
| 186 | #undef PROBE_OFFSETOF | |
| 187 | ||
| 188 | asm ( | |
| 189 | ".text" "\n" | |
| 190 | ".align 2" "\n" | |
| 191 | ".globl " SYMBOL_STRING(ctiMasmProbeTrampoline) "\n" | |
| 192 | HIDE_SYMBOL(ctiMasmProbeTrampoline) "\n" | |
| 193 | ".thumb" "\n" | |
| 194 | ".thumb_func " THUMB_FUNC_PARAM(ctiMasmProbeTrampoline) "\n" | |
| 195 | SYMBOL_STRING(ctiMasmProbeTrampoline) ":" "\n" | |
| 196 | ||
| 197 | // MacroAssembler::probe() has already generated code to store some values. | |
| 198 | // The top of stack now looks like this: | |
| 199 | // esp[0 * ptrSize]: probeFunction | |
| 200 | // esp[1 * ptrSize]: arg1 | |
| 201 | // esp[2 * ptrSize]: arg2 | |
| 202 | // esp[3 * ptrSize]: saved r0 | |
| 203 | // esp[4 * ptrSize]: saved ip | |
| 204 | // esp[5 * ptrSize]: saved lr | |
| 205 | // esp[6 * ptrSize]: saved sp | |
| 206 | ||
| 207 | "mov ip, sp" "\n" | |
| 208 | "mov r0, sp" "\n" | |
| 209 | "sub r0, r0, #" STRINGIZE_VALUE_OF(PROBE_SIZE) "\n" | |
| 210 | ||
| 211 | // The ARM EABI specifies that the stack needs to be 16 byte aligned. | |
| 212 | "bic r0, r0, #0xf" "\n" | |
| 213 | "mov sp, r0" "\n" | |
| 214 | ||
| 215 | "str lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_PC_OFFSET) "]" "\n" | |
| 216 | "add lr, sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_R1_OFFSET) "\n" | |
| 217 | "stmia lr, { r1-r11 }" "\n" | |
| 218 | "mrs lr, APSR" "\n" | |
| 219 | "str lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_APSR_OFFSET) "]" "\n" | |
| 220 | "vmrs lr, FPSCR" "\n" | |
| 221 | "str lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_FPSCR_OFFSET) "]" "\n" | |
| 222 | ||
| 223 | "ldr lr, [ip, #0 * " STRINGIZE_VALUE_OF(PTR_SIZE) "]" "\n" | |
| 224 | "str lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_PROBE_FUNCTION_OFFSET) "]" "\n" | |
| 225 | "ldr lr, [ip, #1 * " STRINGIZE_VALUE_OF(PTR_SIZE) "]" "\n" | |
| 226 | "str lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_ARG1_OFFSET) "]" "\n" | |
| 227 | "ldr lr, [ip, #2 * " STRINGIZE_VALUE_OF(PTR_SIZE) "]" "\n" | |
| 228 | "str lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_ARG2_OFFSET) "]" "\n" | |
| 229 | "ldr lr, [ip, #3 * " STRINGIZE_VALUE_OF(PTR_SIZE) "]" "\n" | |
| 230 | "str lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_R0_OFFSET) "]" "\n" | |
| 231 | "ldr lr, [ip, #4 * " STRINGIZE_VALUE_OF(PTR_SIZE) "]" "\n" | |
| 232 | "str lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_IP_OFFSET) "]" "\n" | |
| 233 | "ldr lr, [ip, #5 * " STRINGIZE_VALUE_OF(PTR_SIZE) "]" "\n" | |
| 234 | "str lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_LR_OFFSET) "]" "\n" | |
| 235 | "ldr lr, [ip, #6 * " STRINGIZE_VALUE_OF(PTR_SIZE) "]" "\n" | |
| 236 | "str lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_SP_OFFSET) "]" "\n" | |
| 237 | ||
| 238 | "ldr lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_PC_OFFSET) "]" "\n" | |
| 239 | ||
| 240 | "add ip, sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_D0_OFFSET) "\n" | |
| 241 | #if CPU(APPLE_ARMV7S) | |
| 242 | "vstmia.64 ip, { d0-d31 }" "\n" | |
| 243 | #else | |
| 244 | "vstmia.64 ip, { d0-d15 }" "\n" | |
| 245 | #endif | |
| 246 | ||
| 247 | "mov fp, sp" "\n" // Save the ProbeContext*. | |
| 248 | ||
| 249 | "ldr ip, [sp, #" STRINGIZE_VALUE_OF(PROBE_PROBE_FUNCTION_OFFSET) "]" "\n" | |
| 250 | "mov r0, sp" "\n" // the ProbeContext* arg. | |
| 251 | "blx ip" "\n" | |
| 252 | ||
| 253 | "mov sp, fp" "\n" | |
| 254 | ||
| 255 | // To enable probes to modify register state, we copy all registers | |
| 256 | // out of the ProbeContext before returning. | |
| 257 | ||
| 258 | #if CPU(APPLE_ARMV7S) | |
| 259 | "add ip, sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_D31_OFFSET + FPREG_SIZE) "\n" | |
| 260 | "vldmdb.64 ip!, { d0-d31 }" "\n" | |
| 261 | #else | |
| 262 | "add ip, sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_D15_OFFSET + FPREG_SIZE) "\n" | |
| 263 | "vldmdb.64 ip!, { d0-d15 }" "\n" | |
| 264 | #endif | |
| 265 | "add ip, sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_R11_OFFSET + GPREG_SIZE) "\n" | |
| 266 | "ldmdb ip, { r0-r11 }" "\n" | |
| 267 | "ldr ip, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_FPSCR_OFFSET) "]" "\n" | |
| 268 | "vmsr FPSCR, ip" "\n" | |
| 269 | ||
| 270 | // There are 5 more registers left to restore: ip, sp, lr, pc, and apsr. | |
| 271 | // There are 2 issues that complicate the restoration of these last few | |
| 272 | // registers: | |
| 273 | // | |
| 274 | // 1. Normal ARM calling convention relies on moving lr to pc to return to | |
| 275 | // the caller. In our case, the address to return to is specified by | |
| 276 | // ProbeContext.cpu.pc. And at that moment, we won't have any available | |
| 277 | // scratch registers to hold the return address (lr needs to hold | |
| 278 | // ProbeContext.cpu.lr, not the return address). | |
| 279 | // | |
| 280 | // The solution is to store the return address on the stack and load the | |
| 281 | // pc from there. | |
| 282 | // | |
| 283 | // 2. Issue 1 means we will need to write to the stack location at | |
| 284 | // ProbeContext.cpu.sp - 4. But if the user probe function had modified | |
| 285 | // the value of ProbeContext.cpu.sp to point in the range between | |
| 286 | // &ProbeContext.cpu.ip thru &ProbeContext.cpu.aspr, then the action for | |
| 287 | // Issue 1 may trash the values to be restored before we can restore | |
| 288 | // them. | |
| 289 | // | |
| 290 | // The solution is to check if ProbeContext.cpu.sp contains a value in | |
| 291 | // the undesirable range. If so, we copy the remaining ProbeContext | |
| 292 | // register data to a safe range (at memory lower than where | |
| 293 | // ProbeContext.cpu.sp points) first, and restore the remaining register | |
| 294 | // from this new range. | |
| 295 | ||
| 296 | "add ip, sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_APSR_OFFSET) "\n" | |
| 297 | "ldr lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_SP_OFFSET) "]" "\n" | |
| 298 | "cmp lr, ip" "\n" | |
| 299 | "it gt" "\n" | |
| 300 | "bgt " SYMBOL_STRING(ctiMasmProbeTrampolineEnd) "\n" | |
| 301 | ||
| 302 | // We get here because the new expected stack pointer location is lower | |
| 303 | // than where it's supposed to be. This means the safe range of stack | |
| 304 | // memory where we'll be copying the remaining register restore values to | |
| 305 | // might be in a region of memory below the sp i.e. unallocated stack | |
| 306 | // memory. This, in turn, makes it vulnerable to interrupts potentially | |
| 307 | // trashing the copied values. To prevent that, we must first allocate the | |
| 308 | // needed stack memory by adjusting the sp before the copying. | |
| 309 | ||
| 310 | "sub lr, lr, #(6 * " STRINGIZE_VALUE_OF(PTR_SIZE) | |
| 311 | " + " STRINGIZE_VALUE_OF(PROBE_CPU_IP_OFFSET) ")" "\n" | |
| 312 | ||
| 313 | "mov ip, sp" "\n" | |
| 314 | "mov sp, lr" "\n" | |
| 315 | "mov lr, ip" "\n" | |
| 316 | ||
| 317 | "ldr ip, [lr, #" STRINGIZE_VALUE_OF(PROBE_CPU_IP_OFFSET) "]" "\n" | |
| 318 | "str ip, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_IP_OFFSET) "]" "\n" | |
| 319 | "ldr ip, [lr, #" STRINGIZE_VALUE_OF(PROBE_CPU_SP_OFFSET) "]" "\n" | |
| 320 | "str ip, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_SP_OFFSET) "]" "\n" | |
| 321 | "ldr ip, [lr, #" STRINGIZE_VALUE_OF(PROBE_CPU_LR_OFFSET) "]" "\n" | |
| 322 | "str ip, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_LR_OFFSET) "]" "\n" | |
| 323 | "ldr ip, [lr, #" STRINGIZE_VALUE_OF(PROBE_CPU_PC_OFFSET) "]" "\n" | |
| 324 | "str ip, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_PC_OFFSET) "]" "\n" | |
| 325 | "ldr ip, [lr, #" STRINGIZE_VALUE_OF(PROBE_CPU_APSR_OFFSET) "]" "\n" | |
| 326 | "str ip, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_APSR_OFFSET) "]" "\n" | |
| 327 | ||
| 328 | ".thumb_func " THUMB_FUNC_PARAM(ctiMasmProbeTrampolineEnd) "\n" | |
| 329 | SYMBOL_STRING(ctiMasmProbeTrampolineEnd) ":" "\n" | |
| 330 | "ldr ip, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_PC_OFFSET) "]" "\n" | |
| 331 | "ldr lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_SP_OFFSET) "]" "\n" | |
| 332 | "sub lr, lr, #" STRINGIZE_VALUE_OF(PTR_SIZE) "\n" | |
| 333 | "str ip, [lr]" "\n" | |
| 334 | "str lr, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_SP_OFFSET) "]" "\n" | |
| 335 | ||
| 336 | "ldr ip, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_APSR_OFFSET) "]" "\n" | |
| 337 | "msr APSR, ip" "\n" | |
| 338 | "ldr ip, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_LR_OFFSET) "]" "\n" | |
| 339 | "mov lr, ip" "\n" | |
| 340 | "ldr ip, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_IP_OFFSET) "]" "\n" | |
| 341 | "ldr sp, [sp, #" STRINGIZE_VALUE_OF(PROBE_CPU_SP_OFFSET) "]" "\n" | |
| 342 | ||
| 343 | "pop { pc }" "\n" | |
| 344 | ); | |
| 345 | #endif // USE(MASM_PROBE) | |
| 346 | ||
| 347 | #endif // COMPILER(GCC) | |
| 348 | ||
| 349 | } // namespace JSC | |
| 350 | ||
| 351 | #endif // JITStubsARMv7_h |