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6fe7ccc8 A |
1 | /* |
2 | * Copyright (C) 2012 Apple Inc. All rights reserved. | |
3 | * | |
4 | * Redistribution and use in source and binary forms, with or without | |
5 | * modification, are permitted provided that the following conditions | |
6 | * are met: | |
7 | * 1. Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * 2. Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * | |
13 | * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY | |
14 | * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
15 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
16 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR | |
17 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
18 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
19 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
20 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY | |
21 | * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
23 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
24 | */ | |
25 | ||
26 | #ifndef LLIntOfflineAsmConfig_h | |
27 | #define LLIntOfflineAsmConfig_h | |
28 | ||
29 | #include "LLIntCommon.h" | |
30 | #include <wtf/Assertions.h> | |
31 | #include <wtf/InlineASM.h> | |
6fe7ccc8 | 32 | |
81345200 | 33 | #if !ENABLE(JIT) |
93a37866 A |
34 | #define OFFLINE_ASM_C_LOOP 1 |
35 | #define OFFLINE_ASM_X86 0 | |
81345200 | 36 | #define OFFLINE_ASM_X86_WIN 0 |
93a37866 A |
37 | #define OFFLINE_ASM_ARM 0 |
38 | #define OFFLINE_ASM_ARMv7 0 | |
39 | #define OFFLINE_ASM_ARMv7_TRADITIONAL 0 | |
81345200 | 40 | #define OFFLINE_ASM_ARM64 0 |
93a37866 | 41 | #define OFFLINE_ASM_X86_64 0 |
81345200 | 42 | #define OFFLINE_ASM_X86_64_WIN 0 |
93a37866 A |
43 | #define OFFLINE_ASM_ARMv7s 0 |
44 | #define OFFLINE_ASM_MIPS 0 | |
45 | #define OFFLINE_ASM_SH4 0 | |
46 | ||
81345200 | 47 | #else // ENABLE(JIT) |
93a37866 A |
48 | |
49 | #define OFFLINE_ASM_C_LOOP 0 | |
50 | ||
81345200 | 51 | #if CPU(X86) && !PLATFORM(WIN) |
6fe7ccc8 A |
52 | #define OFFLINE_ASM_X86 1 |
53 | #else | |
54 | #define OFFLINE_ASM_X86 0 | |
55 | #endif | |
56 | ||
81345200 A |
57 | #if CPU(X86) && PLATFORM(WIN) |
58 | #define OFFLINE_ASM_X86_WIN 1 | |
59 | #else | |
60 | #define OFFLINE_ASM_X86_WIN 0 | |
61 | #endif | |
62 | ||
93a37866 A |
63 | #ifdef __ARM_ARCH_7S__ |
64 | #define OFFLINE_ASM_ARMv7s 1 | |
65 | #else | |
66 | #define OFFLINE_ASM_ARMv7s 0 | |
67 | #endif | |
68 | ||
6fe7ccc8 A |
69 | #if CPU(ARM_THUMB2) |
70 | #define OFFLINE_ASM_ARMv7 1 | |
71 | #else | |
72 | #define OFFLINE_ASM_ARMv7 0 | |
73 | #endif | |
74 | ||
93a37866 A |
75 | #if CPU(ARM_TRADITIONAL) |
76 | #if WTF_ARM_ARCH_AT_LEAST(7) | |
77 | #define OFFLINE_ASM_ARMv7_TRADITIONAL 1 | |
78 | #define OFFLINE_ASM_ARM 0 | |
79 | #else | |
80 | #define OFFLINE_ASM_ARM 1 | |
81 | #define OFFLINE_ASM_ARMv7_TRADITIONAL 0 | |
82 | #endif | |
83 | #else | |
84 | #define OFFLINE_ASM_ARMv7_TRADITIONAL 0 | |
85 | #define OFFLINE_ASM_ARM 0 | |
86 | #endif | |
87 | ||
81345200 | 88 | #if CPU(X86_64) && !PLATFORM(WIN) |
6fe7ccc8 A |
89 | #define OFFLINE_ASM_X86_64 1 |
90 | #else | |
91 | #define OFFLINE_ASM_X86_64 0 | |
92 | #endif | |
93 | ||
81345200 A |
94 | #if CPU(X86_64) && PLATFORM(WIN) |
95 | #define OFFLINE_ASM_X86_64_WIN 1 | |
96 | #else | |
97 | #define OFFLINE_ASM_X86_64_WIN 0 | |
98 | #endif | |
99 | ||
93a37866 A |
100 | #if CPU(MIPS) |
101 | #define OFFLINE_ASM_MIPS 1 | |
102 | #else | |
103 | #define OFFLINE_ASM_MIPS 0 | |
104 | #endif | |
105 | ||
106 | #if CPU(SH4) | |
107 | #define OFFLINE_ASM_SH4 1 | |
108 | #else | |
109 | #define OFFLINE_ASM_SH4 0 | |
110 | #endif | |
111 | ||
93a37866 A |
112 | #if CPU(ARM64) |
113 | #define OFFLINE_ASM_ARM64 1 | |
114 | #else | |
115 | #define OFFLINE_ASM_ARM64 0 | |
116 | #endif | |
117 | ||
81345200 A |
118 | #if CPU(MIPS) |
119 | #ifdef WTF_MIPS_PIC | |
120 | #define S(x) #x | |
121 | #define SX(x) S(x) | |
122 | #define OFFLINE_ASM_CPLOAD(reg) \ | |
123 | ".set noreorder\n" \ | |
124 | ".cpload " SX(reg) "\n" \ | |
125 | ".set reorder\n" | |
126 | #else | |
127 | #define OFFLINE_ASM_CPLOAD(reg) | |
128 | #endif | |
129 | #endif | |
130 | ||
131 | #endif // ENABLE(JIT) | |
132 | ||
6fe7ccc8 A |
133 | #if USE(JSVALUE64) |
134 | #define OFFLINE_ASM_JSVALUE64 1 | |
135 | #else | |
136 | #define OFFLINE_ASM_JSVALUE64 0 | |
137 | #endif | |
138 | ||
139 | #if !ASSERT_DISABLED | |
140 | #define OFFLINE_ASM_ASSERT_ENABLED 1 | |
141 | #else | |
142 | #define OFFLINE_ASM_ASSERT_ENABLED 0 | |
143 | #endif | |
144 | ||
145 | #if CPU(BIG_ENDIAN) | |
146 | #define OFFLINE_ASM_BIG_ENDIAN 1 | |
147 | #else | |
148 | #define OFFLINE_ASM_BIG_ENDIAN 0 | |
149 | #endif | |
150 | ||
6fe7ccc8 A |
151 | #if LLINT_EXECUTION_TRACING |
152 | #define OFFLINE_ASM_EXECUTION_TRACING 1 | |
153 | #else | |
154 | #define OFFLINE_ASM_EXECUTION_TRACING 0 | |
155 | #endif | |
156 | ||
157 | #if LLINT_ALWAYS_ALLOCATE_SLOW | |
158 | #define OFFLINE_ASM_ALWAYS_ALLOCATE_SLOW 1 | |
159 | #else | |
160 | #define OFFLINE_ASM_ALWAYS_ALLOCATE_SLOW 0 | |
161 | #endif | |
162 | ||
81345200 A |
163 | #if ENABLE(GGC) |
164 | #define OFFLINE_ASM_GGC 1 | |
6fe7ccc8 | 165 | #else |
81345200 | 166 | #define OFFLINE_ASM_GGC 0 |
6fe7ccc8 A |
167 | #endif |
168 | ||
6fe7ccc8 | 169 | #endif // LLIntOfflineAsmConfig_h |