X-Git-Url: https://git.saurik.com/apple/xnu.git/blobdiff_plain/a3d08fcd5120d2aa8303b6349ca8b14e3f284af3..91447636331957f3d9b5ca5b508f07c526b0074d:/osfmk/ppc/commpage/cacheflush.s

diff --git a/osfmk/ppc/commpage/cacheflush.s b/osfmk/ppc/commpage/cacheflush.s
index 8b53f91e9..0b8cb48ae 100644
--- a/osfmk/ppc/commpage/cacheflush.s
+++ b/osfmk/ppc/commpage/cacheflush.s
@@ -28,19 +28,19 @@
 
         .text
         .align	2
-        .globl	EXT(commpage_flush_dcache)
-        .globl	EXT(commpage_flush_icache)
 
 
 // *********************************************
 // * C O M M P A G E _ F L U S H _ D C A C H E *
 // *********************************************
 //
+// Note that this routine is called both in 32 and 64-bit mode.
+//
 //	r3 = ptr to 1st byte to flush
 //	r4 = length to flush (may be 0)
 
 commpage_flush_dcache:
-        cmpwi	r4,0			// length 0?
+        mr.     r4,r4           // test length for 0 in mode-independent way
         lhz		r5,_COMM_PAGE_CACHE_LINESIZE(0)
         subi	r9,r5,1			// get (linesize-1)
         and		r0,r3,r9		// get offset within line of 1st byte
@@ -56,18 +56,20 @@ commpage_flush_dcache:
         sync					// make sure lines are flushed before we return
         blr
         
-        COMMPAGE_DESCRIPTOR(commpage_flush_dcache,_COMM_PAGE_FLUSH_DCACHE,0,0,0)	// matches all CPUs
+	COMMPAGE_DESCRIPTOR(commpage_flush_dcache,_COMM_PAGE_FLUSH_DCACHE,0,0,kCommPageBoth)
         
         
 // *********************************************
 // * C O M M P A G E _ F L U S H _ I C A C H E *
 // *********************************************
 //
+// Note that this routine is called both in 32 and 64-bit mode.
+//
 //	r3 = ptr to 1st byte to flush
 //	r4 = length to flush (may be 0)
 
 commpage_flush_icache:
-        cmpwi	r4,0			// length 0?
+        mr.     r4,r4           // test length for 0 in mode-independent way
         lhz		r5,_COMM_PAGE_CACHE_LINESIZE(0)
         subi	r9,r5,1			// get (linesize-1)
         and		r0,r3,r9		// get offset within line of 1st byte
@@ -88,10 +90,16 @@ commpage_flush_icache:
         icbi	0,r7
         add		r7,r7,r5
         bne		2b
+        
+        // The following sync is only needed on MP machines, probably only on
+        // 7400-family MP machines.  But because we're not certain of this, and
+        // this isn't a speed critical routine, we are conservative and always sync.
+        
+        sync					// wait until other processors see the icbi's
         isync					// make sure we haven't prefetched old instructions
         
         blr
 
-        COMMPAGE_DESCRIPTOR(commpage_flush_icache,_COMM_PAGE_FLUSH_ICACHE,0,0,0)	// matches all CPUs
+	COMMPAGE_DESCRIPTOR(commpage_flush_icache,_COMM_PAGE_FLUSH_ICACHE,0,0,kCommPageBoth)