X-Git-Url: https://git.saurik.com/apple/xnu.git/blobdiff_plain/89b3af67bb32e691275bf6fa803d1834b2284115..7e4a7d3939db04e70062ae6c7bf24b8c8b2f5a7c:/osfmk/i386/cpuid.c diff --git a/osfmk/i386/cpuid.c b/osfmk/i386/cpuid.c index 29d7ef51e..c247a157d 100644 --- a/osfmk/i386/cpuid.c +++ b/osfmk/i386/cpuid.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2000 Apple Computer, Inc. All rights reserved. + * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved. * * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ * @@ -30,11 +30,12 @@ */ #include #include +#include #include -#include "cpuid.h" +#include #if MACH_KDB -#include +#include #include #include #include @@ -47,289 +48,223 @@ #define min(a,b) ((a) < (b) ? (a) : (b)) #define quad(hi,lo) (((uint64_t)(hi)) << 32 | (lo)) -#define bit(n) (1UL << (n)) -#define bitmask(h,l) ((bit(h)|(bit(h)-1)) & ~(bit(l)-1)) -#define bitfield(x,h,l) (((x) & bitmask(h,l)) >> l) +/* Only for 32bit values */ +#define bit32(n) (1U << (n)) +#define bitmask32(h,l) ((bit32(h)|(bit32(h)-1)) & ~(bit32(l)-1)) +#define bitfield32(x,h,l) ((((x) & bitmask32(h,l)) >> l)) /* - * CPU identification routines. - * - * Note that this code assumes a processor that supports the - * 'cpuid' instruction. + * Leaf 2 cache descriptor encodings. */ +typedef enum { + _NULL_, /* NULL (empty) descriptor */ + CACHE, /* Cache */ + TLB, /* TLB */ + STLB, /* Shared second-level unified TLB */ + PREFETCH /* Prefetch size */ +} cpuid_leaf2_desc_type_t; + +typedef enum { + NA, /* Not Applicable */ + FULLY, /* Fully-associative */ + TRACE, /* Trace Cache (P4 only) */ + INST, /* Instruction TLB */ + DATA, /* Data TLB */ + DATA0, /* Data TLB, 1st level */ + DATA1, /* Data TLB, 2nd level */ + L1, /* L1 (unified) cache */ + L1_INST, /* L1 Instruction cache */ + L1_DATA, /* L1 Data cache */ + L2, /* L2 (unified) cache */ + L3, /* L3 (unified) cache */ + L2_2LINESECTOR, /* L2 (unified) cache with 2 lines per sector */ + L3_2LINESECTOR, /* L3(unified) cache with 2 lines per sector */ + SMALL, /* Small page TLB */ + LARGE, /* Large page TLB */ + BOTH /* Small and Large page TLB */ +} cpuid_leaf2_qualifier_t; + +typedef struct cpuid_cache_descriptor { + uint8_t value; /* descriptor code */ + uint8_t type; /* cpuid_leaf2_desc_type_t */ + uint8_t level; /* level of cache/TLB hierachy */ + uint8_t ways; /* wayness of cache */ + uint16_t size; /* cachesize or TLB pagesize */ + uint16_t entries; /* number of TLB entries or linesize */ +} cpuid_cache_descriptor_t; -static unsigned int cpuid_maxcpuid; - -static i386_cpu_info_t cpuid_cpu_info; - -uint32_t cpuid_feature; /* XXX obsolescent for compat */ +/* + * These multipliers are used to encode 1*K .. 64*M in a 16 bit size field + */ +#define K (1) +#define M (1024) /* - * We only identify Intel CPUs here. Adding support - * for others would be straightforward. + * Intel cache descriptor table: */ -static void set_cpu_generic(i386_cpu_info_t *); -static void set_cpu_intel(i386_cpu_info_t *); -static void set_cpu_amd(i386_cpu_info_t *); -static void set_cpu_nsc(i386_cpu_info_t *); -static void set_cpu_unknown(i386_cpu_info_t *); - -struct { - const char *vendor; - void (* func)(i386_cpu_info_t *); -} cpu_vendors[] = { - {CPUID_VID_INTEL, set_cpu_intel}, - {CPUID_VID_AMD, set_cpu_amd}, - {CPUID_VID_NSC, set_cpu_nsc}, - {0, set_cpu_unknown} +static cpuid_cache_descriptor_t intel_cpuid_leaf2_descriptor_table[] = { +// ------------------------------------------------------- +// value type level ways size entries +// ------------------------------------------------------- + { 0x00, _NULL_, NA, NA, NA, NA }, + { 0x01, TLB, INST, 4, SMALL, 32 }, + { 0x02, TLB, INST, FULLY, LARGE, 2 }, + { 0x03, TLB, DATA, 4, SMALL, 64 }, + { 0x04, TLB, DATA, 4, LARGE, 8 }, + { 0x05, TLB, DATA1, 4, LARGE, 32 }, + { 0x06, CACHE, L1_INST, 4, 8*K, 32 }, + { 0x08, CACHE, L1_INST, 4, 16*K, 32 }, + { 0x09, CACHE, L1_INST, 4, 32*K, 64 }, + { 0x0A, CACHE, L1_DATA, 2, 8*K, 32 }, + { 0x0B, TLB, INST, 4, LARGE, 4 }, + { 0x0C, CACHE, L1_DATA, 4, 16*K, 32 }, + { 0x0D, CACHE, L1_DATA, 4, 16*K, 64 }, + { 0x0E, CACHE, L1_DATA, 6, 24*K, 64 }, + { 0x21, CACHE, L2, 8, 256*K, 64 }, + { 0x22, CACHE, L3_2LINESECTOR, 4, 512*K, 64 }, + { 0x23, CACHE, L3_2LINESECTOR, 8, 1*M, 64 }, + { 0x25, CACHE, L3_2LINESECTOR, 8, 2*M, 64 }, + { 0x29, CACHE, L3_2LINESECTOR, 8, 4*M, 64 }, + { 0x2C, CACHE, L1_DATA, 8, 32*K, 64 }, + { 0x30, CACHE, L1_INST, 8, 32*K, 64 }, + { 0x40, CACHE, L2, NA, 0, NA }, + { 0x41, CACHE, L2, 4, 128*K, 32 }, + { 0x42, CACHE, L2, 4, 256*K, 32 }, + { 0x43, CACHE, L2, 4, 512*K, 32 }, + { 0x44, CACHE, L2, 4, 1*M, 32 }, + { 0x45, CACHE, L2, 4, 2*M, 32 }, + { 0x46, CACHE, L3, 4, 4*M, 64 }, + { 0x47, CACHE, L3, 8, 8*M, 64 }, + { 0x48, CACHE, L2, 12, 3*M, 64 }, + { 0x49, CACHE, L2, 16, 4*M, 64 }, + { 0x4A, CACHE, L3, 12, 6*M, 64 }, + { 0x4B, CACHE, L3, 16, 8*M, 64 }, + { 0x4C, CACHE, L3, 12, 12*M, 64 }, + { 0x4D, CACHE, L3, 16, 16*M, 64 }, + { 0x4E, CACHE, L2, 24, 6*M, 64 }, + { 0x4F, TLB, INST, NA, SMALL, 32 }, + { 0x50, TLB, INST, NA, BOTH, 64 }, + { 0x51, TLB, INST, NA, BOTH, 128 }, + { 0x52, TLB, INST, NA, BOTH, 256 }, + { 0x55, TLB, INST, FULLY, BOTH, 7 }, + { 0x56, TLB, DATA0, 4, LARGE, 16 }, + { 0x57, TLB, DATA0, 4, SMALL, 16 }, + { 0x59, TLB, DATA0, FULLY, SMALL, 16 }, + { 0x5A, TLB, DATA0, 4, LARGE, 32 }, + { 0x5B, TLB, DATA, NA, BOTH, 64 }, + { 0x5C, TLB, DATA, NA, BOTH, 128 }, + { 0x5D, TLB, DATA, NA, BOTH, 256 }, + { 0x60, CACHE, L1, 16*K, 8, 64 }, + { 0x61, CACHE, L1, 4, 8*K, 64 }, + { 0x62, CACHE, L1, 4, 16*K, 64 }, + { 0x63, CACHE, L1, 4, 32*K, 64 }, + { 0x70, CACHE, TRACE, 8, 12*K, NA }, + { 0x71, CACHE, TRACE, 8, 16*K, NA }, + { 0x72, CACHE, TRACE, 8, 32*K, NA }, + { 0x78, CACHE, L2, 4, 1*M, 64 }, + { 0x79, CACHE, L2_2LINESECTOR, 8, 128*K, 64 }, + { 0x7A, CACHE, L2_2LINESECTOR, 8, 256*K, 64 }, + { 0x7B, CACHE, L2_2LINESECTOR, 8, 512*K, 64 }, + { 0x7C, CACHE, L2_2LINESECTOR, 8, 1*M, 64 }, + { 0x7D, CACHE, L2, 8, 2*M, 64 }, + { 0x7F, CACHE, L2, 2, 512*K, 64 }, + { 0x80, CACHE, L2, 8, 512*K, 64 }, + { 0x82, CACHE, L2, 8, 256*K, 32 }, + { 0x83, CACHE, L2, 8, 512*K, 32 }, + { 0x84, CACHE, L2, 8, 1*M, 32 }, + { 0x85, CACHE, L2, 8, 2*M, 32 }, + { 0x86, CACHE, L2, 4, 512*K, 64 }, + { 0x87, CACHE, L2, 8, 1*M, 64 }, + { 0xB0, TLB, INST, 4, SMALL, 128 }, + { 0xB1, TLB, INST, 4, LARGE, 8 }, + { 0xB2, TLB, INST, 4, SMALL, 64 }, + { 0xB3, TLB, DATA, 4, SMALL, 128 }, + { 0xB4, TLB, DATA1, 4, SMALL, 256 }, + { 0xBA, TLB, DATA1, 4, BOTH, 64 }, + { 0xCA, STLB, DATA1, 4, BOTH, 512 }, + { 0xD0, CACHE, L3, 4, 512*K, 64 }, + { 0xD1, CACHE, L3, 4, 1*M, 64 }, + { 0xD2, CACHE, L3, 4, 2*M, 64 }, + { 0xD3, CACHE, L3, 4, 4*M, 64 }, + { 0xD4, CACHE, L3, 4, 8*M, 64 }, + { 0xD6, CACHE, L3, 8, 1*M, 64 }, + { 0xD7, CACHE, L3, 8, 2*M, 64 }, + { 0xD8, CACHE, L3, 8, 4*M, 64 }, + { 0xD9, CACHE, L3, 8, 8*M, 64 }, + { 0xDA, CACHE, L3, 8, 12*M, 64 }, + { 0xDC, CACHE, L3, 12, 1536*K, 64 }, + { 0xDD, CACHE, L3, 12, 3*M, 64 }, + { 0xDE, CACHE, L3, 12, 6*M, 64 }, + { 0xDF, CACHE, L3, 12, 12*M, 64 }, + { 0xE0, CACHE, L3, 12, 18*M, 64 }, + { 0xE2, CACHE, L3, 16, 2*M, 64 }, + { 0xE3, CACHE, L3, 16, 4*M, 64 }, + { 0xE4, CACHE, L3, 16, 8*M, 64 }, + { 0xE5, CACHE, L3, 16, 16*M, 64 }, + { 0xE6, CACHE, L3, 16, 24*M, 64 }, + { 0xF0, PREFETCH, NA, NA, 64, NA }, + { 0xF1, PREFETCH, NA, NA, 128, NA } }; +#define INTEL_LEAF2_DESC_NUM (sizeof(intel_cpuid_leaf2_descriptor_table) / \ + sizeof(cpuid_cache_descriptor_t)) -void -cpuid_get_info(i386_cpu_info_t *info_p) +static inline cpuid_cache_descriptor_t * +cpuid_leaf2_find(uint8_t value) { - uint32_t cpuid_result[4]; - int i; - - bzero((void *)info_p, sizeof(i386_cpu_info_t)); - - /* do cpuid 0 to get vendor */ - do_cpuid(0, cpuid_result); - cpuid_maxcpuid = cpuid_result[eax]; - bcopy((char *)&cpuid_result[ebx], &info_p->cpuid_vendor[0], 4); /* ug */ - bcopy((char *)&cpuid_result[ecx], &info_p->cpuid_vendor[8], 4); - bcopy((char *)&cpuid_result[edx], &info_p->cpuid_vendor[4], 4); - info_p->cpuid_vendor[12] = 0; + unsigned int i; - /* look up vendor */ - for (i = 0; ; i++) { - if ((cpu_vendors[i].vendor == 0) || - (!strcmp(cpu_vendors[i].vendor, info_p->cpuid_vendor))) { - cpu_vendors[i].func(info_p); - break; - } - } + for (i = 0; i < INTEL_LEAF2_DESC_NUM; i++) + if (intel_cpuid_leaf2_descriptor_table[i].value == value) + return &intel_cpuid_leaf2_descriptor_table[i]; + return NULL; } /* - * Cache descriptor table. Each row has the form: - * (descriptor_value, cache, size, linesize, - * description) - * Note: the CACHE_DESC macro does not expand description text in the kernel. + * CPU identification routines. */ -static cpuid_cache_desc_t cpuid_cache_desc_tab[] = { -CACHE_DESC(CPUID_CACHE_ITLB_4K, Lnone, 0, 0, \ - "Instruction TLB, 4K, pages 4-way set associative, 64 entries"), -CACHE_DESC(CPUID_CACHE_ITLB_4M, Lnone, 0, 0, \ - "Instruction TLB, 4M, pages 4-way set associative, 2 entries"), -CACHE_DESC(CPUID_CACHE_DTLB_4K, Lnone, 0, 0, \ - "Data TLB, 4K pages, 4-way set associative, 64 entries"), -CACHE_DESC(CPUID_CACHE_DTLB_4M, Lnone, 0, 0, \ - "Data TLB, 4M pages, 4-way set associative, 8 entries"), -CACHE_DESC(CPUID_CACHE_ITLB_64, Lnone, 0, 0, \ - "Instruction TLB, 4K and 2M or 4M pages, 64 entries"), -CACHE_DESC(CPUID_CACHE_ITLB_128, Lnone, 0, 0, \ - "Instruction TLB, 4K and 2M or 4M pages, 128 entries"), -CACHE_DESC(CPUID_CACHE_ITLB_256, Lnone, 0, 0, \ - "Instruction TLB, 4K and 2M or 4M pages, 256 entries"), -CACHE_DESC(CPUID_CACHE_DTLB_64, Lnone, 0, 0, \ - "Data TLB, 4K and 4M pages, 64 entries"), -CACHE_DESC(CPUID_CACHE_DTLB_128, Lnone, 0, 0, \ - "Data TLB, 4K and 4M pages, 128 entries"), -CACHE_DESC(CPUID_CACHE_DTLB_256, Lnone, 0, 0, \ - "Data TLB, 4K and 4M pages, 256 entries"), -CACHE_DESC(CPUID_CACHE_ITLB_128_4, Lnone, 0, 0, \ - "Instruction TLB, 4K pages, 4-way set associative, 128 entries"), -CACHE_DESC(CPUID_CACHE_DTLB_128_4, Lnone, 0, 0, \ - "Data TLB, 4K pages, 4-way set associative, 128 entries"), -CACHE_DESC(CPUID_CACHE_ICACHE_8K, L1I, 8*1024, 32, \ - "Instruction L1 cache, 8K, 4-way set associative, 32byte line size"), -CACHE_DESC(CPUID_CACHE_DCACHE_8K, L1D, 8*1024, 32, \ - "Data L1 cache, 8K, 2-way set associative, 32byte line size"), -CACHE_DESC(CPUID_CACHE_ICACHE_16K, L1I, 16*1024, 32, \ - "Instruction L1 cache, 16K, 4-way set associative, 32byte line size"), -CACHE_DESC(CPUID_CACHE_DCACHE_16K, L1D, 16*1024, 32, \ - "Data L1 cache, 16K, 4-way set associative, 32byte line size"), -CACHE_DESC(CPUID_CACHE_DCACHE_8K_64, L1D, 8*1024, 64, \ - "Data L1 cache, 8K, 4-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_DCACHE_16K_64, L1D, 16*1024, 64, \ - "Data L1 cache, 16K, 4-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_DCACHE_32K_64, L1D, 32*1024, 64, \ - "Data L1 cache, 32K, 4-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_DCACHE_32K, L1D, 32*1024, 64, \ - "Data L1 cache, 32K, 8-way set assocative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_ICACHE_32K, L1I, 32*1024, 64, \ - "Instruction L1 cache, 32K, 8-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_DCACHE_16K_8, L1D, 16*1024, 64, \ - "Data L1 cache, 16K, 8-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_TRACE_12K, L1I, 12*1024, 64, \ - "Trace cache, 12K-uop, 8-way set associative"), -CACHE_DESC(CPUID_CACHE_TRACE_16K, L1I, 16*1024, 64, \ - "Trace cache, 16K-uop, 8-way set associative"), -CACHE_DESC(CPUID_CACHE_TRACE_32K, L1I, 32*1024, 64, \ - "Trace cache, 32K-uop, 8-way set associative"), -CACHE_DESC(CPUID_CACHE_UCACHE_128K, L2U, 128*1024, 32, \ - "Unified L2 cache, 128K, 4-way set associative, 32byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_256K, L2U, 128*1024, 32, \ - "Unified L2 cache, 256K, 4-way set associative, 32byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_512K, L2U, 512*1024, 32, \ - "Unified L2 cache, 512K, 4-way set associative, 32byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_1M, L2U, 1*1024*1024, 32, \ - "Unified L2 cache, 1M, 4-way set associative, 32byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_2M, L2U, 2*1024*1024, 32, \ - "Unified L2 cache, 2M, 4-way set associative, 32byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_4M, L2U, 4*1024*1024, 64, \ - "Unified L2 cache, 4M, 16-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_128K_64, L2U, 128*1024, 64, \ - "Unified L2 cache, 128K, 8-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_256K_64, L2U, 256*1024, 64, \ - "Unified L2 cache, 256K, 8-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_512K_64, L2U, 512*1024, 64, \ - "Unified L2 cache, 512K, 8-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_1M_64, L2U, 1*1024*1024, 64, \ - "Unified L2 cache, 1M, 8-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_256K_32, L2U, 256*1024, 32, \ - "Unified L2 cache, 256K, 8-way set associative, 32byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_512K_32, L2U, 512*1024, 32, \ - "Unified L2 cache, 512K, 8-way set associative, 32byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_1M_32, L2U, 1*1024*1024, 32, \ - "Unified L2 cache, 1M, 8-way set associative, 32byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_2M_32, L2U, 2*1024*1024, 32, \ - "Unified L2 cache, 2M, 8-way set associative, 32byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_1M_64_4, L2U, 1*1024*1024, 64, \ - "Unified L2 cache, 1M, 4-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_2M_64, L2U, 2*1024*1024, 64, \ - "Unified L2 cache, 2M, 8-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_512K_64_2,L2U, 512*1024, 64, \ - "Unified L2 cache, 512K, 2-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_512K_64_4,L2U, 512*1024, 64, \ - "Unified L2 cache, 512K, 4-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_1M_64_8, L2U, 1*1024*1024, 64, \ - "Unified L2 cache, 1M, 8-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_128K_S4, L2U, 128*1024, 64, \ - "Unified L2 sectored cache, 128K, 4-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_128K_S2, L2U, 128*1024, 64, \ - "Unified L2 sectored cache, 128K, 2-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_UCACHE_256K_S4, L2U, 256*1024, 64, \ - "Unified L2 sectored cache, 256K, 4-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_L3CACHE_512K, L3U, 512*1024, 64, \ - "Unified L3 cache, 512K, 4-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_L3CACHE_1M, L3U, 1*1024*1024, 64, \ - "Unified L3 cache, 1M, 8-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_L3CACHE_2M, L3U, 2*1024*1024, 64, \ - "Unified L3 cache, 2M, 8-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_L3CACHE_4M, L3U, 4*1024*1024, 64, \ - "Unified L3 cache, 4M, 8-way set associative, 64byte line size"), -CACHE_DESC(CPUID_CACHE_PREFETCH_64, Lnone, 0, 0, \ - "64-Byte Prefetching"), -CACHE_DESC(CPUID_CACHE_PREFETCH_128, Lnone, 0, 0, \ - "128-Byte Prefetching"), -CACHE_DESC(CPUID_CACHE_NOCACHE, Lnone, 0, 0, \ - "No L2 cache or, if valid L2 cache, no L3 cache"), -CACHE_DESC(CPUID_CACHE_NULL, Lnone, 0, 0, \ - (char *)0), -}; -static const char * get_intel_model_string( i386_cpu_info_t * info_p, cpu_type_t* type, cpu_subtype_t* subtype) +static i386_cpu_info_t *cpuid_cpu_infop = NULL; +static i386_cpu_info_t cpuid_cpu_info; + +#if defined(__x86_64__) +static void cpuid_fn(uint32_t selector, uint32_t *result) { - *type = CPU_TYPE_X86; - *subtype = CPU_SUBTYPE_X86_ARCH1; - - /* check for brand id string */ - switch(info_p->cpuid_brand) { - case CPUID_BRAND_UNSUPPORTED: - /* brand ID not supported; use alternate method. */ - switch(info_p->cpuid_family) { - case CPUID_FAMILY_486: - return "Intel 486"; - case CPUID_FAMILY_586: - return "Intel Pentium"; - case CPUID_FAMILY_686: - switch(info_p->cpuid_model) { - case CPUID_MODEL_P6: - return "Intel Pentium Pro"; - case CPUID_MODEL_PII: - return "Intel Pentium II"; - case CPUID_MODEL_P65: - case CPUID_MODEL_P66: - return "Intel Celeron"; - case CPUID_MODEL_P67: - case CPUID_MODEL_P68: - case CPUID_MODEL_P6A: - case CPUID_MODEL_P6B: - return "Intel Pentium III"; - case CPUID_MODEL_PM9: - case CPUID_MODEL_PMD: - return "Intel Pentium M"; - default: - return "Unknown Intel P6 Family"; - } - case CPUID_FAMILY_EXTENDED: - switch (info_p->cpuid_extfamily) { - case CPUID_EXTFAMILY_PENTIUM4: - *subtype = CPU_SUBTYPE_PENTIUM_4; - return "Intel Pentium 4"; - default: - return "Unknown Intel Extended Family"; - } - default: - return "Unknown Intel Family"; - } - break; - case CPUID_BRAND_CELERON_1: - case CPUID_BRAND_CELERON_A: - case CPUID_BRAND_CELERON_14: - return "Intel Celeron"; - case CPUID_BRAND_PENTIUM_III_2: - case CPUID_BRAND_PENTIUM_III_4: - return "Pentium III"; - case CPUID_BRAND_PIII_XEON: - if (info_p->cpuid_signature == 0x6B1) { - return "Intel Celeron"; - } else { - return "Intel Pentium III Xeon"; - } - case CPUID_BRAND_PENTIUM_III_M: - return "Mobile Intel Pentium III-M"; - case CPUID_BRAND_M_CELERON_7: - case CPUID_BRAND_M_CELERON_F: - case CPUID_BRAND_M_CELERON_13: - case CPUID_BRAND_M_CELERON_17: - return "Mobile Intel Celeron"; - case CPUID_BRAND_PENTIUM4_8: - case CPUID_BRAND_PENTIUM4_9: - *subtype = CPU_SUBTYPE_PENTIUM_4; - return "Intel Pentium 4"; - case CPUID_BRAND_XEON: - return "Intel Xeon"; - case CPUID_BRAND_XEON_MP: - return "Intel Xeon MP"; - case CPUID_BRAND_PENTIUM4_M: - if (info_p->cpuid_signature == 0xF13) { - return "Intel Xeon"; - } else { - *subtype = CPU_SUBTYPE_PENTIUM_4; - return "Mobile Intel Pentium 4"; - } - case CPUID_BRAND_CELERON_M: - return "Intel Celeron M"; - case CPUID_BRAND_PENTIUM_M: - return "Intel Pentium M"; - case CPUID_BRAND_MOBILE_15: - case CPUID_BRAND_MOBILE_17: - return "Mobile Intel"; - } - return "Unknown Intel"; + do_cpuid(selector, result); +} +#else +static void cpuid_fn(uint32_t selector, uint32_t *result) +{ + if (cpu_mode_is64bit()) { + asm("call _cpuid64" + : "=a" (result[0]), + "=b" (result[1]), + "=c" (result[2]), + "=d" (result[3]) + : "a"(selector)); + } else { + do_cpuid(selector, result); + } } +#endif -static void set_intel_cache_info( i386_cpu_info_t * info_p ) +/* this function is Intel-specific */ +static void +cpuid_set_cache_info( i386_cpu_info_t * info_p ) { uint32_t cpuid_result[4]; - uint32_t l1d_cache_linesize = 0; + uint32_t reg[4]; + uint32_t index; + uint32_t linesizes[LCACHE_MAX]; unsigned int i; unsigned int j; + boolean_t cpuid_deterministic_supported = FALSE; - /* get processor cache descriptor info */ - do_cpuid(2, cpuid_result); + bzero( linesizes, sizeof(linesizes) ); + + /* Get processor cache descriptor info using leaf 2. We don't use + * this internally, but must publish it for KEXTs. + */ + cpuid_fn(2, cpuid_result); for (j = 0; j < 4; j++) { if ((cpuid_result[j] >> 31) == 1) /* bit31 is validity */ continue; @@ -339,7 +274,7 @@ static void set_intel_cache_info( i386_cpu_info_t * info_p ) for (i = 1; i < info_p->cache_info[0]; i++) { if (i*16 > sizeof(info_p->cache_info)) break; - do_cpuid(2, cpuid_result); + cpuid_fn(2, cpuid_result); for (j = 0; j < 4; j++) { if ((cpuid_result[j] >> 31) == 1) continue; @@ -348,290 +283,395 @@ static void set_intel_cache_info( i386_cpu_info_t * info_p ) } } - /* decode the descriptors looking for L1/L2/L3 size info */ - for (i = 1; i < sizeof(info_p->cache_info); i++) { - cpuid_cache_desc_t *descp; - uint8_t desc = info_p->cache_info[i]; - - if (desc == CPUID_CACHE_NULL) - continue; - for (descp = cpuid_cache_desc_tab; - descp->value != CPUID_CACHE_NULL; descp++) { - if (descp->value != desc) - continue; - info_p->cache_size[descp->type] = descp->size; - if (descp->type == L2U) - info_p->cache_linesize = descp->linesize; - if (descp->type == L1D) - l1d_cache_linesize = descp->linesize; + /* + * Get cache info using leaf 4, the "deterministic cache parameters." + * Most processors Mac OS X supports implement this flavor of CPUID. + * Loop over each cache on the processor. + */ + cpuid_fn(0, cpuid_result); + if (cpuid_result[eax] >= 4) + cpuid_deterministic_supported = TRUE; + + for (index = 0; cpuid_deterministic_supported; index++) { + cache_type_t type = Lnone; + uint32_t cache_type; + uint32_t cache_level; + uint32_t cache_sharing; + uint32_t cache_linesize; + uint32_t cache_sets; + uint32_t cache_associativity; + uint32_t cache_size; + uint32_t cache_partitions; + uint32_t colors; + + reg[eax] = 4; /* cpuid request 4 */ + reg[ecx] = index; /* index starting at 0 */ + cpuid(reg); +//kprintf("cpuid(4) index=%d eax=%p\n", index, reg[eax]); + cache_type = bitfield32(reg[eax], 4, 0); + if (cache_type == 0) + break; /* no more caches */ + cache_level = bitfield32(reg[eax], 7, 5); + cache_sharing = bitfield32(reg[eax], 25, 14) + 1; + info_p->cpuid_cores_per_package + = bitfield32(reg[eax], 31, 26) + 1; + cache_linesize = bitfield32(reg[ebx], 11, 0) + 1; + cache_partitions = bitfield32(reg[ebx], 21, 12) + 1; + cache_associativity = bitfield32(reg[ebx], 31, 22) + 1; + cache_sets = bitfield32(reg[ecx], 31, 0) + 1; + + /* Map type/levels returned by CPUID into cache_type_t */ + switch (cache_level) { + case 1: + type = cache_type == 1 ? L1D : + cache_type == 2 ? L1I : + Lnone; + break; + case 2: + type = cache_type == 3 ? L2U : + Lnone; + break; + case 3: + type = cache_type == 3 ? L3U : + Lnone; break; + default: + type = Lnone; } + + /* The total size of a cache is: + * ( linesize * sets * associativity * partitions ) + */ + if (type != Lnone) { + cache_size = cache_linesize * cache_sets * + cache_associativity * cache_partitions; + info_p->cache_size[type] = cache_size; + info_p->cache_sharing[type] = cache_sharing; + info_p->cache_partitions[type] = cache_partitions; + linesizes[type] = cache_linesize; + + /* Compute the number of page colors for this cache, + * which is: + * ( linesize * sets ) / page_size + * + * To help visualize this, consider two views of a + * physical address. To the cache, it is composed + * of a line offset, a set selector, and a tag. + * To VM, it is composed of a page offset, a page + * color, and other bits in the pageframe number: + * + * +-----------------+---------+--------+ + * cache: | tag | set | offset | + * +-----------------+---------+--------+ + * + * +-----------------+-------+----------+ + * VM: | don't care | color | pg offset| + * +-----------------+-------+----------+ + * + * The color is those bits in (set+offset) not covered + * by the page offset. + */ + colors = ( cache_linesize * cache_sets ) >> 12; + + if ( colors > vm_cache_geometry_colors ) + vm_cache_geometry_colors = colors; + } + } + + /* + * If deterministic cache parameters are not available, use + * something else + */ + if (info_p->cpuid_cores_per_package == 0) { + info_p->cpuid_cores_per_package = 1; + + /* cpuid define in 1024 quantities */ + info_p->cache_size[L2U] = info_p->cpuid_cache_size * 1024; + info_p->cache_sharing[L2U] = 1; + info_p->cache_partitions[L2U] = 1; + + linesizes[L2U] = info_p->cpuid_cache_linesize; } - /* For P-IIIs, L2 could be 256k or 512k but we can't tell */ - if (info_p->cache_size[L2U] == 0 && - info_p->cpuid_family == 0x6 && info_p->cpuid_model == 0xb) { - info_p->cache_size[L2U] = 256*1024; - info_p->cache_linesize = 32; - } - /* If we have no L2 cache, use the L1 data cache line size */ - if (info_p->cache_size[L2U] == 0) - info_p->cache_linesize = l1d_cache_linesize; + + /* + * What linesize to publish? We use the L2 linesize if any, + * else the L1D. + */ + if ( linesizes[L2U] ) + info_p->cache_linesize = linesizes[L2U]; + else if (linesizes[L1D]) + info_p->cache_linesize = linesizes[L1D]; + else panic("no linesize"); /* - * Get cache sharing info if available. + * Extract and publish TLB information from Leaf 2 descriptors. */ - do_cpuid(0, cpuid_result); - if (cpuid_result[eax] >= 4) { - uint32_t reg[4]; - uint32_t index; - for (index = 0;; index++) { - /* - * Scan making calls for cpuid with %eax = 4 - * to get info about successive cache levels - * until a null type is returned. - */ - cache_type_t type = Lnone; - uint32_t cache_type; - uint32_t cache_level; - uint32_t cache_sharing; - - reg[eax] = 4; /* cpuid request 4 */ - reg[ecx] = index; /* index starting at 0 */ - cpuid(reg); -//kprintf("cpuid(4) index=%d eax=%p\n", index, reg[eax]); - cache_type = bitfield(reg[eax], 4, 0); - if (cache_type == 0) - break; /* done with cache info */ - cache_level = bitfield(reg[eax], 7, 5); - cache_sharing = bitfield(reg[eax], 25, 14); - info_p->cpuid_cores_per_package = - bitfield(reg[eax], 31, 26) + 1; - switch (cache_level) { - case 1: - type = cache_type == 1 ? L1D : - cache_type == 2 ? L1I : - Lnone; + for (i = 1; i < sizeof(info_p->cache_info); i++) { + cpuid_cache_descriptor_t *descp; + int id; + int level; + int page; + + descp = cpuid_leaf2_find(info_p->cache_info[i]); + if (descp == NULL) + continue; + + switch (descp->type) { + case TLB: + page = (descp->size == SMALL) ? TLB_SMALL : TLB_LARGE; + /* determine I or D: */ + switch (descp->level) { + case INST: + id = TLB_INST; break; - case 2: - type = cache_type == 3 ? L2U : - Lnone; + case DATA: + case DATA0: + case DATA1: + id = TLB_DATA; break; - case 3: - type = cache_type == 3 ? L3U : - Lnone; + default: + continue; } - if (type != Lnone) - info_p->cache_sharing[type] = cache_sharing + 1; - } + /* determine level: */ + switch (descp->level) { + case DATA1: + level = 1; + break; + default: + level = 0; + } + info_p->cpuid_tlb[id][page][level] = descp->entries; + break; + case STLB: + info_p->cpuid_stlb = descp->entries; + } } } -static void set_cpu_intel( i386_cpu_info_t * info_p ) -{ - set_cpu_generic(info_p); - set_intel_cache_info(info_p); - info_p->cpuid_model_string = get_intel_model_string(info_p, &info_p->cpuid_cpu_type, &info_p->cpuid_cpu_subtype); -} - -static const char * get_amd_model_string( i386_cpu_info_t * info_p, cpu_type_t* type, cpu_subtype_t* subtype ) -{ - *type = CPU_TYPE_X86; - *subtype = CPU_SUBTYPE_X86_ARCH1; - - /* check for brand id string */ - switch (info_p->cpuid_family) - { - case CPUID_FAMILY_486: - switch (info_p->cpuid_model) { - case CPUID_MODEL_AM486_DX: - case CPUID_MODEL_AM486_DX2: - case CPUID_MODEL_AM486_DX2WB: - case CPUID_MODEL_AM486_DX4: - case CPUID_MODEL_AM486_DX4WB: - return "Am486"; - case CPUID_MODEL_AM486_5X86: - case CPUID_MODEL_AM486_5X86WB: - return "Am5x86"; - } - break; - case CPUID_FAMILY_586: - switch (info_p->cpuid_model) { - case CPUID_MODEL_K5M0: - case CPUID_MODEL_K5M1: - case CPUID_MODEL_K5M2: - case CPUID_MODEL_K5M3: - return "AMD-K5"; - case CPUID_MODEL_K6M6: - case CPUID_MODEL_K6M7: - return "AMD-K6"; - case CPUID_MODEL_K6_2: - return "AMD-K6-2"; - case CPUID_MODEL_K6_III: - return "AMD-K6-III"; - } - break; - case CPUID_FAMILY_686: - switch (info_p->cpuid_model) { - case CPUID_MODEL_ATHLON_M1: - case CPUID_MODEL_ATHLON_M2: - case CPUID_MODEL_ATHLON_M4: - case CPUID_MODEL_ATHLON_M6: - case CPUID_MODEL_ATHLON_M8: - case CPUID_MODEL_ATHLON_M10: - return "AMD Athlon"; - case CPUID_MODEL_DURON_M3: - case CPUID_MODEL_DURON_M7: - return "AMD Duron"; - default: - return "Unknown AMD Athlon"; - } - case CPUID_FAMILY_EXTENDED: - switch (info_p->cpuid_model) { - case CPUID_MODEL_ATHLON64: - return "AMD Athlon 64"; - case CPUID_MODEL_OPTERON: - return "AMD Opteron"; - default: - return "Unknown AMD-64"; - } - } - return "Unknown AMD"; -} - -static void set_amd_cache_info( i386_cpu_info_t * info_p ) -{ - uint32_t cpuid_result[4]; - - /* It would make sense to fill in info_p->cache_info with complete information - * on the TLBs and data cache associativity, lines, etc, either by mapping - * to the Intel tags (if possible), or replacing cache_info with a generic - * mechanism. But right now, nothing makes use of that information (that I know - * of). - */ - - /* L1 Cache and TLB Information */ - do_cpuid(0x80000005, cpuid_result); - - /* EAX: TLB Information for 2-Mbyte and 4-MByte Pages */ - /* (ignore) */ - - /* EBX: TLB Information for 4-Kbyte Pages */ - /* (ignore) */ - - /* ECX: L1 Data Cache Information */ - info_p->cache_size[L1D] = ((cpuid_result[ecx] >> 24) & 0xFF) * 1024; - info_p->cache_linesize = (cpuid_result[ecx] & 0xFF); - - /* EDX: L1 Instruction Cache Information */ - info_p->cache_size[L1I] = ((cpuid_result[edx] >> 24) & 0xFF) * 1024; - - /* L2 Cache Information */ - do_cpuid(0x80000006, cpuid_result); - - /* EAX: L2 TLB Information for 2-Mbyte and 4-Mbyte Pages */ - /* (ignore) */ - - /* EBX: L2 TLB Information for 4-Kbyte Pages */ - /* (ignore) */ - - /* ECX: L2 Cache Information */ - info_p->cache_size[L2U] = ((cpuid_result[ecx] >> 16) & 0xFFFF) * 1024; - if (info_p->cache_size[L2U] > 0) - info_p->cache_linesize = cpuid_result[ecx] & 0xFF; -} - -static void set_cpu_amd( i386_cpu_info_t * info_p ) -{ - set_cpu_generic(info_p); - set_amd_cache_info(info_p); - info_p->cpuid_model_string = get_amd_model_string(info_p, &info_p->cpuid_cpu_type, &info_p->cpuid_cpu_subtype); -} - -static void set_cpu_nsc( i386_cpu_info_t * info_p ) -{ - set_cpu_generic(info_p); - set_amd_cache_info(info_p); - - /* check for brand id string */ - if (info_p->cpuid_family == CPUID_FAMILY_586 && info_p->cpuid_model == CPUID_MODEL_GX1) { - info_p->cpuid_model_string = "AMD Geode GX1"; - } else if (info_p->cpuid_family == CPUID_FAMILY_586 && info_p->cpuid_model == CPUID_MODEL_GX2) { - info_p->cpuid_model_string = "AMD Geode GX"; - } else { - info_p->cpuid_model_string = "Unknown National Semiconductor"; - } - info_p->cpuid_cpu_type = CPU_TYPE_X86; - info_p->cpuid_cpu_subtype = CPU_SUBTYPE_X86_ARCH1; -} - static void -set_cpu_generic(i386_cpu_info_t *info_p) +cpuid_set_generic_info(i386_cpu_info_t *info_p) { - uint32_t cpuid_result[4]; - uint32_t max_extid; + uint32_t reg[4]; char str[128], *p; + /* do cpuid 0 to get vendor */ + cpuid_fn(0, reg); + info_p->cpuid_max_basic = reg[eax]; + bcopy((char *)®[ebx], &info_p->cpuid_vendor[0], 4); /* ug */ + bcopy((char *)®[ecx], &info_p->cpuid_vendor[8], 4); + bcopy((char *)®[edx], &info_p->cpuid_vendor[4], 4); + info_p->cpuid_vendor[12] = 0; + /* get extended cpuid results */ - do_cpuid(0x80000000, cpuid_result); - max_extid = cpuid_result[eax]; + cpuid_fn(0x80000000, reg); + info_p->cpuid_max_ext = reg[eax]; /* check to see if we can get brand string */ - if (max_extid >= 0x80000004) { + if (info_p->cpuid_max_ext >= 0x80000004) { /* * The brand string 48 bytes (max), guaranteed to * be NUL terminated. */ - do_cpuid(0x80000002, cpuid_result); - bcopy((char *)cpuid_result, &str[0], 16); - do_cpuid(0x80000003, cpuid_result); - bcopy((char *)cpuid_result, &str[16], 16); - do_cpuid(0x80000004, cpuid_result); - bcopy((char *)cpuid_result, &str[32], 16); + cpuid_fn(0x80000002, reg); + bcopy((char *)reg, &str[0], 16); + cpuid_fn(0x80000003, reg); + bcopy((char *)reg, &str[16], 16); + cpuid_fn(0x80000004, reg); + bcopy((char *)reg, &str[32], 16); for (p = str; *p != '\0'; p++) { if (*p != ' ') break; } - strncpy(info_p->cpuid_brand_string, - p, sizeof(info_p->cpuid_brand_string)-1); - info_p->cpuid_brand_string[sizeof(info_p->cpuid_brand_string)-1] = '\0'; + strlcpy(info_p->cpuid_brand_string, + p, sizeof(info_p->cpuid_brand_string)); - if (!strcmp(info_p->cpuid_brand_string, CPUID_STRING_UNKNOWN)) { + if (!strncmp(info_p->cpuid_brand_string, CPUID_STRING_UNKNOWN, + min(sizeof(info_p->cpuid_brand_string), + strlen(CPUID_STRING_UNKNOWN) + 1))) { /* - * This string means we have a BIOS-programmable brand string, - * and the BIOS couldn't figure out what sort of CPU we have. + * This string means we have a firmware-programmable brand string, + * and the firmware couldn't figure out what sort of CPU we have. */ info_p->cpuid_brand_string[0] = '\0'; } } + /* Get cache and addressing info. */ + if (info_p->cpuid_max_ext >= 0x80000006) { + cpuid_fn(0x80000006, reg); + info_p->cpuid_cache_linesize = bitfield32(reg[ecx], 7, 0); + info_p->cpuid_cache_L2_associativity = + bitfield32(reg[ecx],15,12); + info_p->cpuid_cache_size = bitfield32(reg[ecx],31,16); + cpuid_fn(0x80000008, reg); + info_p->cpuid_address_bits_physical = + bitfield32(reg[eax], 7, 0); + info_p->cpuid_address_bits_virtual = + bitfield32(reg[eax],15, 8); + } + /* get processor signature and decode */ - do_cpuid(1, cpuid_result); - info_p->cpuid_signature = cpuid_result[eax]; - info_p->cpuid_stepping = bitfield(cpuid_result[eax], 3, 0); - info_p->cpuid_model = bitfield(cpuid_result[eax], 7, 4); - info_p->cpuid_family = bitfield(cpuid_result[eax], 11, 8); - info_p->cpuid_type = bitfield(cpuid_result[eax], 13, 12); - info_p->cpuid_extmodel = bitfield(cpuid_result[eax], 19, 16); - info_p->cpuid_extfamily = bitfield(cpuid_result[eax], 27, 20); - info_p->cpuid_brand = bitfield(cpuid_result[ebx], 7, 0); - info_p->cpuid_logical_per_package = - bitfield(cpuid_result[ebx], 23, 16); - info_p->cpuid_features = quad(cpuid_result[ecx], cpuid_result[edx]); - - if (max_extid >= 0x80000001) { - do_cpuid(0x80000001, cpuid_result); + cpuid_fn(1, reg); + info_p->cpuid_signature = reg[eax]; + info_p->cpuid_stepping = bitfield32(reg[eax], 3, 0); + info_p->cpuid_model = bitfield32(reg[eax], 7, 4); + info_p->cpuid_family = bitfield32(reg[eax], 11, 8); + info_p->cpuid_type = bitfield32(reg[eax], 13, 12); + info_p->cpuid_extmodel = bitfield32(reg[eax], 19, 16); + info_p->cpuid_extfamily = bitfield32(reg[eax], 27, 20); + info_p->cpuid_brand = bitfield32(reg[ebx], 7, 0); + info_p->cpuid_features = quad(reg[ecx], reg[edx]); + + /* Fold extensions into family/model */ + if (info_p->cpuid_family == 0x0f) + info_p->cpuid_family += info_p->cpuid_extfamily; + if (info_p->cpuid_family == 0x0f || info_p->cpuid_family == 0x06) + info_p->cpuid_model += (info_p->cpuid_extmodel << 4); + + if (info_p->cpuid_features & CPUID_FEATURE_HTT) + info_p->cpuid_logical_per_package = + bitfield32(reg[ebx], 23, 16); + else + info_p->cpuid_logical_per_package = 1; + + if (info_p->cpuid_max_ext >= 0x80000001) { + cpuid_fn(0x80000001, reg); info_p->cpuid_extfeatures = - quad(cpuid_result[ecx], cpuid_result[edx]); + quad(reg[ecx], reg[edx]); + } + + /* Fold in the Invariant TSC feature bit, if present */ + if (info_p->cpuid_max_ext >= 0x80000007) { + cpuid_fn(0x80000007, reg); + info_p->cpuid_extfeatures |= + reg[edx] & (uint32_t)CPUID_EXTFEATURE_TSCI; + } + + /* Find the microcode version number a.k.a. signature a.k.a. BIOS ID */ + info_p->cpuid_microcode_version = + (uint32_t) (rdmsr64(MSR_IA32_BIOS_SIGN_ID) >> 32); + + if (info_p->cpuid_max_basic >= 0x5) { + cpuid_mwait_leaf_t *cmp = &info_p->cpuid_mwait_leaf; + + /* + * Extract the Monitor/Mwait Leaf info: + */ + cpuid_fn(5, reg); + cmp->linesize_min = reg[eax]; + cmp->linesize_max = reg[ebx]; + cmp->extensions = reg[ecx]; + cmp->sub_Cstates = reg[edx]; + info_p->cpuid_mwait_leafp = cmp; + } + + if (info_p->cpuid_max_basic >= 0x6) { + cpuid_thermal_leaf_t *ctp = &info_p->cpuid_thermal_leaf; + + /* + * The thermal and Power Leaf: + */ + cpuid_fn(6, reg); + ctp->sensor = bitfield32(reg[eax], 0, 0); + ctp->dynamic_acceleration = bitfield32(reg[eax], 1, 1); + ctp->thresholds = bitfield32(reg[ebx], 3, 0); + ctp->ACNT_MCNT = bitfield32(reg[ecx], 0, 0); + info_p->cpuid_thermal_leafp = ctp; + } + + if (info_p->cpuid_max_basic >= 0xa) { + cpuid_arch_perf_leaf_t *capp = &info_p->cpuid_arch_perf_leaf; + + /* + * Architectural Performance Monitoring Leaf: + */ + cpuid_fn(0xa, reg); + capp->version = bitfield32(reg[eax], 7, 0); + capp->number = bitfield32(reg[eax], 15, 8); + capp->width = bitfield32(reg[eax], 23, 16); + capp->events_number = bitfield32(reg[eax], 31, 24); + capp->events = reg[ebx]; + capp->fixed_number = bitfield32(reg[edx], 4, 0); + capp->fixed_width = bitfield32(reg[edx], 12, 5); + info_p->cpuid_arch_perf_leafp = capp; } return; } -static void -set_cpu_unknown(__unused i386_cpu_info_t *info_p) +static uint32_t +cpuid_set_cpufamily(i386_cpu_info_t *info_p) { - info_p->cpuid_model_string = "Unknown"; + uint32_t cpufamily = CPUFAMILY_UNKNOWN; + + switch (info_p->cpuid_family) { + case 6: + switch (info_p->cpuid_model) { + case 13: + cpufamily = CPUFAMILY_INTEL_6_13; + break; + case 14: + cpufamily = CPUFAMILY_INTEL_YONAH; + break; + case 15: + cpufamily = CPUFAMILY_INTEL_MEROM; + break; + case 23: + cpufamily = CPUFAMILY_INTEL_PENRYN; + break; + case CPUID_MODEL_NEHALEM: + case CPUID_MODEL_FIELDS: + case CPUID_MODEL_DALES: + case CPUID_MODEL_NEHALEM_EX: + cpufamily = CPUFAMILY_INTEL_NEHALEM; + break; + } + break; + } + + info_p->cpuid_cpufamily = cpufamily; + return cpufamily; } +void +cpuid_set_info(void) +{ + i386_cpu_info_t *info_p = &cpuid_cpu_info; + + bzero((void *)info_p, sizeof(cpuid_cpu_info)); + + cpuid_set_generic_info(info_p); + + /* verify we are running on a supported CPU */ + if ((strncmp(CPUID_VID_INTEL, info_p->cpuid_vendor, + min(strlen(CPUID_STRING_UNKNOWN) + 1, + sizeof(info_p->cpuid_vendor)))) || + (cpuid_set_cpufamily(info_p) == CPUFAMILY_UNKNOWN)) + panic("Unsupported CPU"); + + info_p->cpuid_cpu_type = CPU_TYPE_X86; + info_p->cpuid_cpu_subtype = CPU_SUBTYPE_X86_ARCH1; + + cpuid_set_cache_info(&cpuid_cpu_info); + + /* + * Find the number of enabled cores and threads + * (which determines whether SMT/Hyperthreading is active). + */ + switch (info_p->cpuid_cpufamily) { + case CPUFAMILY_INTEL_NEHALEM: { + uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT); + info_p->core_count = bitfield32((uint32_t)msr, 31, 16); + info_p->thread_count = bitfield32((uint32_t)msr, 15, 0); + break; + } + } + if (info_p->core_count == 0) { + info_p->core_count = info_p->cpuid_cores_per_package; + info_p->thread_count = info_p->cpuid_logical_per_package; + } + + cpuid_cpu_info.cpuid_model_string = ""; /* deprecated */ +} static struct { uint64_t mask; @@ -672,10 +712,16 @@ static struct { {CPUID_FEATURE_SMX, "SMX"}, {CPUID_FEATURE_EST, "EST"}, {CPUID_FEATURE_TM2, "TM2"}, - {CPUID_FEATURE_MNI, "MNI"}, + {CPUID_FEATURE_SSSE3, "SSSE3"}, {CPUID_FEATURE_CID, "CID"}, {CPUID_FEATURE_CX16, "CX16"}, {CPUID_FEATURE_xTPR, "TPR"}, + {CPUID_FEATURE_PDCM, "PDCM"}, + {CPUID_FEATURE_SSE4_1, "SSE4.1"}, + {CPUID_FEATURE_SSE4_2, "SSE4.2"}, + {CPUID_FEATURE_xAPIC, "xAPIC"}, + {CPUID_FEATURE_POPCNT, "POPCNT"}, + {CPUID_FEATURE_VMM, "VMM"}, {0, 0} }, extfeature_map[] = { @@ -683,13 +729,26 @@ extfeature_map[] = { {CPUID_EXTFEATURE_XD, "XD"}, {CPUID_EXTFEATURE_EM64T, "EM64T"}, {CPUID_EXTFEATURE_LAHF, "LAHF"}, + {CPUID_EXTFEATURE_RDTSCP, "RDTSCP"}, + {CPUID_EXTFEATURE_TSCI, "TSCI"}, {0, 0} }; +i386_cpu_info_t * +cpuid_info(void) +{ + /* Set-up the cpuid_info stucture lazily */ + if (cpuid_cpu_infop == NULL) { + cpuid_set_info(); + cpuid_cpu_infop = &cpuid_cpu_info; + } + return cpuid_cpu_infop; +} + char * cpuid_get_feature_names(uint64_t features, char *buf, unsigned buf_len) { - int len = -1; + size_t len = -1; char *p = buf; int i; @@ -698,7 +757,7 @@ cpuid_get_feature_names(uint64_t features, char *buf, unsigned buf_len) continue; if (len > 0) *p++ = ' '; - len = min(strlen(feature_map[i].name), (buf_len-1) - (p-buf)); + len = min(strlen(feature_map[i].name), (size_t) ((buf_len-1) - (p-buf))); if (len == 0) break; bcopy(feature_map[i].name, p, len); @@ -711,7 +770,7 @@ cpuid_get_feature_names(uint64_t features, char *buf, unsigned buf_len) char * cpuid_get_extfeature_names(uint64_t extfeatures, char *buf, unsigned buf_len) { - int len = -1; + size_t len = -1; char *p = buf; int i; @@ -720,7 +779,7 @@ cpuid_get_extfeature_names(uint64_t extfeatures, char *buf, unsigned buf_len) continue; if (len > 0) *p++ = ' '; - len = min(strlen(extfeature_map[i].name), (buf_len-1)-(p-buf)); + len = min(strlen(extfeature_map[i].name), (size_t) ((buf_len-1)-(p-buf))); if (len == 0) break; bcopy(extfeature_map[i].name, p, len); @@ -730,6 +789,7 @@ cpuid_get_extfeature_names(uint64_t extfeatures, char *buf, unsigned buf_len) return buf; } + void cpuid_feature_display( const char *header) @@ -773,34 +833,42 @@ cpuid_cpu_display( unsigned int cpuid_family(void) { - return cpuid_cpu_info.cpuid_family; + return cpuid_info()->cpuid_family; +} + +uint32_t +cpuid_cpufamily(void) +{ + return cpuid_info()->cpuid_cpufamily; } cpu_type_t cpuid_cputype(void) { - return cpuid_cpu_info.cpuid_cpu_type; + return cpuid_info()->cpuid_cpu_type; } cpu_subtype_t cpuid_cpusubtype(void) { - return cpuid_cpu_info.cpuid_cpu_subtype; + return cpuid_info()->cpuid_cpu_subtype; } uint64_t cpuid_features(void) { static int checked = 0; - char fpu_arg[16] = { 0 }; + char fpu_arg[20] = { 0 }; + + (void) cpuid_info(); if (!checked) { /* check for boot-time fpu limitations */ - if (PE_parse_boot_arg("_fpu", &fpu_arg[0])) { + if (PE_parse_boot_argn("_fpu", &fpu_arg[0], sizeof (fpu_arg))) { printf("limiting fpu features to: %s\n", fpu_arg); - if (!strncmp("387", fpu_arg, sizeof "387") || !strncmp("mmx", fpu_arg, sizeof "mmx")) { + if (!strncmp("387", fpu_arg, sizeof("387")) || !strncmp("mmx", fpu_arg, sizeof("mmx"))) { printf("no sse or sse2\n"); cpuid_cpu_info.cpuid_features &= ~(CPUID_FEATURE_SSE | CPUID_FEATURE_SSE2 | CPUID_FEATURE_FXSR); - } else if (!strncmp("sse", fpu_arg, sizeof "sse")) { + } else if (!strncmp("sse", fpu_arg, sizeof("sse"))) { printf("no sse2\n"); cpuid_cpu_info.cpuid_features &= ~(CPUID_FEATURE_SSE2); } @@ -813,20 +881,9 @@ cpuid_features(void) uint64_t cpuid_extfeatures(void) { - return cpuid_cpu_info.cpuid_extfeatures; + return cpuid_info()->cpuid_extfeatures; } -i386_cpu_info_t * -cpuid_info(void) -{ - return &cpuid_cpu_info; -} - -void -cpuid_set_info(void) -{ - cpuid_get_info(&cpuid_cpu_info); -} #if MACH_KDB