X-Git-Url: https://git.saurik.com/apple/xnu.git/blobdiff_plain/765c9de3b4af7c2078d16a03812ae2c7c2b24938..d12e16782ebf8bb779633dff9e14486293bf6d07:/osfmk/ppc/start.s diff --git a/osfmk/ppc/start.s b/osfmk/ppc/start.s index 6bdd30360..6ad6a1e4c 100644 --- a/osfmk/ppc/start.s +++ b/osfmk/ppc/start.s @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -54,11 +55,13 @@ #define PROCESSOR_VERSION_604 4 #define PROCESSOR_VERSION_603e 6 #define PROCESSOR_VERSION_750 8 +#define PROCESSOR_VERSION_750FX 0x7000 /* ? */ #define PROCESSOR_VERSION_604e 9 #define PROCESSOR_VERSION_604ev 10 /* ? */ #define PROCESSOR_VERSION_7400 12 /* ? */ #define PROCESSOR_VERSION_7410 0x800C /* ? */ #define PROCESSOR_VERSION_7450 0x8000 /* ? */ +#define PROCESSOR_VERSION_7455 0x8001 /* ? */ /* * Interrupt and bootup stack for initial processor @@ -436,17 +439,6 @@ callcpu: ; Specific processor initialization routines ; -; 750CX - -init750CX: - bf firstBoot, init750 ; No init for wakeup.... - mfspr r13,hid1 ; Get HID1 - li r14,lo16(0xFD5F) ; Get valid - rlwinm r13,r13,4,28,31 ; Isolate - slw r14,r14,r13 ; Position - rlwimi r17,r14,15-pfCanNapb,pfCanNapb,pfCanNapb ; Set it - b init750 ; Join common... - ; 750 init750: @@ -465,6 +457,7 @@ i750hl2: slw r14,r14,r15 ; Set 256KB, 512KB, or 1MB beq- init750l2none ; Not a valid setting... + stw r13,pfl2crOriginal(r30) ; Shadow the L2CR stw r13,pfl2cr(r30) ; Shadow the L2CR stw r14,pfl2Size(r30) ; Set the L2 size b init750l2done ; Done with L2 @@ -478,13 +471,76 @@ init750l2done: blr ; Return... init750nb: - lwz r11,pfHID0(r30) ; Get HID0 + lwz r11,pfHID0(r30) ; Get HID0 sync mtspr hid0,r11 ; Set the HID isync sync blr +; 750CX + +init750CX: + bf firstBoot, init750 ; No init for wakeup.... + mfspr r13,hid1 ; Get HID1 + li r14,lo16(0xFD5F) ; Get valid + rlwinm r13,r13,4,28,31 ; Isolate + slw r14,r14,r13 ; Position + rlwimi r17,r14,15-pfCanNapb,pfCanNapb,pfCanNapb ; Set it + b init750 ; Join common... + + +; 750FX + +init750FX: + bf firstBoot, init750FXnb + mfspr r11, hid1 + stw r11, pfHID1(r30) ; Save the HID1 value + b init750 + +init750FXnb: + lwz r13, pfHID0(r30) ; Get HID0 + lwz r11, pfHID1(r30) ; Get HID1 + + rlwinm. r0, r11, 0, hid1ps, hid1ps ; Isolate the hid1ps bit + beq init750FXnb2 ; Clear BTIC if hid1ps set + rlwinm r13, r13, 0, btic+1, btic-1 ; Clear the BTIC bit + +init750FXnb2: + sync + mtspr hid0, r13 ; Set the HID + isync + sync + + rlwinm r12, r11, 0, hid1ps+1, hid1ps-1 ; Select PLL0 + mtspr hid1, r12 ; Restore PLL config + mftb r13 ; Wait 5000 ticks (> 200 us) + +init750FXnbloop: + mftb r14 + sub r14, r14, r13 + cmpli cr0, r14, 5000 + ble init750FXnbloop + mtspr hid1, r11 ; Select the desired PLL + blr + +; 750FX vers 2.0 or later +init750FXV2: + bf firstBoot, init750FXV2nb ; Wake from sleep + + mfspr r11, hid2 + stw r11, pfHID2(r30) ; Save the HID2 value + b init750FX ; Continue with 750FX init + +init750FXV2nb: + lwz r13, pfHID2(r30) ; Get HID2 + rlwinm r13, r13, 0, hid2vmin+1, hid2vmin-1 ; Clear the vmin bit + mtspr hid2, r13 ; Restore HID2 value + sync ; Wait for it to be done + b init750FX + +; 7400 + init7400: bf firstBoot,i7400nb ; Do different if not initial boot... mfspr r13,l2cr ; Get the L2CR rlwinm. r0,r13,0,l2e,l2e ; Any L2? @@ -496,6 +552,7 @@ i7400hl2: lis r14,hi16(256*1024) ; Base L2 size rlwinm r15,r15,4,30,31 slw r14,r14,r15 ; Set 256KB, 512KB, 1MB, or 2MB + stw r13,pfl2crOriginal(r30) ; Shadow the L2CR stw r13,pfl2cr(r30) ; Shadow the L2CR stw r14,pfl2Size(r30) ; Set the L2 size @@ -512,6 +569,8 @@ i7400hl2: lis r14,hi16(256*1024) ; Base L2 size blr ; Return... i7400nb: + li r11,0 + mtspr l2cr,r11 ; Make sure L2CR is zero lwz r11,pfHID0(r30) ; Get HID0 sync mtspr hid0,r11 ; Set the HID @@ -528,54 +587,68 @@ i7400nb: isync sync blr - + +; 7400 (ver 2.0 - ver 2.7) + +init7400v2_7: + bf firstBoot, init7400 + mfspr r13, hid0 ; Get the HID0 + ori r13, r13, nopdstm ; ? + mtspr hid0, r13 ; Set the HID0 + isync + sync + b init7400 + ; 7410 ; Note that this is the same as 7400 except we initialize the l2cr2 register init7410: li r13,0 ; Clear mtspr 1016,r13 ; Turn off direct cache b init7400 ; Join up with common.... - -; 7450 -init7450: bf firstBoot,i7450nb ; Do different if not initial boot... - oris r17,r17,hi16(pfAvJava) ; Show that we do Java mode in non-open source version + +; 745X - Any 7450 family processor + +init745X: + bf firstBoot,init745Xnb ; Do different if not initial boot... mfspr r13,l2cr ; Get the L2CR rlwinm. r0,r13,0,l2e,l2e ; Any L2? - bne+ i7450hl2 ; Yes... + bne+ init745Xhl2 ; Yes... rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature -i7450hl2: lis r14,hi16(256*1024) ; Base L2 size +init745Xhl2: lis r14,hi16(256*1024) ; Base L2 size rlwinm r15,r13,22,12,13 ; Convert to 256k, 512k, or 768k add r14,r14,r15 ; Add in minimum + stw r13,pfl2crOriginal(r30) ; Shadow the L2CR stw r13,pfl2cr(r30) ; Shadow the L2CR stw r14,pfl2Size(r30) ; Set the L2 size ; Take care of level 3 cache mfspr r13,l3cr ; Get the L3CR - rlwinm. r0,r13,0,l3e,l3e ; Any L2? - bne+ i7450hl3 ; Yes... - rlwinm r17,r17,0,pfL3b+1,pfL3b-1 ; No L2, turn off feature + rlwinm. r0,r13,0,l3e,l3e ; Any L3? + bne+ init745Xhl3 ; Yes... + rlwinm r17,r17,0,pfL3b+1,pfL3b-1 ; No L3, turn off feature -i7450hl3: cmplwi cr0,r13,0 ; No L3 if L3CR is zero - beq- init7450none ; Go turn off the features... +init745Xhl3: cmplwi cr0,r13,0 ; No L3 if L3CR is zero + beq- init745Xnone ; Go turn off the features... lis r14,hi16(1024*1024) ; Base L3 size rlwinm r15,r13,4,31,31 ; Get size multiplier slw r14,r14,r15 ; Set 1 or 2MB + stw r13,pfl3crOriginal(r30) ; Shadow the L3CR stw r13,pfl3cr(r30) ; Shadow the L3CR stw r14,pfl3Size(r30) ; Set the L3 size - b init7450fin ; Return.... + b init745Xfin ; Return.... -init7450none: +init745Xnone: rlwinm r17,r17,0,pfL3fab+1,pfL3b-1 ; No 3rd level cache or assist rlwinm r11,r17,pfWillNapb-pfCanNapb,pfCanNapb,pfCanNapb ; Set pfCanNap if pfWillNap is set or r17,r17,r11 -init7450fin: +init745Xfin: rlwinm r17,r17,0,pfWillNapb+1,pfWillNapb-1 ; Make sure pfWillNap is not set mfspr r11,hid0 ; Get the current HID0 @@ -592,10 +665,12 @@ init7450fin: stw r11,pfLDSTCR(r30) ; Save the LDSTCR value mfspr r11,ldstdb ; Get the ldstdb register stw r11,pfLDSTDB(r30) ; Save the LDSTDB value + mfspr r11,pir ; Get the pir register + stw r11,pfBootConfig(r30) ; Save the BootConfig value blr ; Return.... -i7450nb: lwz r11,pfHID0(r30) ; Get HID0 +init745Xnb: lwz r11,pfHID0(r30) ; Get HID0 sync mtspr hid0,r11 ; Set the HID isync @@ -625,6 +700,21 @@ i7450nb: lwz r11,pfHID0(r30) ; Get HID0 sync blr +; 7450 - Specific + +init7450: + bf firstBoot, init745X ; Not boot, use standard init + + mfspr r13, pir ; Get BootConfig from PIR + rlwinm. r14, r13, 0, 20, 23 ; Is the pdet value zero + bne init7450done ; No, done for now + + ori r13, r13, 0x0400 ; Force pdet value to 4 + mtspr pir, r13 ; Write back the BootConfig + +init7450done: + b init745X ; Continue with standard init + ; ; Processor to feature table @@ -782,7 +872,51 @@ processor_types: .long 32*1024 .long 32*1024 +; 750FX (ver 1.x) + + .align 2 + .long 0xFFFF0F00 ; 1.x vers + .short PROCESSOR_VERSION_750FX + .short 0x0100 + .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pfL1i | pfL1d | pfL2 + .long init750FX + .long CPU_SUBTYPE_POWERPC_750 + .long 105 + .long 90 + .long 32 + .long 32*1024 + .long 32*1024 + +; 750FX (generic) + .align 2 + .long 0xFFFF0000 ; All revisions + .short PROCESSOR_VERSION_750FX + .short 0 + .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pfL1i | pfL1d | pfL2 + .long init750FXV2 + .long CPU_SUBTYPE_POWERPC_750 + .long 105 + .long 90 + .long 32 + .long 32*1024 + .long 32*1024 + +; 7400 (ver 2.0 - ver 2.7) + + .align 2 + .long 0xFFFFFFF8 ; All revisions + .short PROCESSOR_VERSION_7400 + .short 0x0200 + .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pfThermal | pfL1i | pfL1d | pfL1fa | pfL2 | pfL2fa + .long init7400v2_7 + .long CPU_SUBTYPE_POWERPC_7400 + .long 105 + .long 90 + .long 32 + .long 32*1024 + .long 32*1024 + ; 7400 (generic) .align 2 @@ -834,7 +968,7 @@ processor_types: .long 0xFFFFFF00 ; Just revisions 1.xx .short PROCESSOR_VERSION_7450 .short 0x0100 - .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfLClck | pfL1nnc | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa + .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa .long init7450 .long CPU_SUBTYPE_POWERPC_7450 .long 105 @@ -849,7 +983,7 @@ processor_types: .long 0xFFFFFFFF ; Just revision 2.0 .short PROCESSOR_VERSION_7450 .short 0x0200 - .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa + .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa .long init7450 .long CPU_SUBTYPE_POWERPC_7450 .long 105 @@ -864,7 +998,7 @@ processor_types: .long 0xFFFF0000 ; All other revisions .short PROCESSOR_VERSION_7450 .short 0 - .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfWillNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa + .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa .long init7450 .long CPU_SUBTYPE_POWERPC_7450 .long 105 @@ -873,6 +1007,50 @@ processor_types: .long 32*1024 .long 32*1024 +; 7455 (1.xx) Just like 7450 2.0 + + .align 2 + .long 0xFFFFFF00 ; Just revisions 1.xx + .short PROCESSOR_VERSION_7455 + .short 0x0100 + .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa + .long init745X + .long CPU_SUBTYPE_POWERPC_7450 + .long 105 + .long 90 + .long 32 + .long 32*1024 + .long 32*1024 + +; 7455 (2.0) + + .align 2 + .long 0xFFFFFFFF ; Just revision 2.0 + .short PROCESSOR_VERSION_7455 + .short 0x0200 + .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa + .long init745X + .long CPU_SUBTYPE_POWERPC_7450 + .long 105 + .long 90 + .long 32 + .long 32*1024 + .long 32*1024 + +; 7455 (2.1) + + .align 2 + .long 0xFFFF0000 ; All other revisions + .short PROCESSOR_VERSION_7455 + .short 0 + .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa + .long init745X + .long CPU_SUBTYPE_POWERPC_7450 + .long 105 + .long 90 + .long 32 + .long 32*1024 + .long 32*1024 ; Default dumb loser machine