X-Git-Url: https://git.saurik.com/apple/xnu.git/blobdiff_plain/55e303ae13a4cf49d70f2294092726f2fffb9ef2..5353443c9cd32307ab4ce5d2e263522955d5d5dd:/osfmk/ppc/start.s diff --git a/osfmk/ppc/start.s b/osfmk/ppc/start.s index 29c228362..583baf34d 100644 --- a/osfmk/ppc/start.s +++ b/osfmk/ppc/start.s @@ -3,22 +3,19 @@ * * @APPLE_LICENSE_HEADER_START@ * - * Copyright (c) 1999-2003 Apple Computer, Inc. All Rights Reserved. + * The contents of this file constitute Original Code as defined in and + * are subject to the Apple Public Source License Version 1.1 (the + * "License"). You may not use this file except in compliance with the + * License. Please obtain a copy of the License at + * http://www.apple.com/publicsource and read it before using this file. * - * This file contains Original Code and/or Modifications of Original Code - * as defined in and that are subject to the Apple Public Source License - * Version 2.0 (the 'License'). You may not use this file except in - * compliance with the License. Please obtain a copy of the License at - * http://www.opensource.apple.com/apsl/ and read it before using this - * file. - * - * The Original Code and all software distributed under the License are - * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * This Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. - * Please see the License for the specific language governing rights and - * limitations under the License. + * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. * * @APPLE_LICENSE_HEADER_END@ */ @@ -44,18 +41,17 @@ #define ptRevision 6 #define ptFeatures 8 #define ptCPUCap 12 -#define ptPatch 16 -#define ptInitRout 20 -#define ptRptdProc 24 -#define ptTempMax 28 -#define ptTempThr 32 -#define ptLineSize 36 -#define ptl1iSize 40 -#define ptl1dSize 44 -#define ptPTEG 48 -#define ptMaxVAddr 52 -#define ptMaxPAddr 56 -#define ptSize 60 +#define ptPwrModes 16 +#define ptPatch 20 +#define ptInitRout 24 +#define ptRptdProc 28 +#define ptLineSize 32 +#define ptl1iSize 36 +#define ptl1dSize 40 +#define ptPTEG 44 +#define ptMaxVAddr 48 +#define ptMaxPAddr 52 +#define ptSize 56 #define bootCPU 10 #define firstInit 9 @@ -181,10 +177,8 @@ donePVR: lwz r20,ptInitRout(r26) ; Grab the special init routine lwz r18,ptRptdProc(r26) ; Get the reported processor sth r18,pfrptdProc(r30) ; Set the reported processor - lwz r13,ptTempMax(r26) ; Get maximum operating temperature - stw r13,thrmmaxTemp(r30) ; Set the maximum - lwz r13,ptTempThr(r26) ; Get temprature to throttle down when exceeded - stw r13,thrmthrottleTemp(r30) ; Set the temperature that we throttle + lwz r13,ptPwrModes(r26) ; Get the supported power modes + stw r13,pfPowerModes(r30) ; Set the supported power modes lwz r13,ptLineSize(r26) ; Get the cache line size sth r13,pflineSize(r30) ; Save it @@ -247,7 +241,7 @@ doOurInit: mr. r20,r20 ; See if initialization routine cpyFCpu: addic. r2,r2,-1 ; Count down la r8,pfAvailable(r23) ; Point to features of boot processor la r7,pfAvailable(r6) ; Point to features of our processor - li r9,(pfSize+thrmSize)/4 ; Get size of a features area + li r9,pfSize/4 ; Get size of a features area ble-- nofeatcpy ; Copied all we need cpyFeat: subi r9,r9,1 ; Count word @@ -434,18 +428,7 @@ noVector: rlwinm. r0,r17,0,pfSMPcapb,pfSMPcapb ; See if we can do SMP lhz r13,PP_CPU_NUMBER(r30) ; Get the CPU number mtspr pir,r13 ; Set the PIR -noSMP: rlwinm. r0,r17,0,pfThermalb,pfThermalb ; See if there is an TAU - beq- noThermometer ; Nope... - - li r13,0 ; Disable thermals for now - mtspr thrm3,r13 ; Do it - li r13,lo16(thrmtidm|thrmvm) ; Set for lower-than thermal event at 0 degrees - mtspr thrm1,r13 ; Do it - lis r13,hi16(thrmthrm) ; Set 127 degrees - ori r13,r13,lo16(thrmvm) ; Set for higher-than event - mtspr thrm2,r13 ; Set it - -noThermometer: +noSMP: bl EXT(cacheInit) ; Initializes all caches (including the TLB) @@ -672,18 +655,20 @@ init745X: rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature init745Xhl2: - mfpvr r14 ; Get processor version - rlwinm r14,r14,16,16,31 ; Isolate processor version - cmpli cr0, r14, PROCESSOR_VERSION_7457 + mfpvr r14 ; Get processor version + rlwinm r14,r14,16,16,31 ; Isolate processor version + cmpli cr0, r14, PROCESSOR_VERSION_7457 ; Test for 7457 or + cmpli cr1, r14, PROCESSOR_VERSION_7447A ; 7447A + cror cr0_eq, cr1_eq, cr0_eq lis r14,hi16(512*1024) ; 512KB L2 - beq init745Xhl2_2 + beq init745Xhl2_2 lis r14,hi16(256*1024) ; Base L2 size rlwinm r15,r13,22,12,13 ; Convert to 256k, 512k, or 768k add r14,r14,r15 ; Add in minimum init745Xhl2_2: - stw r13,pfl2crOriginal(r30) ; Shadow the L2CR + stw r13,pfl2crOriginal(r30) ; Shadow the L2CR stw r13,pfl2cr(r30) ; Shadow the L2CR stw r14,pfl2Size(r30) ; Set the L2 size @@ -780,7 +765,7 @@ init7450done: init970: li r20,0 ; Clear this - mtspr hior,r20 ; Make sure that 0 is interrupt prefix + mtspr hior,r20 ; Make sure that 0 is interrupt prefix bf firstBoot,init970nb ; No init for wakeup or second processor.... @@ -792,7 +777,21 @@ init970: std r11,pfHID4(r30) ; Save original mfspr r11,hid5 ; Get original hid5 std r11,pfHID5(r30) ; Save original - + + lis r0, hi16(dnapm) ; Create a mask for the dnap bit + sldi r0, r0, 32 ; Shift to the top half + ld r11,pfHID0(r30) ; Load the hid0 value + andc r11, r11, r0 ; Clear the dnap bit + isync + mtspr hid0,r11 ; Stuff it + mfspr r11,hid0 ; Get it + mfspr r11,hid0 ; Get it + mfspr r11,hid0 ; Get it + mfspr r11,hid0 ; Get it + mfspr r11,hid0 ; Get it + mfspr r11,hid0 ; Get it + isync + ; ; We can not query or change the L2 size. We will just ; phoney up a L2CR to make sysctl "happy" and set the @@ -811,7 +810,11 @@ init970: ; Start up code for second processor or wake up from sleep ; -init970nb: ld r11,pfHID0(r30) ; Get it +init970nb: + lis r0, hi16(dnapm) ; Create a mask for the dnap bit + sldi r0, r0, 32 ; Shift to the top half + ld r11,pfHID0(r30) ; Load the hid0 value + andc r11, r11, r0 ; Clear the dnap bit isync mtspr hid0,r11 ; Stuff it mfspr r11,hid0 ; Get it @@ -822,20 +825,48 @@ init970nb: ld r11,pfHID0(r30) ; Get it mfspr r11,hid0 ; Get it isync - ld r11,pfHID1(r30) ; Get it + ld r20,pfHID1(r30) ; Get it isync - mtspr hid1,r11 ; Stick it - mtspr hid1,r11 ; Stick it again + mtspr hid1,r20 ; Stick it + mtspr hid1,r20 ; Stick it again isync ld r11,pfHID4(r30) ; Get it sync mtspr hid4,r11 ; Stick it isync + + lis r11,0xE000 ; Get the unlikeliest ESID possible + srdi r11,r11,1 ; Make 0x7FFFFFFFF0000000 + slbie r11 ; Make sure the ERAT is cleared ld r11,pfHID5(r30) ; Get it mtspr hid5,r11 ; Set it isync +; +; May have changed dcbz mode so kill icache +; + + eqv r13,r13,r13 ; Get a constant -1 + mr r14,r20 ; Save HID1 + rldimi r14,r13,54,9 ; Set force icbi match mode + + li r11,0 ; Set start if ICBI range + isync + mtspr hid1,r14 ; Stick it + mtspr hid1,r14 ; Stick it again + isync + +inin970ki: icbi 0,r11 ; Kill I$ + addi r11,r11,128 ; Next line + andis. r0,r11,1 ; Have we done them all? + beq++ inin970ki ; Not yet... + + isync + mtspr hid1,r20 ; Stick it + mtspr hid1,r20 ; Stick it again + isync + blr ; Leave... @@ -855,11 +886,10 @@ initUnsupported: ; .short ptRevision - Revision code from PVR. A zero value denotes the generic attributes if not specific ; .long ptFeatures - Available features ; .long ptCPUCap - Default value for _cpu_capabilities +; .long ptPwrModes - Available power management features ; .long ptPatch - Patch features ; .long ptInitRout - Initilization routine. Can modify any of the other attributes. ; .long ptRptdProc - Processor type reported -; .long ptTempMax - Maximum operating temprature -; .long ptTempThr - Temprature threshold. We throttle if above ; .long ptLineSize - Level 1 cache line size ; .long ptl1iSize - Level 1 instruction cache size ; .long ptl1dSize - Level 1 data cache size @@ -871,26 +901,6 @@ initUnsupported: .align 2 processor_types: -; 750 (ver 2.2) - - .align 2 - .long 0xFFFFFFFF ; Exact match - .short PROCESSOR_VERSION_750 - .short 0x4202 - .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL2 - .long kCache32 | kHasGraphicsOps | kHasStfiwx - .long PatchExt32 - .long init750 - .long CPU_SUBTYPE_POWERPC_750 - .long 105 - .long 90 - .long 32 - .long 32*1024 - .long 32*1024 - .long 64 - .long 52 - .long 32 - ; 750CX (ver 2.x) .align 2 @@ -899,11 +909,10 @@ processor_types: .short 0x0200 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL2 .long kCache32 | kHasGraphicsOps | kHasStfiwx + .long 0 .long PatchExt32 .long init750CX .long CPU_SUBTYPE_POWERPC_750 - .long 105 - .long 90 .long 32 .long 32*1024 .long 32*1024 @@ -917,13 +926,12 @@ processor_types: .long 0xFFFF0000 ; All revisions .short PROCESSOR_VERSION_750 .short 0 - .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfThermal | pf32Byte | pfL2 + .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL2 .long kCache32 | kHasGraphicsOps | kHasStfiwx + .long 0 .long PatchExt32 .long init750 .long CPU_SUBTYPE_POWERPC_750 - .long 105 - .long 90 .long 32 .long 32*1024 .long 32*1024 @@ -939,11 +947,10 @@ processor_types: .short 0x0100 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pf32Byte | pfL2 .long kCache32 | kHasGraphicsOps | kHasStfiwx + .long pmDualPLL .long PatchExt32 .long init750FX .long CPU_SUBTYPE_POWERPC_750 - .long 105 - .long 90 .long 32 .long 32*1024 .long 32*1024 @@ -959,11 +966,10 @@ processor_types: .short 0 .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pf32Byte | pfL2 .long kCache32 | kHasGraphicsOps | kHasStfiwx + .long pmDualPLL | pmDPLLVmin .long PatchExt32 .long init750FXV2 .long CPU_SUBTYPE_POWERPC_750 - .long 105 - .long 90 .long 32 .long 32*1024 .long 32*1024 @@ -977,13 +983,12 @@ processor_types: .long 0xFFFFFFF8 ; ver 2.0 - 2.7 .short PROCESSOR_VERSION_7400 .short 0x0200 - .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pfThermal | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba + .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx + .long 0 .long PatchExt32 .long init7400v2_7 .long CPU_SUBTYPE_POWERPC_7400 - .long 105 - .long 90 .long 32 .long 32*1024 .long 32*1024 @@ -997,13 +1002,12 @@ processor_types: .long 0xFFFF0000 ; All revisions .short PROCESSOR_VERSION_7400 .short 0 - .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pfThermal | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba + .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx + .long 0 .long PatchExt32 .long init7400 .long CPU_SUBTYPE_POWERPC_7400 - .long 105 - .long 90 .long 32 .long 32*1024 .long 32*1024 @@ -1019,11 +1023,10 @@ processor_types: .short 0x1101 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx + .long 0 .long PatchExt32 .long init7410 .long CPU_SUBTYPE_POWERPC_7400 - .long 105 - .long 90 .long 32 .long 32*1024 .long 32*1024 @@ -1039,11 +1042,10 @@ processor_types: .short 0 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pf32Byte | pfL1fa | pfL2 | pfL2fa | pfHasDcba .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx + .long 0 .long PatchExt32 .long init7410 .long CPU_SUBTYPE_POWERPC_7400 - .long 105 - .long 90 .long 32 .long 32*1024 .long 32*1024 @@ -1059,11 +1061,10 @@ processor_types: .short 0x0100 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx + .long 0 .long PatchExt32 .long init7450 .long CPU_SUBTYPE_POWERPC_7450 - .long 105 - .long 90 .long 32 .long 32*1024 .long 32*1024 @@ -1079,11 +1080,10 @@ processor_types: .short 0x0200 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx + .long 0 .long PatchExt32 .long init7450 .long CPU_SUBTYPE_POWERPC_7450 - .long 105 - .long 90 .long 32 .long 32*1024 .long 32*1024 @@ -1099,11 +1099,10 @@ processor_types: .short 0 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx + .long 0 .long PatchExt32 .long init7450 .long CPU_SUBTYPE_POWERPC_7450 - .long 105 - .long 90 .long 32 .long 32*1024 .long 32*1024 @@ -1119,11 +1118,10 @@ processor_types: .short 0x0100 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx + .long 0 .long PatchExt32 .long init745X .long CPU_SUBTYPE_POWERPC_7450 - .long 105 - .long 90 .long 32 .long 32*1024 .long 32*1024 @@ -1139,11 +1137,10 @@ processor_types: .short 0x0200 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx + .long 0 .long PatchExt32 .long init745X .long CPU_SUBTYPE_POWERPC_7450 - .long 105 - .long 90 .long 32 .long 32*1024 .long 32*1024 @@ -1159,11 +1156,10 @@ processor_types: .short 0 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx + .long 0 .long PatchExt32 .long init745X .long CPU_SUBTYPE_POWERPC_7450 - .long 105 - .long 90 .long 32 .long 32*1024 .long 32*1024 @@ -1179,11 +1175,29 @@ processor_types: .short 0 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx + .long 0 + .long PatchExt32 + .long init745X + .long CPU_SUBTYPE_POWERPC_7450 + .long 32 + .long 32*1024 + .long 32*1024 + .long 64 + .long 52 + .long 36 + +; 7447A + + .align 2 + .long 0xFFFF0000 ; All revisions + .short PROCESSOR_VERSION_7447A + .short 0 + .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pf32Byte | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa | pfHasDcba + .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx + .long pmDFS .long PatchExt32 .long init745X .long CPU_SUBTYPE_POWERPC_7450 - .long 105 - .long 90 .long 32 .long 32*1024 .long 32*1024 @@ -1199,11 +1213,29 @@ processor_types: .short 0 .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pf128Byte | pf64Bit | pfL2 | pfSCOMFixUp .long kHasAltivec | k64Bit | kCache128 | kDataStreamsAvailable | kDcbtStreamsRecommended | kDcbtStreamsAvailable | kHasGraphicsOps | kHasStfiwx | kHasFsqrt + .long 0 + .long PatchLwsync + .long init970 + .long CPU_SUBTYPE_POWERPC_970 + .long 128 + .long 64*1024 + .long 32*1024 + .long 128 + .long 65 + .long 42 + +; 970FX + + .align 2 + .long 0xFFFF0000 ; All versions so far + .short PROCESSOR_VERSION_970FX + .short 0 + .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pf128Byte | pf64Bit | pfL2 + .long kHasAltivec | k64Bit | kCache128 | kDataStreamsAvailable | kDcbtStreamsRecommended | kDcbtStreamsAvailable | kHasGraphicsOps | kHasStfiwx | kHasFsqrt + .long pmPowerTune .long PatchLwsync .long init970 .long CPU_SUBTYPE_POWERPC_970 - .long 105 - .long 90 .long 128 .long 64*1024 .long 32*1024 @@ -1219,11 +1251,10 @@ processor_types: .short 0 .long pfFloat | pf32Byte .long kCache32 | kHasGraphicsOps | kHasStfiwx + .long 0 .long PatchExt32 .long initUnsupported .long CPU_SUBTYPE_POWERPC_ALL - .long 105 - .long 90 .long 32 .long 32*1024 .long 32*1024