X-Git-Url: https://git.saurik.com/apple/xnu.git/blobdiff_plain/2d21ac55c334faf3a56e5634905ed6987fc787d4..316670eb35587141e969394ae8537d66b9211e80:/osfmk/i386/rtclock.c?ds=sidebyside diff --git a/osfmk/i386/rtclock.c b/osfmk/i386/rtclock.c index bad2abbe7..8a5f8c667 100644 --- a/osfmk/i386/rtclock.c +++ b/osfmk/i386/rtclock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2000-2007 Apple Inc. All rights reserved. + * Copyright (c) 2000-2010 Apple Inc. All rights reserved. * * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ * @@ -40,7 +40,6 @@ */ #include -#include #include @@ -52,29 +51,25 @@ #include #include #include +#include #include #include #include /* for kernel_map */ -#include #include -#include -#include #include -#include #include -#include #include -#include +#include #include +#include +#include +#include #include #include #include #include #include -#include -#include - -#define NSEC_PER_HZ (NSEC_PER_SEC / 100) /* nsec per tick */ +#include #define UI_CPUFREQ_ROUNDING_FACTOR 10000000 @@ -82,56 +77,93 @@ int rtclock_config(void); int rtclock_init(void); -uint64_t rtc_decrementer_min; - -void rtclock_intr(x86_saved_state_t *regs); -static uint64_t maxDec; /* longest interval our hardware timer can handle (nsec) */ - -/* XXX this should really be in a header somewhere */ -extern clock_timer_func_t rtclock_timer_expire; +uint64_t tsc_rebase_abs_time = 0; static void rtc_set_timescale(uint64_t cycles); static uint64_t rtc_export_speed(uint64_t cycles); -extern void _rtc_nanotime_store( - uint64_t tsc, - uint64_t nsec, - uint32_t scale, - uint32_t shift, - rtc_nanotime_t *dst); - -extern uint64_t _rtc_nanotime_read( - rtc_nanotime_t *rntp, - int slow ); - -rtc_nanotime_t rtc_nanotime_info = {0,0,0,0,1,0}; - +void +rtc_timer_start(void) +{ + /* + * Force a complete re-evaluation of timer deadlines. + */ + etimer_resync_deadlines(); +} -static uint32_t -deadline_to_decrementer( - uint64_t deadline, - uint64_t now) +/* + * tsc_to_nanoseconds: + * + * Basic routine to convert a raw 64 bit TSC value to a + * 64 bit nanosecond value. The conversion is implemented + * based on the scale factor and an implicit 32 bit shift. + */ +static inline uint64_t +_tsc_to_nanoseconds(uint64_t value) { - uint64_t delta; +#if defined(__i386__) + asm volatile("movl %%edx,%%esi ;" + "mull %%ecx ;" + "movl %%edx,%%edi ;" + "movl %%esi,%%eax ;" + "mull %%ecx ;" + "addl %%edi,%%eax ;" + "adcl $0,%%edx " + : "+A" (value) + : "c" (pal_rtc_nanotime_info.scale) + : "esi", "edi"); +#elif defined(__x86_64__) + asm volatile("mul %%rcx;" + "shrq $32, %%rax;" + "shlq $32, %%rdx;" + "orq %%rdx, %%rax;" + : "=a"(value) + : "a"(value), "c"(pal_rtc_nanotime_info.scale) + : "rdx", "cc" ); +#else +#error Unsupported architecture +#endif - if (deadline <= now) - return rtc_decrementer_min; - else { - delta = deadline - now; - return MIN(MAX(rtc_decrementer_min,delta),maxDec); - } + return (value); } -void -rtc_lapic_start_ticking(void) +static inline uint32_t +_absolutetime_to_microtime(uint64_t abstime, clock_sec_t *secs, clock_usec_t *microsecs) { - x86_lcpu_t *lcpu = x86_lcpu(); + uint32_t remain; +#if defined(__i386__) + asm volatile( + "divl %3" + : "=a" (*secs), "=d" (remain) + : "A" (abstime), "r" (NSEC_PER_SEC)); + asm volatile( + "divl %3" + : "=a" (*microsecs) + : "0" (remain), "d" (0), "r" (NSEC_PER_USEC)); +#elif defined(__x86_64__) + *secs = abstime / (uint64_t)NSEC_PER_SEC; + remain = (uint32_t)(abstime % (uint64_t)NSEC_PER_SEC); + *microsecs = remain / NSEC_PER_USEC; +#else +#error Unsupported architecture +#endif + return remain; +} - /* - * Force a complete re-evaluation of timer deadlines. - */ - lcpu->rtcPop = EndOfAllTime; - etimer_resync_deadlines(); +static inline void +_absolutetime_to_nanotime(uint64_t abstime, clock_sec_t *secs, clock_usec_t *nanosecs) +{ +#if defined(__i386__) + asm volatile( + "divl %3" + : "=a" (*secs), "=d" (*nanosecs) + : "A" (abstime), "r" (NSEC_PER_SEC)); +#elif defined(__x86_64__) + *secs = abstime / (uint64_t)NSEC_PER_SEC; + *nanosecs = (clock_usec_t)(abstime % (uint64_t)NSEC_PER_SEC); +#else +#error Unsupported architecture +#endif } /* @@ -169,7 +201,7 @@ rtclock_config(void) * be guaranteed by the caller. */ static inline void -rtc_nanotime_set_commpage(rtc_nanotime_t *rntp) +rtc_nanotime_set_commpage(pal_rtc_nanotime_t *rntp) { commpage_set_nanotime(rntp->tsc_base, rntp->ns_base, rntp->scale, rntp->shift); } @@ -180,20 +212,18 @@ rtc_nanotime_set_commpage(rtc_nanotime_t *rntp) * Intialize the nanotime info from the base time. */ static inline void -_rtc_nanotime_init(rtc_nanotime_t *rntp, uint64_t base) +_rtc_nanotime_init(pal_rtc_nanotime_t *rntp, uint64_t base) { uint64_t tsc = rdtsc64(); - _rtc_nanotime_store(tsc, base, rntp->scale, rntp->shift, rntp); + _pal_rtc_nanotime_store(tsc, base, rntp->scale, rntp->shift, rntp); } static void rtc_nanotime_init(uint64_t base) { - rtc_nanotime_t *rntp = &rtc_nanotime_info; - - _rtc_nanotime_init(rntp, base); - rtc_nanotime_set_commpage(rntp); + _rtc_nanotime_init(&pal_rtc_nanotime_info, base); + rtc_nanotime_set_commpage(&pal_rtc_nanotime_info); } /* @@ -208,8 +238,7 @@ rtc_nanotime_init_commpage(void) { spl_t s = splclock(); - rtc_nanotime_set_commpage(&rtc_nanotime_info); - + rtc_nanotime_set_commpage(&pal_rtc_nanotime_info); splx(s); } @@ -225,35 +254,58 @@ rtc_nanotime_read(void) #if CONFIG_EMBEDDED if (gPEClockFrequencyInfo.timebase_frequency_hz > SLOW_TSC_THRESHOLD) - return _rtc_nanotime_read( &rtc_nanotime_info, 1 ); /* slow processor */ + return _rtc_nanotime_read(&rtc_nanotime_info, 1); /* slow processor */ else #endif - return _rtc_nanotime_read( &rtc_nanotime_info, 0 ); /* assume fast processor */ + return _rtc_nanotime_read(&pal_rtc_nanotime_info, 0); /* assume fast processor */ } /* * rtc_clock_napped: * - * Invoked from power manangement when we have awoken from a nap (C3/C4) - * during which the TSC lost counts. The nanotime data is updated according - * to the provided value which indicates the number of nanoseconds that the - * TSC was not counting. - * - * The caller must guarantee non-reentrancy. + * Invoked from power management when we exit from a low C-State (>= C4) + * and the TSC has stopped counting. The nanotime data is updated according + * to the provided value which represents the new value for nanotime. */ void -rtc_clock_napped( - uint64_t delta) +rtc_clock_napped(uint64_t base, uint64_t tsc_base) { - rtc_nanotime_t *rntp = &rtc_nanotime_info; - uint32_t generation; + pal_rtc_nanotime_t *rntp = &pal_rtc_nanotime_info; + uint64_t oldnsecs; + uint64_t newnsecs; + uint64_t tsc; assert(!ml_get_interrupts_enabled()); - generation = rntp->generation; - rntp->generation = 0; - rntp->ns_base += delta; - rntp->generation = ((generation + 1) != 0) ? (generation + 1) : 1; - rtc_nanotime_set_commpage(rntp); + tsc = rdtsc64(); + oldnsecs = rntp->ns_base + _tsc_to_nanoseconds(tsc - rntp->tsc_base); + newnsecs = base + _tsc_to_nanoseconds(tsc - tsc_base); + + /* + * Only update the base values if time using the new base values + * is later than the time using the old base values. + */ + if (oldnsecs < newnsecs) { + _pal_rtc_nanotime_store(tsc_base, base, rntp->scale, rntp->shift, rntp); + rtc_nanotime_set_commpage(rntp); + trace_set_timebases(tsc_base, base); + } +} + +/* + * Invoked from power management to correct the SFLM TSC entry drift problem: + * a small delta is added to the tsc_base. This is equivalent to nudgin time + * backwards. We require this to be on the order of a TSC quantum which won't + * cause callers of mach_absolute_time() to see time going backwards! + */ +void +rtc_clock_adjust(uint64_t tsc_base_delta) +{ + pal_rtc_nanotime_t *rntp = &pal_rtc_nanotime_info; + + assert(!ml_get_interrupts_enabled()); + assert(tsc_base_delta < 100ULL); /* i.e. it's small */ + _rtc_nanotime_adjust(tsc_base_delta, rntp); + rtc_nanotime_set_commpage(rntp); } void @@ -273,7 +325,7 @@ rtc_clock_stepped(__unused uint32_t new_frequency, /* * rtc_sleep_wakeup: * - * Invoked from power manageent when we have awoken from a sleep (S3) + * Invoked from power management when we have awoken from a sleep (S3) * and the TSC has been reset. The nanotime data is updated based on * the passed in value. * @@ -283,6 +335,9 @@ void rtc_sleep_wakeup( uint64_t base) { + /* Set fixed configuration for lapic timers */ + rtc_timer->config(); + /* * Reset nanotime. * The timestamp counter will have been reset @@ -319,22 +374,15 @@ rtclock_init(void) gPEClockFrequencyInfo.cpu_frequency_min_hz = cycles; gPEClockFrequencyInfo.cpu_frequency_max_hz = cycles; - /* - * Compute the longest interval we can represent. - */ - maxDec = tmrCvt(0x7fffffffULL, busFCvtt2n); - kprintf("maxDec: %lld\n", maxDec); - - /* Minimum interval is 1usec */ - rtc_decrementer_min = deadline_to_decrementer(NSEC_PER_USEC, 0ULL); - /* Point LAPIC interrupts to hardclock() */ - lapic_set_timer_func((i386_intr_func_t) rtclock_intr); - + rtc_timer_init(); clock_timebase_init(); ml_init_lock_timeout(); + ml_init_delay_spin_threshold(); } - rtc_lapic_start_ticking(); + /* Set fixed configuration for lapic timers */ + rtc_timer->config(); + rtc_timer_start(); return (1); } @@ -345,12 +393,18 @@ rtclock_init(void) static void rtc_set_timescale(uint64_t cycles) { - rtc_nanotime_info.scale = ((uint64_t)NSEC_PER_SEC << 32) / cycles; + pal_rtc_nanotime_t *rntp = &pal_rtc_nanotime_info; + rntp->scale = (uint32_t)(((uint64_t)NSEC_PER_SEC << 32) / cycles); +#if CONFIG_EMBEDDED if (cycles <= SLOW_TSC_THRESHOLD) - rtc_nanotime_info.shift = cycles; + rntp->shift = (uint32_t)cycles; else - rtc_nanotime_info.shift = 32; +#endif + rntp->shift = 32; + + if (tsc_rebase_abs_time == 0) + tsc_rebase_abs_time = mach_absolute_time(); rtc_nanotime_init(0); } @@ -381,33 +435,22 @@ rtc_export_speed(uint64_t cyc_per_sec) void clock_get_system_microtime( - uint32_t *secs, - uint32_t *microsecs) + clock_sec_t *secs, + clock_usec_t *microsecs) { uint64_t now = rtc_nanotime_read(); - uint32_t remain; - asm volatile( - "divl %3" - : "=a" (*secs), "=d" (remain) - : "A" (now), "r" (NSEC_PER_SEC)); - asm volatile( - "divl %3" - : "=a" (*microsecs) - : "0" (remain), "d" (0), "r" (NSEC_PER_USEC)); + _absolutetime_to_microtime(now, secs, microsecs); } void clock_get_system_nanotime( - uint32_t *secs, - uint32_t *nanosecs) + clock_sec_t *secs, + clock_nsec_t *nanosecs) { uint64_t now = rtc_nanotime_read(); - asm volatile( - "divl %3" - : "=a" (*secs), "=d" (*nanosecs) - : "A" (now), "r" (NSEC_PER_SEC)); + _absolutetime_to_nanotime(now, secs, nanosecs); } void @@ -415,24 +458,15 @@ clock_gettimeofday_set_commpage( uint64_t abstime, uint64_t epoch, uint64_t offset, - uint32_t *secs, - uint32_t *microsecs) + clock_sec_t *secs, + clock_usec_t *microsecs) { - uint64_t now = abstime; + uint64_t now = abstime + offset; uint32_t remain; - now += offset; + remain = _absolutetime_to_microtime(now, secs, microsecs); - asm volatile( - "divl %3" - : "=a" (*secs), "=d" (remain) - : "A" (now), "r" (NSEC_PER_SEC)); - asm volatile( - "divl %3" - : "=a" (*microsecs) - : "0" (remain), "d" (0), "r" (NSEC_PER_USEC)); - - *secs += epoch; + *secs += (clock_sec_t)epoch; commpage_set_timestamp(abstime - remain, *secs); } @@ -444,14 +478,6 @@ clock_timebase_info( info->numer = info->denom = 1; } -void -clock_set_timer_func( - clock_timer_func_t func) -{ - if (rtclock_timer_expire == NULL) - rtclock_timer_expire = func; -} - /* * Real-time clock device interrupt. */ @@ -461,24 +487,17 @@ rtclock_intr( { uint64_t rip; boolean_t user_mode = FALSE; - uint64_t abstime; - uint32_t latency; - x86_lcpu_t *lcpu = x86_lcpu(); assert(get_preemption_level() > 0); assert(!ml_get_interrupts_enabled()); - abstime = rtc_nanotime_read(); - latency = (uint32_t)(abstime - lcpu->rtcDeadline); - if (abstime < lcpu->rtcDeadline) - latency = 1; - if (is_saved_state64(tregs) == TRUE) { x86_saved_state64_t *regs; regs = saved_state64(tregs); - user_mode = TRUE; + if (regs->isf.cs & 0x03) + user_mode = TRUE; rip = regs->isf.rip; } else { x86_saved_state32_t *regs; @@ -490,37 +509,39 @@ rtclock_intr( rip = regs->eip; } - /* Log the interrupt service latency (-ve value expected by tool) */ - KERNEL_DEBUG_CONSTANT( - MACHDBG_CODE(DBG_MACH_EXCP_DECI, 0) | DBG_FUNC_NONE, - -latency, (uint32_t)rip, user_mode, 0, 0); - /* call the generic etimer */ etimer_intr(user_mode, rip); } + /* * Request timer pop from the hardware */ -int +uint64_t setPop( uint64_t time) { - uint64_t now; - uint32_t decr; - uint64_t count; - - now = rtc_nanotime_read(); /* The time in nanoseconds */ - decr = deadline_to_decrementer(time, now); + uint64_t now; + uint64_t pop; + + /* 0 and EndOfAllTime are special-cases for "clear the timer" */ + if (time == 0 || time == EndOfAllTime ) { + time = EndOfAllTime; + now = 0; + pop = rtc_timer->set(0, 0); + } else { + now = rtc_nanotime_read(); /* The time in nanoseconds */ + pop = rtc_timer->set(time, now); + } - count = tmrCvt(decr, busFCvtn2t); - lapic_set_timer(TRUE, one_shot, divide_by_1, (uint32_t) count); + /* Record requested and actual deadlines set */ + x86_lcpu()->rtcDeadline = time; + x86_lcpu()->rtcPop = pop; - return decr; /* Pass back what we set */ + return pop - now; } - uint64_t mach_absolute_time(void) { @@ -539,37 +560,25 @@ clock_interval_to_absolutetime_interval( void absolutetime_to_microtime( uint64_t abstime, - uint32_t *secs, - uint32_t *microsecs) + clock_sec_t *secs, + clock_usec_t *microsecs) { - uint32_t remain; - - asm volatile( - "divl %3" - : "=a" (*secs), "=d" (remain) - : "A" (abstime), "r" (NSEC_PER_SEC)); - asm volatile( - "divl %3" - : "=a" (*microsecs) - : "0" (remain), "d" (0), "r" (NSEC_PER_USEC)); + _absolutetime_to_microtime(abstime, secs, microsecs); } void absolutetime_to_nanotime( uint64_t abstime, - uint32_t *secs, - uint32_t *nanosecs) + clock_sec_t *secs, + clock_nsec_t *nanosecs) { - asm volatile( - "divl %3" - : "=a" (*secs), "=d" (*nanosecs) - : "A" (abstime), "r" (NSEC_PER_SEC)); + _absolutetime_to_nanotime(abstime, secs, nanosecs); } void nanotime_to_absolutetime( - uint32_t secs, - uint32_t nanosecs, + clock_sec_t secs, + clock_nsec_t nanosecs, uint64_t *result) { *result = ((uint64_t)secs * NSEC_PER_SEC) + nanosecs;