X-Git-Url: https://git.saurik.com/apple/xnu.git/blobdiff_plain/13f56ec4e58bf8687e2a68032c093c0213dd519b..39236c6e673c41db228275375ab7fdb0f837b292:/osfmk/i386/cpuid.h

diff --git a/osfmk/i386/cpuid.h b/osfmk/i386/cpuid.h
index bc7fae019..38b5ac7c0 100644
--- a/osfmk/i386/cpuid.h
+++ b/osfmk/i386/cpuid.h
@@ -44,6 +44,8 @@
 #define	CPUID_VID_INTEL		"GenuineIntel"
 #define	CPUID_VID_AMD		"AuthenticAMD"
 
+#define CPUID_VMM_ID_VMWARE	"VMwareVMware"
+
 #define CPUID_STRING_UNKNOWN    "Unknown CPU Typ"
 
 #define _Bit(n)			(1ULL << n)
@@ -95,6 +97,7 @@
 #define CPUID_FEATURE_SSSE3     _HBit(9)  /* Supplemental SSE3 instructions */
 #define CPUID_FEATURE_CID       _HBit(10) /* L1 Context ID */
 #define CPUID_FEATURE_SEGLIM64  _HBit(11) /* 64-bit segment limit checking */
+#define CPUID_FEATURE_FMA       _HBit(12) /* Fused-Multiply-Add support */
 #define CPUID_FEATURE_CX16      _HBit(13) /* CmpXchg16b instruction */
 #define CPUID_FEATURE_xTPR      _HBit(14) /* Send Task PRiority msgs */
 #define CPUID_FEATURE_PDCM      _HBit(15) /* Perf/Debug Capability MSR */
@@ -103,7 +106,7 @@
 #define CPUID_FEATURE_DCA       _HBit(18) /* Direct Cache Access */
 #define CPUID_FEATURE_SSE4_1    _HBit(19) /* Streaming SIMD extensions 4.1 */
 #define CPUID_FEATURE_SSE4_2    _HBit(20) /* Streaming SIMD extensions 4.2 */
-#define CPUID_FEATURE_xAPIC     _HBit(21) /* Extended APIC Mode */
+#define CPUID_FEATURE_x2APIC    _HBit(21) /* Extended APIC Mode */
 #define CPUID_FEATURE_MOVBE     _HBit(22) /* MOVBE instruction */
 #define CPUID_FEATURE_POPCNT    _HBit(23) /* POPCNT instruction */
 #define CPUID_FEATURE_TSCTMR    _HBit(24) /* TSC deadline timer */
@@ -112,8 +115,12 @@
 #define CPUID_FEATURE_OSXSAVE   _HBit(27) /* XGETBV/XSETBV instructions */
 #define CPUID_FEATURE_AVX1_0	_HBit(28) /* AVX 1.0 instructions */
 #define CPUID_FEATURE_VMM       _HBit(31) /* VMM (Hypervisor) present */
-#define CPUID_FEATURE_RDRAND	_HBit(29) /* RDRAND instruction */
-#define CPUID_FEATURE_F16C	_HBit(30) /* Float16 convert instructions */
+#define CPUID_FEATURE_SEGLIM64  _HBit(11) /* 64-bit segment limit checking */
+#define CPUID_FEATURE_PCID      _HBit(17) /* ASID-PCID support */
+#define CPUID_FEATURE_TSCTMR    _HBit(24) /* TSC deadline timer */
+#define CPUID_FEATURE_AVX1_0	_HBit(28) /* AVX 1.0 instructions */
+#define CPUID_FEATURE_F16C	_HBit(29) /* Float16 convert instructions */
+#define CPUID_FEATURE_RDRAND	_HBit(30) /* RDRAND instruction */
 
 /*
  * Leaf 7, subleaf 0 additional features.
@@ -122,6 +129,13 @@
 #define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0)	/* FS/GS base read/write */
 #define CPUID_LEAF7_FEATURE_SMEP     _Bit(7)	/* Supervisor Mode Execute Protect */
 #define CPUID_LEAF7_FEATURE_ENFSTRG  _Bit(9)	/* ENhanced Fast STRinG copy */
+#define CPUID_LEAF7_FEATURE_TSCOFF   _Bit(1)	/* TSC thread offset */
+#define CPUID_LEAF7_FEATURE_BMI1     _Bit(3)	/* Bit Manipulation Instrs, set 1 */
+#define CPUID_LEAF7_FEATURE_HLE      _Bit(4)	/* Hardware Lock Elision*/
+#define CPUID_LEAF7_FEATURE_AVX2     _Bit(5)	/* AVX2 Instructions */
+#define CPUID_LEAF7_FEATURE_BMI2     _Bit(8)	/* Bit Manipulation Instrs, set 2 */
+#define CPUID_LEAF7_FEATURE_INVPCID  _Bit(10)	/* INVPCID intruction, TDB */
+#define CPUID_LEAF7_FEATURE_RTM      _Bit(11)	/* TBD */
 
 /*
  * The CPUID_EXTFEATURE_XXX values define 64-bit values
@@ -147,20 +161,28 @@
 #define CPUID_MWAIT_EXTENSION	_Bit(0)	/* enumeration of WMAIT extensions */
 #define CPUID_MWAIT_BREAK	_Bit(1)	/* interrupts are break events	   */
 
-#define CPUID_MODEL_YONAH	0x0E
-#define CPUID_MODEL_MEROM	0x0F
-#define CPUID_MODEL_PENRYN	0x17
-#define CPUID_MODEL_NEHALEM	0x1A
-#define CPUID_MODEL_FIELDS	0x1E	/* Lynnfield, Clarksfield, Jasper */
-#define CPUID_MODEL_DALES	0x1F	/* Havendale, Auburndale */
-#define CPUID_MODEL_NEHALEM_EX	0x2E
-#define CPUID_MODEL_DALES_32NM	0x25	/* Clarkdale, Arrandale */
-#define CPUID_MODEL_WESTMERE	0x2C	/* Gulftown, Westmere-EP, Westmere-WS */
-#define CPUID_MODEL_WESTMERE_EX	0x2F
-#define CPUID_MODEL_SANDYBRIDGE	0x2A
-#define CPUID_MODEL_JAKETOWN	0x2D
-#define CPUID_MODEL_IVYBRIDGE	0x3A
+#define CPUID_MODEL_YONAH		0x0E
+#define CPUID_MODEL_MEROM		0x0F
+#define CPUID_MODEL_PENRYN		0x17
+#define CPUID_MODEL_NEHALEM		0x1A
+#define CPUID_MODEL_FIELDS		0x1E	/* Lynnfield, Clarksfield */
+#define CPUID_MODEL_DALES		0x1F	/* Havendale, Auburndale */
+#define CPUID_MODEL_NEHALEM_EX		0x2E
+#define CPUID_MODEL_DALES_32NM		0x25	/* Clarkdale, Arrandale */
+#define CPUID_MODEL_WESTMERE		0x2C	/* Gulftown, Westmere-EP/-WS */
+#define CPUID_MODEL_WESTMERE_EX		0x2F
+#define CPUID_MODEL_SANDYBRIDGE		0x2A
+#define CPUID_MODEL_JAKETOWN		0x2D
+#define CPUID_MODEL_IVYBRIDGE		0x3A
+#ifdef PRIVATE
+#define CPUID_MODEL_CRYSTALWELL		0x46
+#endif
+#define CPUID_MODEL_HASWELL		0x3C
+#define CPUID_MODEL_HASWELL_SVR		0x3F
+#define CPUID_MODEL_HASWELL_ULT		0x45
 
+#define CPUID_VMM_FAMILY_UNKNOWN	0x0
+#define CPUID_VMM_FAMILY_VMWARE		0x1
 
 #ifndef ASSEMBLER
 #include <stdint.h>
@@ -337,6 +359,15 @@ typedef struct {
 	uint32_t		cpuid_leaf7_features;
 } i386_cpu_info_t;
 
+#ifdef MACH_KERNEL_PRIVATE
+typedef struct {
+	char		cpuid_vmm_vendor[16];
+	uint32_t	cpuid_vmm_family;
+	uint32_t	cpuid_vmm_bus_frequency;
+	uint32_t	cpuid_vmm_tsc_frequency;
+} i386_vmm_info_t;
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -359,11 +390,15 @@ extern uint64_t		cpuid_leaf7_features(void);
 extern uint32_t		cpuid_family(void);
 extern uint32_t		cpuid_cpufamily(void);
 	
-extern void		cpuid_get_info(i386_cpu_info_t *info_p);
 extern i386_cpu_info_t	*cpuid_info(void);
-
 extern void		cpuid_set_info(void);
 
+#ifdef MACH_KERNEL_PRIVATE
+extern boolean_t	cpuid_vmm_present(void);
+extern i386_vmm_info_t	*cpuid_vmm_info(void);
+extern uint32_t		cpuid_vmm_family(void);
+#endif
+
 #ifdef __cplusplus
 }
 #endif