X-Git-Url: https://git.saurik.com/apple/xnu.git/blobdiff_plain/0c530ab8987f0ae6a1a3d9284f40182b88852816..2d21ac55c334faf3a56e5634905ed6987fc787d4:/osfmk/i386/perfmon.h diff --git a/osfmk/i386/perfmon.h b/osfmk/i386/perfmon.h index 3c2906b7c..b943d1817 100644 --- a/osfmk/i386/perfmon.h +++ b/osfmk/i386/perfmon.h @@ -1,23 +1,29 @@ /* * Copyright (c) 2003 Apple Computer, Inc. All rights reserved. * - * @APPLE_LICENSE_HEADER_START@ + * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ * - * The contents of this file constitute Original Code as defined in and - * are subject to the Apple Public Source License Version 1.1 (the - * "License"). You may not use this file except in compliance with the - * License. Please obtain a copy of the License at - * http://www.apple.com/publicsource and read it before using this file. + * This file contains Original Code and/or Modifications of Original Code + * as defined in and that are subject to the Apple Public Source License + * Version 2.0 (the 'License'). You may not use this file except in + * compliance with the License. The rights granted to you under the License + * may not be used to create, or enable the creation or redistribution of, + * unlawful or unlicensed copies of an Apple operating system, or to + * circumvent, violate, or enable the circumvention or violation of, any + * terms of an Apple operating system software license agreement. * - * This Original Code and all software distributed under the License are - * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * Please obtain a copy of the License at + * http://www.opensource.apple.com/apsl/ and read it before using this file. + * + * The Original Code and all software distributed under the License are + * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the - * License for the specific language governing rights and limitations - * under the License. + * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. + * Please see the License for the specific language governing rights and + * limitations under the License. * - * @APPLE_LICENSE_HEADER_END@ + * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ */ #ifndef _I386_PERFMON_H_ #define _I386_PERFMON_H_ @@ -58,30 +64,103 @@ pmc_is_available(void) #define PMC_COUNTER_COUNTER field(0,39) #define PMC_COUNTER_RESERVED field(40,64) #define PMC_COUNTER_MAX ((uint64_t) PMC_COUNTER_COUNTER) -typedef struct { +typedef union { + struct { uint64_t counter : 40; uint64_t reserved : 24; + } fld; + uint64_t u64; } pmc_counter_t; -#define PMC_COUNTER_ZERO { 0, 0 } +#define PMC_COUNTER_ZERO { .u64 = 0 } /* - * There are 2 basic flavors of PMCsL: P6 and P4/Xeon: + * There are 2 basic flavors of PMCs: P6 (or Core) and P4/Xeon: */ typedef enum { - pmc_none, + pmc_none = 0, pmc_P6, pmc_P4_Xeon, + pmc_Core, pmc_unknown } pmc_machine_t; +#define MSR_PERF_FIXED_CTR(n) (0x309 + (n)) +#define MSR_PERF_INST_RETIRED MSR_PERF_FIXED_CTR(0) +#define MSR_PERF_CPU_CLK_UNHALTED_CORE MSR_PERF_FIXED_CTR(1) +#define MSR_PERF_CPU_CLK_UNHALTED_REF MSR_PERF_FIXED_CTR(2) + +#define MSR_PERF_FIXED_CTR_CTRL (0x38d) +typedef union { + struct { + uint64_t FIXED_CTR0_enable :2; + uint64_t reserved0 :1; + uint64_t FIXED_CTR0_pmi :1; + uint64_t FIXED_CTR1_enable :2; + uint64_t reserved1 :1; + uint64_t FIXED_CTR1_pmi :1; + uint64_t FIXED_CTR2_enable :2; + uint64_t reserved2 :1; + uint64_t FIXED_CTR2_pmi :1; + } fld; + uint64_t u64; +} pmc_fixed_ctr_ctrl_t; + +#define MSR_PERF_GLOBAL_STATUS (0x38e) +typedef union { + struct { + uint64_t PMC0_overflow : 1; + uint64_t PMC1_overflow : 1; + uint64_t reserved1 : 30; + uint64_t FIXED_CTR0_overflow : 1; + uint64_t FIXED_CTR1_overflow : 1; + uint64_t FIXED_CTR2_overflow : 1; + uint64_t reserved2 : 27; + uint64_t ovf_buffer : 1; + uint64_t cond_changed : 1; + } fld; + uint64_t u64; +} pmc_global_status_t; + +#define MSR_PERF_GLOBAL_CTRL (0x38f) +typedef union { + struct { + uint64_t PMC0_enable : 1; + uint64_t PMC1_enable : 1; + uint64_t reserved1 : 30; + uint64_t FIXED_CTR0_enable : 1; + uint64_t FIXED_CTR1_enable : 1; + uint64_t FIXED_CTR2_enable : 1; + } fld; + uint64_t u64; +} pmc_global_ctrl_t; + +#define MSR_PERF_GLOBAL_OVF_CTRL (0x390) +typedef union { + struct { + uint64_t PMC0_clr_overflow : 1; + uint64_t PMC1_clr_overflow : 1; + uint64_t reserved1 : 30; + uint64_t FIXED_CTR0_clr_overflow : 1; + uint64_t FIXED_CTR1_clr_overflow : 1; + uint64_t FIXED_CTR2_clr_overflow : 1; + uint64_t reserved2 : 27; + uint64_t clr_ovf_buffer : 1; + uint64_t clr_cond_changed : 1; + } fld; + uint64_t u64; +} pmc_global_ovf_ctrl; + /* * P6 MSRs... */ #define MSR_P6_COUNTER_ADDR(n) (0x0c1 + (n)) #define MSR_P6_PES_ADDR(n) (0x186 + (n)) +#define MSR_IA32_PMC(n) (0x0c1 + (n)) +#define MSR_IA32_PERFEVTSEL(n) (0x186 + (n)) -typedef struct { +typedef union { + struct { uint64_t event_select : 8; uint64_t umask : 8; uint64_t usr : 1; @@ -93,8 +172,45 @@ typedef struct { uint64_t en : 1; uint64_t inv : 1; uint64_t cmask : 8; + } fld; + uint64_t u64; } pmc_evtsel_t; -#define PMC_EVTSEL_ZERO ((pmc_evtsel_t){ 0,0,0,0,0,0,0,0,0,0,0 }) +#define PMC_EVTSEL_ZERO { .u64 = 0ULL } + + +/* + * Non-architectural event selectors. See Vol 3b, section 18.13: + */ +#define PMC_EVTSEL_ALLCORES (bit(15)|bit(14)) +#define PMC_EVTSEL_THISCORE (bit(14)) +#define PMC_EVTSEL_ALLAGENTS (bit(14)) +#define PMC_EVTSEL_THISAGENT (0ULL) } +#define PMC_EVTSEL_PREFETCH_ALL (bit(13)|bit(12)) +#define PMC_EVTSEL_PREFETCH_HW (bit(12)) +#define PMC_EVTSEL_PREFETCH_NOHW (0ULL) +#define PMC_EVTSEL_MESI_MOD (bit(11)) +#define PMC_EVTSEL_MESI_EXCL (bit(10)) +#define PMC_EVTSEL_MESI_SHRD (bit(9)) +#define PMC_EVTSEL_MESI_INVAL (bit(8)) + +#define PMC_EVTSEL_SNOOP_HITM (bit(11)) +#define PMC_EVTSEL_SNOOP_HIT (bit(9)) +#define PMC_EVTSEL_SNOOP_CLEAN (bit(8)) +#define PMC_EVTSEL_SNOOP_CMP2I (bit(9)) +#define PMC_EVTSEL_SNOOP_CMP2S (bit(8)) + +#define PMC_CORE_ITLB_MISS_RETIRED \ + { .fld.event_select = 0xc9, .fld.umask = 0 } +#define PMC_CORE_MEM_LOAD_RETIRED_L1D_MISS \ + { .fld.event_select = 0xcb, .fld.umask = 1 } +#define PMC_CORE_MEM_LOAD_RETIRED_L1D_LINE_MISS \ + { .fld.event_select = 0xcb, .fld.umask = 2 } +#define PMC_CORE_MEM_LOAD_RETIRED_L2_MISS \ + { .fld.event_select = 0xcb, .fld.umask = 4 } +#define PMC_CORE_MEM_LOAD_RETIRED_L2_LINE_MISS \ + { .fld.event_select = 0xcb, .fld.umask = 8 } +#define PMC_CORE_MEM_LOAD_RETIRED_DTLB_MISS \ + { .fld.event_select = 0xcb, .fld.umask = 0x10 } #define MSR_P6_PERFCTR0 0 #define MSR_P6_PERFCTR1 1