X-Git-Url: https://git.saurik.com/apple/xnu.git/blobdiff_plain/0c530ab8987f0ae6a1a3d9284f40182b88852816..008676633c2ad2c325837c2b64915f7ded690a8f:/osfmk/i386/machine_check.h

diff --git a/osfmk/i386/machine_check.h b/osfmk/i386/machine_check.h
index 3ec287bbe..138122596 100644
--- a/osfmk/i386/machine_check.h
+++ b/osfmk/i386/machine_check.h
@@ -29,6 +29,10 @@
 #ifndef _I386_MACHINE_CHECK_H_
 #define _I386_MACHINE_CHECK_H_
 
+#include <stdint.h>
+
+#include <i386/cpu_data.h>
+
 /*
  * This header defines the machine check architecture for Pentium4 and Xeon.
  */
@@ -49,11 +53,12 @@ typedef union {
 	uint64_t	count			:BITS(7,0);
 	uint64_t	mcg_ctl_p		:BIT1(8);
 	uint64_t	mcg_ext_p		:BIT1(9);
-	uint64_t	reserved1		:BIT1(10);
+	uint64_t	mcg_ext_corr_err_p	:BIT1(10);
 	uint64_t	mcg_tes_p		:BIT1(11);
-	uint64_t	reserved2		:BITS(15,12);
+	uint64_t	mcg_ecms		:BIT1(12);
+	uint64_t	mcg_reserved2		:BITS(15,13);
 	uint64_t	mcg_ext_cnt		:BITS(23,16);
-	uint64_t	reserved3		:BITS(63,24);
+	uint64_t	mcg_ser_p		:BIT1(24);
      }		bits;
      uint64_t	u64;
 } ia32_mcg_cap_t;
@@ -64,7 +69,6 @@ typedef union {
 	uint64_t	ripv			:BIT1(0);
 	uint64_t	eipv			:BIT1(1);
 	uint64_t	mcip			:BIT1(2);
-	uint64_t	reserved		:BITS(61,3);
      }		bits;
      uint64_t	u64;
 } ia32_mcg_status_t;
@@ -113,7 +117,7 @@ typedef uint64_t	ia32_mci_ctl_t;
 #define IA32_MCi_CTL_ENABLE_ALL	(0xFFFFFFFFFFFFFFFFULL)
 
 typedef union {
-     struct {
+    struct {
 	uint64_t	mca_error		:BITS(15,0);
 	uint64_t	model_specific_error	:BITS(31,16);
 	uint64_t	other_information	:BITS(56,32);
@@ -124,13 +128,14 @@ typedef union {
 	uint64_t	uc			:BIT1(61);
 	uint64_t	over			:BIT1(62);
 	uint64_t	val			:BIT1(63);
-     }		bits;
-     struct {		/* Variant if threshold-based error status present: */
+    }		bits;
+    struct {		/* Variant if threshold-based error status present: */
 	uint64_t	mca_error		:BITS(15,0);
 	uint64_t	model_specific_error	:BITS(31,16);
 	uint64_t	other_information	:BITS(52,32);
 	uint64_t	threshold		:BITS(54,53);
-	uint64_t	reserved		:BITS(56,55);
+	uint64_t	ar			:BIT1(55);
+	uint64_t	s			:BIT1(56);
 	uint64_t	pcc			:BIT1(57);
 	uint64_t	addrv			:BIT1(58);
 	uint64_t	miscv			:BIT1(59);
@@ -138,8 +143,8 @@ typedef union {
 	uint64_t	uc			:BIT1(61);
 	uint64_t	over			:BIT1(62);
 	uint64_t	val			:BIT1(63);
-     }		bits_tes_p;
-     uint64_t	u64;
+    }		bits_tes_p;
+    uint64_t	u64;
 } ia32_mci_status_t;
 
 /* Values for threshold_status if mcg_tes_p == 1 and uc == 0 */
@@ -151,46 +156,11 @@ typedef union {
 typedef uint64_t	ia32_mci_addr_t;
 typedef uint64_t	ia32_mci_misc_t;
 
-
-#define IA32_MCG_EAX		(0x180)
-#define IA32_MCG_EBX		(0x181)
-#define IA32_MCG_ECX		(0x182)
-#define IA32_MCG_EDX		(0x183)
-#define IA32_MCG_ESI		(0x184)
-#define IA32_MCG_EDI		(0x185)
-#define IA32_MCG_EBP		(0x186)
-#define IA32_MCG_ESP		(0x187)
-#define IA32_MCG_EFLAGS		(0x188)
-#define IA32_MCG_EIP		(0x189)
-#define IA32_MCG_MISC		(0x18A)
-
-#define IA32_MCG_RAX		(0x180)
-#define IA32_MCG_RBX		(0x181)
-#define IA32_MCG_RCX		(0x182)
-#define IA32_MCG_RDX		(0x183)
-#define IA32_MCG_RSI		(0x184)
-#define IA32_MCG_RDI		(0x185)
-#define IA32_MCG_RBP		(0x186)
-#define IA32_MCG_RSP		(0x187)
-#define IA32_MCG_RFLAGS		(0x188)
-#define IA32_MCG_RIP		(0x189)
-#define IA32_MCG_MISC		(0x18A)
-#define IA32_MCG_RESERVED1	(0x18B)
-#define IA32_MCG_RESERVED2	(0x18C)
-#define IA32_MCG_RESERVED3	(0x18D)
-#define IA32_MCG_RESERVED4	(0x18E)
-#define IA32_MCG_RESERVED5	(0x18F)
-#define IA32_MCG_R8		(0x190)
-#define IA32_MCG_R9		(0x191)
-#define IA32_MCG_R10		(0x192)
-#define IA32_MCG_R11		(0x193)
-#define IA32_MCG_R12		(0x194)
-#define IA32_MCG_R13		(0x195)
-#define IA32_MCG_R14		(0x196)
-#define IA32_MCG_R15		(0x197)
-
-extern void	mca_cpu_init(void);
-extern void	mca_dump(void);
+extern void		mca_cpu_alloc(cpu_data_t *cdp);
+extern void		mca_cpu_init(void);
+extern void		mca_dump(void);
+extern void		mca_check_save(void);
+extern boolean_t	mca_is_cmci_present(void);
 
 #endif	/* _I386_MACHINE_CHECK_H_ */
 #endif	/* KERNEL_PRIVATE */