xnu-4570.51.1.tar.gz

[apple/xnu.git] / osfmk / i386 / cpuid.h

diff --git a/osfmk/i386/cpuid.h b/osfmk/i386/cpuid.h
index cd37a55a2612ed83bfa57daa76bcf4a599189f6a..f8e8e24c2b89c0695af0bc92efc1b9e988064dca 100644 (file)
--- a/osfmk/i386/cpuid.h
+++ b/osfmk/i386/cpuid.h
@@ -121,7 +121,7 @@
 
 /*
  * Leaf 7, subleaf 0 additional features.
- * Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
+ * Bits returned in %ebx:%ecx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
  */
 #define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0)   /* FS/GS base read/write */
 #define CPUID_LEAF7_FEATURE_TSCOFF   _Bit(1)   /* TSC thread offset */
@@ -132,7 +132,31 @@
 #define CPUID_LEAF7_FEATURE_BMI2     _Bit(8)   /* Bit Manipulation Instrs, set 2 */
 #define CPUID_LEAF7_FEATURE_ERMS     _Bit(9)   /* Enhanced Rep Movsb/Stosb */
 #define CPUID_LEAF7_FEATURE_INVPCID  _Bit(10)  /* INVPCID intruction, TDB */
-#define CPUID_LEAF7_FEATURE_RTM      _Bit(11)  /* TBD */
+#define CPUID_LEAF7_FEATURE_RTM      _Bit(11)  /* RTM */
+#define CPUID_LEAF7_FEATURE_RDSEED   _Bit(18)  /* RDSEED Instruction */
+#define CPUID_LEAF7_FEATURE_ADX      _Bit(19)  /* ADX Instructions */
+#define CPUID_LEAF7_FEATURE_SMAP     _Bit(20)  /* Supervisor Mode Access Protect */
+#define CPUID_LEAF7_FEATURE_SGX      _Bit(2)   /* Software Guard eXtensions */
+#define CPUID_LEAF7_FEATURE_PQM      _Bit(12)  /* Platform Qos Monitoring */
+#define CPUID_LEAF7_FEATURE_FPU_CSDS _Bit(13)  /* FPU CS/DS deprecation */
+#define CPUID_LEAF7_FEATURE_MPX      _Bit(14)  /* Memory Protection eXtensions */
+#define CPUID_LEAF7_FEATURE_PQE      _Bit(15)  /* Platform Qos Enforcement */
+#define CPUID_LEAF7_FEATURE_CLFSOPT  _Bit(23)  /* CLFSOPT */
+#define CPUID_LEAF7_FEATURE_IPT      _Bit(25)  /* Intel Processor Trace */
+#define CPUID_LEAF7_FEATURE_SHA      _Bit(29)  /* SHA instructions */
+#if !defined(RC_HIDE_XNU_J137)
+#define CPUID_LEAF7_FEATURE_AVX512F  _Bit(16)  /* AVX512F instructions */
+#define CPUID_LEAF7_FEATURE_AVX512DQ _Bit(17)  /* AVX512DQ instructions */
+#define CPUID_LEAF7_FEATURE_AVX512IFMA _Bit(21)        /* AVX512IFMA instructions */
+#define CPUID_LEAF7_FEATURE_AVX512CD _Bit(28)  /* AVX512CD instructions */
+#define CPUID_LEAF7_FEATURE_AVX512BW _Bit(30)  /* AVX512BW instructions */
+#define CPUID_LEAF7_FEATURE_AVX512VL _Bit(31)  /* AVX512VL instructions */
+#endif /* not RC_HIDE_XNU_J137 */
+
+#define CPUID_LEAF7_FEATURE_PREFETCHWT1 _HBit(0)/* Prefetch Write/T1 hint */
+#if !defined(RC_HIDE_XNU_J137)
+#define CPUID_LEAF7_FEATURE_AVX512VBMI  _HBit(1)/* AVX512VBMI instructions */
+#endif /* not RC_HIDE_XNU_J137 */
 
 /*
  * The CPUID_EXTFEATURE_XXX values define 64-bit values
@@ -180,8 +204,6 @@
 #define CPUID_MWAIT_EXTENSION  _Bit(0) /* enumeration of WMAIT extensions */
 #define CPUID_MWAIT_BREAK      _Bit(1) /* interrupts are break events     */
 
-#define CPUID_MODEL_YONAH              0x0E
-#define CPUID_MODEL_MEROM              0x0F
 #define CPUID_MODEL_PENRYN             0x17
 #define CPUID_MODEL_NEHALEM            0x1A
 #define CPUID_MODEL_FIELDS             0x1E    /* Lynnfield, Clarksfield */
@@ -196,8 +218,23 @@
 #define CPUID_MODEL_IVYBRIDGE_EP       0x3E
 #define CPUID_MODEL_CRYSTALWELL                0x46
 #define CPUID_MODEL_HASWELL            0x3C
-#define CPUID_MODEL_HASWELL_SVR                0x3F
+#define CPUID_MODEL_HASWELL_EP         0x3F
 #define CPUID_MODEL_HASWELL_ULT                0x45
+#define CPUID_MODEL_BROADWELL          0x3D
+#define CPUID_MODEL_BROADWELL_ULX      0x3D
+#define CPUID_MODEL_BROADWELL_ULT      0x3D
+#define CPUID_MODEL_BRYSTALWELL                0x47
+#define CPUID_MODEL_SKYLAKE            0x4E
+#define CPUID_MODEL_SKYLAKE_ULT                0x4E
+#define CPUID_MODEL_SKYLAKE_ULX                0x4E
+#define CPUID_MODEL_SKYLAKE_DT         0x5E
+#if !defined(RC_HIDE_XNU_J137)
+#define CPUID_MODEL_SKYLAKE_W          0x55
+#endif /* not RC_HIDE_XNU_J137 */
+#define CPUID_MODEL_KABYLAKE            0x8E
+#define CPUID_MODEL_KABYLAKE_ULT        0x8E
+#define CPUID_MODEL_KABYLAKE_ULX        0x8E
+#define CPUID_MODEL_KABYLAKE_DT         0x9E
 
 #define CPUID_VMM_FAMILY_UNKNOWN       0x0
 #define CPUID_VMM_FAMILY_VMWARE                0x1
@@ -302,6 +339,12 @@ typedef struct {
        uint8_t         fixed_width;
 } cpuid_arch_perf_leaf_t;
 
+/* The TSC to Core Crystal (RefCLK) Clock Information leaf */
+typedef struct {
+       uint32_t        numerator;
+       uint32_t        denominator;
+} cpuid_tsc_leaf_t;
+
 /* Physical CPU info - this is exported out of the kernel (kexts), so be wary of changes */
 typedef struct {
        char            cpuid_vendor[16];
@@ -341,7 +384,7 @@ typedef struct {
 #define cpuid_mwait_sub_Cstates                cpuid_mwait_leaf.sub_Cstates
        cpuid_thermal_leaf_t    cpuid_thermal_leaf;
        cpuid_arch_perf_leaf_t  cpuid_arch_perf_leaf;
-       cpuid_xsave_leaf_t      cpuid_xsave_leaf;
+       uint32_t        unused[4];                      /* cpuid_xsave_leaf */
 
        /* Cache details: */
        uint32_t        cpuid_cache_linesize;
@@ -375,7 +418,9 @@ typedef struct {
        cpuid_thermal_leaf_t    *cpuid_thermal_leafp;
        cpuid_arch_perf_leaf_t  *cpuid_arch_perf_leafp;
        cpuid_xsave_leaf_t      *cpuid_xsave_leafp;
-       uint32_t                cpuid_leaf7_features;
+       uint64_t                cpuid_leaf7_features;
+       cpuid_tsc_leaf_t        cpuid_tsc_leaf;
+       cpuid_xsave_leaf_t      cpuid_xsave_leaf[2];
 } i386_cpu_info_t;
 
 #ifdef MACH_KERNEL_PRIVATE