/*
- * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
+ * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
*
- * @APPLE_LICENSE_HEADER_START@
+ * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
*
- * The contents of this file constitute Original Code as defined in and
- * are subject to the Apple Public Source License Version 1.1 (the
- * "License"). You may not use this file except in compliance with the
- * License. Please obtain a copy of the License at
- * http://www.apple.com/publicsource and read it before using this file.
+ * This file contains Original Code and/or Modifications of Original Code
+ * as defined in and that are subject to the Apple Public Source License
+ * Version 2.0 (the 'License'). You may not use this file except in
+ * compliance with the License. The rights granted to you under the License
+ * may not be used to create, or enable the creation or redistribution of,
+ * unlawful or unlicensed copies of an Apple operating system, or to
+ * circumvent, violate, or enable the circumvention or violation of, any
+ * terms of an Apple operating system software license agreement.
*
- * This Original Code and all software distributed under the License are
- * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
+ * Please obtain a copy of the License at
+ * http://www.opensource.apple.com/apsl/ and read it before using this file.
+ *
+ * The Original Code and all software distributed under the License are
+ * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
- * License for the specific language governing rights and limitations
- * under the License.
+ * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
+ * Please see the License for the specific language governing rights and
+ * limitations under the License.
*
- * @APPLE_LICENSE_HEADER_END@
+ * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
*/
/*
* @OSF_COPYRIGHT@
/*
* x86 CPU identification
*
- * TODO : Add TI/Thomson processors
*/
#ifndef _MACHINE_CPUID_H_
#define _MACHINE_CPUID_H_
-#define CPUID_VID_SIZE 12
+#include <sys/appleapiopts.h>
+
+#ifdef __APPLE_API_PRIVATE
+
#define CPUID_VID_INTEL "GenuineIntel"
-#define CPUID_VID_UMC "UMC UMC UMC "
#define CPUID_VID_AMD "AuthenticAMD"
-#define CPUID_VID_CYRIX "CyrixInstead"
-#define CPUID_VID_NEXTGEN "NexGenDriven"
-
-#define CPUID_FEATURE_FPU 0x00000001 /* Floating point unit on-chip */
-#define CPUID_FEATURE_VME 0x00000002 /* Virtual Mode Extension */
-#define CPUID_FEATURE_IOB 0x00000004 /* I/O Breakpoints */
-#define CPUID_FEATURE_PSE 0x00000008 /* Page Size Extension */
-#define CPUID_FEATURE_TSC 0x00000010 /* Time Stamp Counter */
-#define CPUID_FEATURE_MSR 0x00000020 /* Model Specific Registers */
-#define CPUID_FEATURE_MCE 0x00000080 /* Machine Check Exception */
-#define CPUID_FEATURE_CX8 0x00000100 /* CMPXCHG8B */
-#define CPUID_FEATURE_APIC 0x00000200 /* On-chip APIC */
-#define CPUID_FEATURE_MTRR 0x00001000 /* Memory Type Range Register */
-#define CPUID_FEATURE_PGE 0x00002000 /* Page Global Enable */
-#define CPUID_FEATURE_MCA 0x00004000 /* Machine Check Architecture */
-#define CPUID_FEATURE_CMOV 0x00008000 /* Conditional Move Instruction */
-
-#define CPUID_TYPE_OEM 0x0 /* Original processor */
-#define CPUID_TYPE_OVERDRIVE 0x1 /* Overdrive processor */
-#define CPUID_TYPE_DUAL 0x2 /* Can be used as dual processor */
-#define CPUID_TYPE_RESERVED 0x3 /* Reserved */
-
-#define CPUID_FAMILY_386 0x3 /* Intel 386 (not part of CPUID) */
-#define CPUID_FAMILY_486 0x4 /* Intel 486 */
-#define CPUID_FAMILY_P5 0x5 /* Intel Pentium */
-#define CPUID_FAMILY_PPRO 0x6 /* Intel Pentium Pro */
-
-#define CPUID_MODEL_I386_DX 0x0 /* Intel 386 (not part of CPUID) */
-
-#define CPUID_MODEL_I486_DX 0x0 /* Intel 486DX */
-#define CPUID_MODEL_I486_DX_S 0x1 /* Intel 486DX-S */
-#define CPUID_MODEL_I486_SX 0x2 /* Intel 486SX */
-#define CPUID_MODEL_I486_DX2 0x3 /* Intel 486DX2 */
-#define CPUID_MODEL_I486_SL 0x4 /* Intel 486SL */
-#define CPUID_MODEL_I486_SX2 0x5 /* Intel 486SX2 */
-#define CPUID_MODEL_I486_DX2WB 0x7 /* Intel 486DX2WB */
-#define CPUID_MODEL_I486_DX4 0x8 /* Intel 486DX4 */
-#define CPUID_MODEL_I486_DX4WB 0x9 /* Intel 486DX4WB */
-
-#define CPUID_MODEL_AM486_DX 0x1 /* AMD 486DX */
-#define CPUID_MODEL_AM486_DX2 0x3 /* AMD 486DX2 */
-#define CPUID_MODEL_AM486_DX2WB 0x7 /* AMD 486DX2WB */
-#define CPUID_MODEL_AM486_DX4 0x8 /* AMD 486DX4 */
-#define CPUID_MODEL_AM486_DX4WB 0x9 /* AMD 486DX4WB */
-#define CPUID_MODEL_AM486_5X86 0xE /* AMD 5x86 */
-#define CPUID_MODEL_AM486_5X86WB 0xF /* AMD 5x86WB */
-
-#define CPUID_MODEL_CYRIX5X86 0x9 /* CYRIX 5X86 */
-
-#define CPUID_MODEL_UMC5SD 0x1 /* UMC U5SD */
-#define CPUID_MODEL_UMC5S 0x2 /* UMC U5S */
-#define CPUID_MODEL_UMC486_DX2 0x3 /* UMC U486_DX2 */
-#define CPUID_MODEL_UMC486_SX2 0x5 /* UMC U486_SX2 */
-
-#define CPUID_MODEL_P5A 0x0 /* Intel P5 60/66 Step A */
-#define CPUID_MODEL_P5 0x1 /* Intel P5 60/66 */
-#define CPUID_MODEL_P54 0x2 /* Intel P5 75/80/100/120/133/166 */
-#define CPUID_MODEL_P24T 0x3 /* Intel P5 Overdrive 63/83 */
-
-#define CPUID_MODEL_P6 0x1 /* Intel P6 */
-#define CPUID_MODEL_PII 0x3 /* Intel PII */
-
-#define CPUID_CACHE_SIZE 16 /* Number of descriptor vales */
-#define CPUID_CACHE_VALID 4 /* Index of descriptor validity */
-
-#define CPUID_CACHE_NULL 0x00 /* NULL */
-#define CPUID_CACHE_ITLB_4K 0x01 /* Instruction TLB, 4K pages */
-#define CPUID_CACHE_ITLB_4M 0x02 /* Instruction TLB, 4M pages */
-#define CPUID_CACHE_DTLB_4K 0x03 /* Data TLB, 4K pages */
-#define CPUID_CACHE_DTLB_4M 0x04 /* Data TLB, 4M pages */
-#define CPUID_CACHE_ICACHE_8K 0x06 /* Instruction cache, 8K */
-#define CPUID_CACHE_DCACHE_8K 0x0A /* Data cache, 8K */
-#define CPUID_CACHE_UCACHE_128K 0x41 /* Unified cache, 128K */
-#define CPUID_CACHE_UCACHE_256K 0x42 /* Unified cache, 256K */
-#define CPUID_CACHE_UCACHE_512K 0x43 /* Unified cache, 512K */
-#ifndef ASSEMBLER
-#include <mach/machine.h>
+#define CPUID_VMM_ID_VMWARE "VMwareVMware"
+
+#define CPUID_STRING_UNKNOWN "Unknown CPU Typ"
-extern unsigned int cpuid_value;
-extern unsigned char cpuid_type;
-extern unsigned char cpuid_family;
-extern unsigned char cpuid_model;
-extern unsigned char cpuid_stepping;
-extern unsigned int cpuid_feature;
-extern char cpuid_vid[];
-extern unsigned char cpuid_cache[];
+#define _Bit(n) (1ULL << n)
+#define _HBit(n) (1ULL << ((n)+32))
/*
- * Product ID arrays per vendor
+ * The CPUID_FEATURE_XXX values define 64-bit values
+ * returned in %ecx:%edx to a CPUID request with %eax of 1:
*/
-struct cpuid_product {
- unsigned char type; /* CPU type */
- unsigned char family; /* CPU family */
- unsigned char model; /* CPU model */
- unsigned int delay; /* 1MHz Delay (scale 1000) */
- unsigned int *frequency; /* Frequency array */
- char *name; /* Model name */
-};
+#define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */
+#define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */
+#define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */
+#define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */
+#define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */
+#define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */
+#define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */
+#define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */
+#define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */
+#define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */
+#define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */
+#define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */
+#define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */
+#define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */
+#define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */
+#define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */
+#define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */
+#define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */
+#define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */
+#define CPUID_FEATURE_DS _Bit(21) /* Debug Store */
+#define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */
+#define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */
+#define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */
+#define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */
+#define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */
+#define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */
+#define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */
+#define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */
+#define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */
+
+#define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */
+#define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ instruction */
+#define CPUID_FEATURE_DTES64 _HBit(2) /* 64-bit DS layout */
+#define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */
+#define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */
+#define CPUID_FEATURE_VMX _HBit(5) /* VMX */
+#define CPUID_FEATURE_SMX _HBit(6) /* SMX */
+#define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */
+#define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */
+#define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */
+#define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */
+#define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */
+#define CPUID_FEATURE_FMA _HBit(12) /* Fused-Multiply-Add support */
+#define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */
+#define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */
+#define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */
+
+#define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */
+#define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */
+#define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */
+#define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */
+#define CPUID_FEATURE_x2APIC _HBit(21) /* Extended APIC Mode */
+#define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */
+#define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */
+#define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */
+#define CPUID_FEATURE_AES _HBit(25) /* AES instructions */
+#define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */
+#define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */
+#define CPUID_FEATURE_AVX1_0 _HBit(28) /* AVX 1.0 instructions */
+#define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */
+#define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */
+#define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */
+#define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */
+#define CPUID_FEATURE_AVX1_0 _HBit(28) /* AVX 1.0 instructions */
+#define CPUID_FEATURE_F16C _HBit(29) /* Float16 convert instructions */
+#define CPUID_FEATURE_RDRAND _HBit(30) /* RDRAND instruction */
/*
- * Vendor ID structure
+ * Leaf 7, subleaf 0 additional features.
+ * Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
*/
-struct cpuid_name {
- char *name; /* Vendor ID name */
- struct cpuid_product *product; /* product array */
- unsigned int size; /* #elements in product array */
-};
+#define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0) /* FS/GS base read/write */
+#define CPUID_LEAF7_FEATURE_SMEP _Bit(7) /* Supervisor Mode Execute Protect */
+#define CPUID_LEAF7_FEATURE_ENFSTRG _Bit(9) /* ENhanced Fast STRinG copy */
+#define CPUID_LEAF7_FEATURE_TSCOFF _Bit(1) /* TSC thread offset */
+#define CPUID_LEAF7_FEATURE_BMI1 _Bit(3) /* Bit Manipulation Instrs, set 1 */
+#define CPUID_LEAF7_FEATURE_HLE _Bit(4) /* Hardware Lock Elision*/
+#define CPUID_LEAF7_FEATURE_AVX2 _Bit(5) /* AVX2 Instructions */
+#define CPUID_LEAF7_FEATURE_BMI2 _Bit(8) /* Bit Manipulation Instrs, set 2 */
+#define CPUID_LEAF7_FEATURE_INVPCID _Bit(10) /* INVPCID intruction, TDB */
+#define CPUID_LEAF7_FEATURE_RTM _Bit(11) /* TBD */
/*
- * Cache ID description structure
+ * The CPUID_EXTFEATURE_XXX values define 64-bit values
+ * returned in %ecx:%edx to a CPUID request with %eax of 0x80000001:
*/
-struct cpuid_cache_desc {
- unsigned char value; /* Descriptor value */
- char *description; /* Cache description */
-};
+#define CPUID_EXTFEATURE_SYSCALL _Bit(11) /* SYSCALL/sysret */
+#define CPUID_EXTFEATURE_XD _Bit(20) /* eXecute Disable */
+
+#define CPUID_EXTFEATURE_1GBPAGE _Bit(26) /* 1GB pages */
+#define CPUID_EXTFEATURE_RDTSCP _Bit(27) /* RDTSCP */
+#define CPUID_EXTFEATURE_EM64T _Bit(29) /* Extended Mem 64 Technology */
+
+#define CPUID_EXTFEATURE_LAHF _HBit(0) /* LAFH/SAHF instructions */
+
+/*
+ * The CPUID_EXTFEATURE_XXX values define 64-bit values
+ * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007:
+ */
+#define CPUID_EXTFEATURE_TSCI _Bit(8) /* TSC Invariant */
+
+#define CPUID_CACHE_SIZE 16 /* Number of descriptor values */
+
+#define CPUID_MWAIT_EXTENSION _Bit(0) /* enumeration of WMAIT extensions */
+#define CPUID_MWAIT_BREAK _Bit(1) /* interrupts are break events */
+
+#define CPUID_MODEL_YONAH 0x0E
+#define CPUID_MODEL_MEROM 0x0F
+#define CPUID_MODEL_PENRYN 0x17
+#define CPUID_MODEL_NEHALEM 0x1A
+#define CPUID_MODEL_FIELDS 0x1E /* Lynnfield, Clarksfield */
+#define CPUID_MODEL_DALES 0x1F /* Havendale, Auburndale */
+#define CPUID_MODEL_NEHALEM_EX 0x2E
+#define CPUID_MODEL_DALES_32NM 0x25 /* Clarkdale, Arrandale */
+#define CPUID_MODEL_WESTMERE 0x2C /* Gulftown, Westmere-EP/-WS */
+#define CPUID_MODEL_WESTMERE_EX 0x2F
+#define CPUID_MODEL_SANDYBRIDGE 0x2A
+#define CPUID_MODEL_JAKETOWN 0x2D
+#define CPUID_MODEL_IVYBRIDGE 0x3A
+#ifdef PRIVATE
+#define CPUID_MODEL_IVYBRIDGE_EP 0x3E
+#define CPUID_MODEL_CRYSTALWELL 0x46
+#endif
+#define CPUID_MODEL_HASWELL 0x3C
+#define CPUID_MODEL_HASWELL_SVR 0x3F
+#define CPUID_MODEL_HASWELL_ULT 0x45
+
+#define CPUID_VMM_FAMILY_UNKNOWN 0x0
+#define CPUID_VMM_FAMILY_VMWARE 0x1
+
+#ifndef ASSEMBLER
+#include <stdint.h>
+#include <mach/mach_types.h>
+#include <kern/kern_types.h>
+#include <mach/machine.h>
+
+
+typedef enum { eax, ebx, ecx, edx } cpuid_register_t;
+static inline void
+cpuid(uint32_t *data)
+{
+ asm("cpuid"
+ : "=a" (data[eax]),
+ "=b" (data[ebx]),
+ "=c" (data[ecx]),
+ "=d" (data[edx])
+ : "a" (data[eax]),
+ "b" (data[ebx]),
+ "c" (data[ecx]),
+ "d" (data[edx]));
+}
+
+static inline void
+do_cpuid(uint32_t selector, uint32_t *data)
+{
+ asm("cpuid"
+ : "=a" (data[0]),
+ "=b" (data[1]),
+ "=c" (data[2]),
+ "=d" (data[3])
+ : "a"(selector),
+ "b" (0),
+ "c" (0),
+ "d" (0));
+}
+
+/*
+ * Cache ID descriptor structure, used to parse CPUID leaf 2.
+ * Note: not used in kernel.
+ */
+typedef enum { Lnone, L1I, L1D, L2U, L3U, LCACHE_MAX } cache_type_t ;
+typedef struct {
+ unsigned char value; /* Descriptor value */
+ cache_type_t type; /* Cache type */
+ unsigned int size; /* Cache size */
+ unsigned int linesize; /* Cache line size */
+#ifdef KERNEL
+ const char *description; /* Cache description */
+#endif /* KERNEL */
+} cpuid_cache_desc_t;
+
+#ifdef KERNEL
+#define CACHE_DESC(value,type,size,linesize,text) \
+ { value, type, size, linesize, text }
+#else
+#define CACHE_DESC(value,type,size,linesize,text) \
+ { value, type, size, linesize }
+#endif /* KERNEL */
+
+/* Monitor/mwait Leaf: */
+typedef struct {
+ uint32_t linesize_min;
+ uint32_t linesize_max;
+ uint32_t extensions;
+ uint32_t sub_Cstates;
+} cpuid_mwait_leaf_t;
+
+/* Thermal and Power Management Leaf: */
+typedef struct {
+ boolean_t sensor;
+ boolean_t dynamic_acceleration;
+ boolean_t invariant_APIC_timer;
+ boolean_t core_power_limits;
+ boolean_t fine_grain_clock_mod;
+ boolean_t package_thermal_intr;
+ uint32_t thresholds;
+ boolean_t ACNT_MCNT;
+ boolean_t hardware_feedback;
+ boolean_t energy_policy;
+} cpuid_thermal_leaf_t;
+
+
+/* XSAVE Feature Leaf: */
+typedef struct {
+ uint32_t extended_state[4]; /* eax .. edx */
+} cpuid_xsave_leaf_t;
+
+
+/* Architectural Performance Monitoring Leaf: */
+typedef struct {
+ uint8_t version;
+ uint8_t number;
+ uint8_t width;
+ uint8_t events_number;
+ uint32_t events;
+ uint8_t fixed_number;
+ uint8_t fixed_width;
+} cpuid_arch_perf_leaf_t;
+
+/* Physical CPU info - this is exported out of the kernel (kexts), so be wary of changes */
+typedef struct {
+ char cpuid_vendor[16];
+ char cpuid_brand_string[48];
+ const char *cpuid_model_string;
+
+ cpu_type_t cpuid_type; /* this is *not* a cpu_type_t in our <mach/machine.h> */
+ uint8_t cpuid_family;
+ uint8_t cpuid_model;
+ uint8_t cpuid_extmodel;
+ uint8_t cpuid_extfamily;
+ uint8_t cpuid_stepping;
+ uint64_t cpuid_features;
+ uint64_t cpuid_extfeatures;
+ uint32_t cpuid_signature;
+ uint8_t cpuid_brand;
+ uint8_t cpuid_processor_flag;
+
+ uint32_t cache_size[LCACHE_MAX];
+ uint32_t cache_linesize;
+
+ uint8_t cache_info[64]; /* list of cache descriptors */
+
+ uint32_t cpuid_cores_per_package;
+ uint32_t cpuid_logical_per_package;
+ uint32_t cache_sharing[LCACHE_MAX];
+ uint32_t cache_partitions[LCACHE_MAX];
+
+ cpu_type_t cpuid_cpu_type; /* <mach/machine.h> */
+ cpu_subtype_t cpuid_cpu_subtype; /* <mach/machine.h> */
+
+ /* Per-vendor info */
+ cpuid_mwait_leaf_t cpuid_mwait_leaf;
+#define cpuid_mwait_linesize_max cpuid_mwait_leaf.linesize_max
+#define cpuid_mwait_linesize_min cpuid_mwait_leaf.linesize_min
+#define cpuid_mwait_extensions cpuid_mwait_leaf.extensions
+#define cpuid_mwait_sub_Cstates cpuid_mwait_leaf.sub_Cstates
+ cpuid_thermal_leaf_t cpuid_thermal_leaf;
+ cpuid_arch_perf_leaf_t cpuid_arch_perf_leaf;
+ cpuid_xsave_leaf_t cpuid_xsave_leaf;
+
+ /* Cache details: */
+ uint32_t cpuid_cache_linesize;
+ uint32_t cpuid_cache_L2_associativity;
+ uint32_t cpuid_cache_size;
+
+ /* Virtual and physical address aize: */
+ uint32_t cpuid_address_bits_physical;
+ uint32_t cpuid_address_bits_virtual;
+
+ uint32_t cpuid_microcode_version;
+
+ /* Numbers of tlbs per processor [i|d, small|large, level0|level1] */
+ uint32_t cpuid_tlb[2][2][2];
+ #define TLB_INST 0
+ #define TLB_DATA 1
+ #define TLB_SMALL 0
+ #define TLB_LARGE 1
+ uint32_t cpuid_stlb;
+
+ uint32_t core_count;
+ uint32_t thread_count;
+
+ /* Max leaf ids available from CPUID */
+ uint32_t cpuid_max_basic;
+ uint32_t cpuid_max_ext;
+
+ /* Family-specific info links */
+ uint32_t cpuid_cpufamily;
+ cpuid_mwait_leaf_t *cpuid_mwait_leafp;
+ cpuid_thermal_leaf_t *cpuid_thermal_leafp;
+ cpuid_arch_perf_leaf_t *cpuid_arch_perf_leafp;
+ cpuid_xsave_leaf_t *cpuid_xsave_leafp;
+ uint32_t cpuid_leaf7_features;
+} i386_cpu_info_t;
+
+#ifdef MACH_KERNEL_PRIVATE
+typedef struct {
+ char cpuid_vmm_vendor[16];
+ uint32_t cpuid_vmm_family;
+ uint32_t cpuid_vmm_bus_frequency;
+ uint32_t cpuid_vmm_tsc_frequency;
+} i386_vmm_info_t;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
/*
* External declarations
*/
-extern cpu_type_t cpuid_cputype(int);
-extern void cpuid_cpu_display(char *, int);
-extern void cpuid_cache_display(char *, int);
+extern cpu_type_t cpuid_cputype(void);
+extern cpu_subtype_t cpuid_cpusubtype(void);
+extern void cpuid_cpu_display(const char *);
+extern void cpuid_feature_display(const char *);
+extern void cpuid_extfeature_display(const char *);
+extern char * cpuid_get_feature_names(uint64_t, char *, unsigned);
+extern char * cpuid_get_extfeature_names(uint64_t, char *, unsigned);
+extern char * cpuid_get_leaf7_feature_names(uint64_t, char *, unsigned);
+
+extern uint64_t cpuid_features(void);
+extern uint64_t cpuid_extfeatures(void);
+extern uint64_t cpuid_leaf7_features(void);
+extern uint32_t cpuid_family(void);
+extern uint32_t cpuid_cpufamily(void);
+
+extern i386_cpu_info_t *cpuid_info(void);
+extern void cpuid_set_info(void);
+
+#ifdef MACH_KERNEL_PRIVATE
+extern boolean_t cpuid_vmm_present(void);
+extern i386_vmm_info_t *cpuid_vmm_info(void);
+extern uint32_t cpuid_vmm_family(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
#endif /* ASSEMBLER */
+
+#endif /* __APPLE_API_PRIVATE */
#endif /* _MACHINE_CPUID_H_ */
projects / apple / xnu.git / blobdiff