+typedef enum {
+ ID = 0x02,
+ VERSION = 0x03,
+ TPR = 0x08,
+ APR = 0x09,
+ PPR = 0x0A,
+ EOI = 0x0B,
+ REMOTE_READ = 0x0C,
+ LDR = 0x0D,
+ DFR = 0x0E,
+ SVR = 0x0F,
+ ISR_BASE = 0x10,
+ TMR_BASE = 0x18,
+ IRR_BASE = 0x20,
+ ERROR_STATUS = 0x28,
+ LVT_CMCI = 0x2F,
+ ICR = 0x30,
+ ICRD = 0x31,
+ LVT_TIMER = 0x32,
+ LVT_THERMAL = 0x33,
+ LVT_PERFCNT = 0x34,
+ LVT_LINT0 = 0x35,
+ LVT_LINT1 = 0x36,
+ LVT_ERROR = 0x37,
+ TIMER_INITIAL_COUNT = 0x38,
+ TIMER_CURRENT_COUNT = 0x39,
+ TIMER_DIVIDE_CONFIG = 0x3E,
+} lapic_register_t;
+
+#define LAPIC_MMIO_PBASE 0xFEE00000 /* Default physical MMIO addr */
+#define LAPIC_MMIO_VBASE lapic_vbase /* Actual virtual mapped addr */
+#define LAPIC_MSR_BASE 0x800
+
+#define LAPIC_MMIO_OFFSET(reg) (reg << 4)
+#define LAPIC_MSR_OFFSET(reg) (reg)
+
+#define LAPIC_MMIO(reg) ((volatile uint32_t *) \
+ (LAPIC_MMIO_VBASE + LAPIC_MMIO_OFFSET(reg)))
+#define LAPIC_MSR(reg) (LAPIC_MSR_BASE + LAPIC_MSR_OFFSET(reg))
+
+typedef struct {
+ void (*init) (void);
+ uint32_t (*read) (lapic_register_t);
+ void (*write)(lapic_register_t, uint32_t);
+} lapic_ops_table_t;
+extern lapic_ops_table_t *lapic_ops;
+
+#define LAPIC_WRITE(reg,val) lapic_ops->write(reg, val)
+#define LAPIC_READ(reg) lapic_ops->read(reg)
+#define LAPIC_READ_OFFSET(reg,off) LAPIC_READ((reg)+(off))
+