xnu-7195.101.1.tar.gz

[apple/xnu.git] / osfmk / i386 / trap_native.c

diff --git a/osfmk/i386/trap_native.c b/osfmk/i386/trap_native.c
index 23bda004ea63a9c2e4a01355fefb982e122ed295..33c9d9408949cdf3be1c0b4af31b2493384e12b1 100644 (file)
--- a/osfmk/i386/trap_native.c
+++ b/osfmk/i386/trap_native.c
@@ -2,7 +2,7 @@
  * Copyright (c) 2009-2012 Apple Inc. All rights reserved.
  *
  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
  * Copyright (c) 2009-2012 Apple Inc. All rights reserved.
  *
  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@

- * 
+ *

  * This file contains Original Code and/or Modifications of Original Code
  * as defined in and that are subject to the Apple Public Source License
  * Version 2.0 (the 'License'). You may not use this file except in
  * This file contains Original Code and/or Modifications of Original Code
  * as defined in and that are subject to the Apple Public Source License
  * Version 2.0 (the 'License'). You may not use this file except in


@@ -11,10 +11,10 @@
  * unlawful or unlicensed copies of an Apple operating system, or to
  * circumvent, violate, or enable the circumvention or violation of, any
  * terms of an Apple operating system software license agreement.
  * unlawful or unlicensed copies of an Apple operating system, or to
  * circumvent, violate, or enable the circumvention or violation of, any
  * terms of an Apple operating system software license agreement.

- * 
+ *

  * Please obtain a copy of the License at
  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  * Please obtain a copy of the License at
  * http://www.opensource.apple.com/apsl/ and read it before using this file.

- * 
+ *

  * The Original Code and all software distributed under the License are
  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  * The Original Code and all software distributed under the License are
  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,


@@ -22,42 +22,42 @@
  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  * Please see the License for the specific language governing rights and
  * limitations under the License.
  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  * Please see the License for the specific language governing rights and
  * limitations under the License.

- * 
+ *

  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  */
 /*
  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  */
 /*

-* @OSF_COPYRIGHT@
-*/
-/* 
-* Mach Operating System
-* Copyright (c) 1991,1990,1989,1988 Carnegie Mellon University
-* All Rights Reserved.
-* 
-* Permission to use, copy, modify and distribute this software and its
-* documentation is hereby granted, provided that both the copyright
-* notice and this permission notice appear in all copies of the
-* software, derivative works or modified versions, and any portions
-* thereof, and that both notices appear in supporting documentation.
-* 
-* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
-* CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
-* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
-* 
-* Carnegie Mellon requests users of this software to return to
-* 
-*  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
-*  School of Computer Science
-*  Carnegie Mellon University
-*  Pittsburgh PA 15213-3890
-* 
-* any improvements or extensions that they make and grant Carnegie Mellon
-* the rights to redistribute these changes.
-*/
+ * @OSF_COPYRIGHT@
+ */
+/*
+ * Mach Operating System
+ * Copyright (c) 1991,1990,1989,1988 Carnegie Mellon University
+ * All Rights Reserved.
+ *
+ * Permission to use, copy, modify and distribute this software and its
+ * documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ *
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
+ * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
+ * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
+ * Carnegie Mellon requests users of this software to return to
+ *
+ *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
+ *  School of Computer Science
+ *  Carnegie Mellon University
+ *  Pittsburgh PA 15213-3890
+ *
+ * any improvements or extensions that they make and grant Carnegie Mellon
+ * the rights to redistribute these changes.
+ */

 /*
 /*

-*/
+ */

 
 /*
 
 /*

-* Hardware trap/fault handler.
+ * Hardware trap/fault handler.

  */
 
 #include <types.h>
  */
 
 #include <types.h>


@@ -65,7 +65,7 @@
 #include <i386/trap.h>
 #include <i386/pmap.h>
 #include <i386/fpu.h>
 #include <i386/trap.h>
 #include <i386/pmap.h>
 #include <i386/fpu.h>

-#include <i386/misc_protos.h> /* panic_io_port_read() */
+#include <i386/panic_notify.h>

 
 #include <mach/exception.h>
 #include <mach/kern_return.h>
 
 #include <mach/exception.h>
 #include <mach/kern_return.h>


@@ -100,7 +100,6 @@
 
 extern void kprintf_break_lock(void);
 extern void kprint_state(x86_saved_state64_t *saved_state);
 
 extern void kprintf_break_lock(void);
 extern void kprint_state(x86_saved_state64_t *saved_state);

-void panic_64(x86_saved_state_t *, int, const char *, boolean_t);

 
 extern volatile int panic_double_fault_cpu;
 
 
 extern volatile int panic_double_fault_cpu;
 


@@ -109,7 +108,7 @@ extern volatile int panic_double_fault_cpu;
 /*
  * K64 debug - fatal handler for debug code in the trap vectors.
  */
 /*
  * K64 debug - fatal handler for debug code in the trap vectors.
  */

-extern void
+extern void __dead2

 panic_idt64(x86_saved_state_t *rsp);
 void
 panic_idt64(x86_saved_state_t *rsp)
 panic_idt64(x86_saved_state_t *rsp);
 void
 panic_idt64(x86_saved_state_t *rsp)


@@ -120,7 +119,8 @@ panic_idt64(x86_saved_state_t *rsp)
 #endif
 
 
 #endif
 
 

-void
+__dead2
+static void

 panic_64(x86_saved_state_t *sp, __unused int pc, __unused const char *msg, boolean_t do_mca_dump)
 {
        /* Set postcode (DEBUG only) */
 panic_64(x86_saved_state_t *sp, __unused int pc, __unused const char *msg, boolean_t do_mca_dump)
 {
        /* Set postcode (DEBUG only) */


@@ -130,9 +130,9 @@ panic_64(x86_saved_state_t *sp, __unused int pc, __unused const char *msg, boole
         * Issue an I/O port read if one has been requested - this is an
         * event logic analyzers can use as a trigger point.
         */
         * Issue an I/O port read if one has been requested - this is an
         * event logic analyzers can use as a trigger point.
         */

-       panic_io_port_read();
+       panic_notify();
+

 
 

-       

        /*
         * Break kprintf lock in case of recursion,
         * and record originally faulted instruction address.
        /*
         * Break kprintf lock in case of recursion,
         * and record originally faulted instruction address.


@@ -150,35 +150,40 @@ panic_64(x86_saved_state_t *sp, __unused int pc, __unused const char *msg, boole
 
        x86_saved_state64_t *regs = saved_state64(sp);
        panic("%s at 0x%016llx, registers:\n"
 
        x86_saved_state64_t *regs = saved_state64(sp);
        panic("%s at 0x%016llx, registers:\n"

-             "CR0: 0x%016lx, CR2: 0x%016lx, CR3: 0x%016lx, CR4: 0x%016lx\n"
-             "RAX: 0x%016llx, RBX: 0x%016llx, RCX: 0x%016llx, RDX: 0x%016llx\n"
-             "RSP: 0x%016llx, RBP: 0x%016llx, RSI: 0x%016llx, RDI: 0x%016llx\n"
-             "R8:  0x%016llx, R9:  0x%016llx, R10: 0x%016llx, R11: 0x%016llx\n"
-             "R12: 0x%016llx, R13: 0x%016llx, R14: 0x%016llx, R15: 0x%016llx\n"
-             "RFL: 0x%016llx, RIP: 0x%016llx, CS:  0x%016llx, SS:  0x%016llx\n"
-             "Error code: 0x%016llx%s\n",
-             msg,
-                 regs->isf.rip,
-             get_cr0(), get_cr2(), get_cr3_raw(), get_cr4(),
-             regs->rax, regs->rbx, regs->rcx, regs->rdx,
-             regs->isf.rsp, regs->rbp, regs->rsi, regs->rdi,
-             regs->r8,  regs->r9,  regs->r10, regs->r11,
-             regs->r12, regs->r13, regs->r14, regs->r15,
-             regs->isf.rflags, regs->isf.rip, regs->isf.cs & 0xFFFF,  regs->isf.ss & 0xFFFF,
-             regs->isf.err, virtualized ? " VMM" : "");
+           "CR0: 0x%016lx, CR2: 0x%016lx, CR3: 0x%016lx, CR4: 0x%016lx\n"
+           "RAX: 0x%016llx, RBX: 0x%016llx, RCX: 0x%016llx, RDX: 0x%016llx\n"
+           "RSP: 0x%016llx, RBP: 0x%016llx, RSI: 0x%016llx, RDI: 0x%016llx\n"
+           "R8:  0x%016llx, R9:  0x%016llx, R10: 0x%016llx, R11: 0x%016llx\n"
+           "R12: 0x%016llx, R13: 0x%016llx, R14: 0x%016llx, R15: 0x%016llx\n"
+           "RFL: 0x%016llx, RIP: 0x%016llx, CS:  0x%016llx, SS:  0x%016llx\n"
+           "Error code: 0x%016llx%s\n",
+           msg,
+           regs->isf.rip,
+           get_cr0(), get_cr2(), get_cr3_raw(), get_cr4(),
+           regs->rax, regs->rbx, regs->rcx, regs->rdx,
+           regs->isf.rsp, regs->rbp, regs->rsi, regs->rdi,
+           regs->r8, regs->r9, regs->r10, regs->r11,
+           regs->r12, regs->r13, regs->r14, regs->r15,
+           regs->isf.rflags, regs->isf.rip, regs->isf.cs & 0xFFFF, regs->isf.ss & 0xFFFF,
+           regs->isf.err, virtualized ? " VMM" : "");

 }
 
 void
 panic_double_fault64(x86_saved_state_t *sp)
 {
 }
 
 void
 panic_double_fault64(x86_saved_state_t *sp)
 {

-       (void)OSCompareAndSwap((UInt32) -1, (UInt32) cpu_number(), (volatile UInt32 *)&panic_double_fault_cpu);
+#if DEVELOPMENT || DEBUG
+       uint64_t frameptr = is_saved_state64(sp) ? saved_state64(sp)->rbp : saved_state32(sp)->ebp;
+       (void) traptrace_start(T_DOUBLE_FAULT, saved_state64(sp)->isf.rip, mach_absolute_time(), frameptr);
+#endif
+       (void)OSCompareAndSwap((UInt32) - 1, (UInt32) cpu_number(), (volatile UInt32 *)&panic_double_fault_cpu);

        panic_64(sp, PANIC_DOUBLE_FAULT, "Double fault", FALSE);
        panic_64(sp, PANIC_DOUBLE_FAULT, "Double fault", FALSE);

-

 }
 void
 }
 void

-

 panic_machine_check64(x86_saved_state_t *sp)
 {
 panic_machine_check64(x86_saved_state_t *sp)
 {

+#if DEVELOPMENT || DEBUG
+       uint64_t frameptr = is_saved_state64(sp) ? saved_state64(sp)->rbp : saved_state32(sp)->ebp;
+       (void) traptrace_start(T_MACHINE_CHECK, saved_state64(sp)->isf.rip, mach_absolute_time(), frameptr);
+#endif

        panic_64(sp, PANIC_MACHINE_CHECK, "Machine Check", TRUE);
        panic_64(sp, PANIC_MACHINE_CHECK, "Machine Check", TRUE);

-

 }
 }