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[apple/xnu.git] / osfmk / chud / ppc / chud_cpu_ppc.c
1 /*
2 * Copyright (c) 2003-2007 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28
29 #include <mach/mach_types.h>
30 #include <mach/mach_host.h>
31
32 #include <kern/host.h>
33 #include <kern/processor.h>
34
35 #include <chud/chud_xnu.h>
36 #include <chud/ppc/chud_spr.h>
37 #include <chud/ppc/chud_cpu_asm.h>
38 #include <ppc/machine_routines.h>
39 #include <ppc/exception.h>
40 #include <ppc/hw_perfmon.h>
41 #include <ppc/Diagnostics.h>
42
43 // the macros in proc_reg.h fail with "expression must be absolute"
44
45 #undef mtsprg
46 #undef mfsprg
47 #define mtsprg(n, reg) __asm__ volatile("mtsprg " # n ", %0" : : "r" (reg))
48 #define mfsprg(reg, n) __asm__ volatile("mfsprg %0, " # n : "=r" (reg))
49
50 #undef mtspr
51 #undef mfspr
52 #define mtspr(spr, reg) __asm__ volatile ("mtspr %0, %1" : : "n" (spr), "r" (reg))
53 #define mfspr(reg, spr) __asm__ volatile("mfspr %0, %1" : "=r" (reg) : "n" (spr));
54
55 #undef mtsr
56 #undef mfsr
57 #define mtsr(sr, reg) __asm__ volatile("sync" "@" "mtsr sr%0, %1 " "@" "isync" : : "i" (sr), "r" (reg));
58 #define mfsr(reg, sr) __asm__ volatile("mfsr %0, sr%1" : "=r" (reg) : "i" (sr));
59
60 #pragma mark **** cpu enable/disable ****
61
62 extern kern_return_t processor_start(processor_t processor); // osfmk/kern/processor.c
63 extern kern_return_t processor_exit(processor_t processor); // osfmk/kern/processor.c
64
65 __private_extern__
66 kern_return_t chudxnu_enable_cpu(int cpu, boolean_t enable)
67 {
68 chudxnu_unbind_thread(current_thread(), 0);
69
70 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
71 return KERN_FAILURE;
72 }
73
74 if((PerProcTable[cpu].ppe_vaddr != (struct per_proc_info *)NULL)
75 && cpu != master_cpu) {
76 processor_t processor = cpu_to_processor(cpu);
77
78 if(enable) {
79 return processor_start(processor);
80 } else {
81 return processor_exit(processor);
82 }
83 }
84 return KERN_FAILURE;
85 }
86
87 #pragma mark **** nap ****
88
89 __private_extern__
90 kern_return_t chudxnu_enable_cpu_nap(int cpu, boolean_t enable)
91 {
92 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
93 return KERN_FAILURE;
94 }
95
96 if(PerProcTable[cpu].ppe_vaddr != (struct per_proc_info *)NULL) {
97 ml_enable_nap(cpu, enable);
98 return KERN_SUCCESS;
99 }
100
101 return KERN_FAILURE;
102 }
103
104 __private_extern__
105 boolean_t chudxnu_cpu_nap_enabled(int cpu)
106 {
107 boolean_t prev;
108
109 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
110 cpu = 0;
111 }
112
113 prev = ml_enable_nap(cpu, TRUE);
114 ml_enable_nap(cpu, prev);
115
116 return prev;
117 }
118
119 #pragma mark **** shadowed spr ****
120
121 __private_extern__
122 kern_return_t chudxnu_set_shadowed_spr(int cpu, int spr, uint32_t val)
123 {
124 cpu_subtype_t target_cpu_subtype;
125 uint32_t available;
126 kern_return_t retval = KERN_FAILURE;
127 struct per_proc_info *per_proc;
128 boolean_t didBind = FALSE;
129
130 if(cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
131 return KERN_FAILURE;
132 }
133
134 if(cpu<0) { // cpu<0 means don't bind (current cpu)
135 cpu = chudxnu_cpu_number();
136 didBind = FALSE;
137 } else {
138 chudxnu_bind_thread(current_thread(), cpu, 0);
139 didBind = TRUE;
140 }
141
142 per_proc = PerProcTable[cpu].ppe_vaddr;
143 available = per_proc->pf.Available;
144 target_cpu_subtype = per_proc->cpu_subtype;
145
146 if(spr==chud_750_l2cr) {
147 switch(target_cpu_subtype) {
148 case CPU_SUBTYPE_POWERPC_750:
149 case CPU_SUBTYPE_POWERPC_7400:
150 case CPU_SUBTYPE_POWERPC_7450:
151 if(available & pfL2) {
152 // int enable = (val & 0x80000000) ? TRUE : FALSE;
153 // if(enable) {
154 // per_proc->pf.l2cr = val;
155 // } else {
156 // per_proc->pf.l2cr = 0;
157 // }
158 per_proc->pf.l2cr = val;
159 cacheInit();
160 // mtspr(l2cr, per_proc->pf.l2cr); // XXXXXXX why is this necessary? XXXXXXX
161 retval = KERN_SUCCESS;
162 } else {
163 retval = KERN_FAILURE;
164 }
165 break;
166 default:
167 retval = KERN_INVALID_ARGUMENT;
168 break;
169 }
170 }
171 else if(spr==chud_7450_l3cr) {
172 switch(target_cpu_subtype) {
173 case CPU_SUBTYPE_POWERPC_7450:
174 if(available & pfL3) {
175 int enable = (val & 0x80000000) ? TRUE : FALSE;
176 if(enable) {
177 per_proc->pf.l3cr = val;
178 } else {
179 per_proc->pf.l3cr = 0;
180 }
181 cacheInit();
182 retval = KERN_SUCCESS;
183 } else {
184 retval = KERN_FAILURE;
185 }
186 break;
187 default:
188 retval = KERN_INVALID_ARGUMENT;
189 break;
190 }
191 }
192 else if(spr==chud_750_hid0) {
193 switch(target_cpu_subtype) {
194 case CPU_SUBTYPE_POWERPC_750:
195 cacheInit();
196 cacheDisable(); /* disable caches */
197 mtspr(chud_750_hid0, val);
198 per_proc->pf.pfHID0 = val;
199 cacheInit(); /* reenable caches */
200 retval = KERN_SUCCESS;
201 break;
202 case CPU_SUBTYPE_POWERPC_7400:
203 case CPU_SUBTYPE_POWERPC_7450:
204 mtspr(chud_750_hid0, val);
205 per_proc->pf.pfHID0 = val;
206 retval = KERN_SUCCESS;
207 break;
208 default:
209 retval = KERN_INVALID_ARGUMENT;
210 break;
211 }
212 }
213 else if(spr==chud_750_hid1) {
214 switch(target_cpu_subtype) {
215 case CPU_SUBTYPE_POWERPC_750:
216 case CPU_SUBTYPE_POWERPC_7400:
217 case CPU_SUBTYPE_POWERPC_7450:
218 mtspr(chud_750_hid1, val);
219 per_proc->pf.pfHID1 = val;
220 retval = KERN_SUCCESS;
221 break;
222 default:
223 retval = KERN_INVALID_ARGUMENT;
224 break;
225 }
226 }
227 else if(spr==chud_750fx_hid2 && target_cpu_subtype==CPU_SUBTYPE_POWERPC_750) {
228 mtspr(chud_750fx_hid2, val);
229 per_proc->pf.pfHID2 = val;
230 retval = KERN_SUCCESS;
231 }
232 else if(spr==chud_7400_msscr0 && (target_cpu_subtype==CPU_SUBTYPE_POWERPC_7400 || target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450)) {
233 mtspr(chud_7400_msscr0, val);
234 per_proc->pf.pfMSSCR0 = val;
235 retval = KERN_SUCCESS;
236 }
237 else if(spr==chud_7400_msscr1 && (target_cpu_subtype==CPU_SUBTYPE_POWERPC_7400 || target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450)) { // called msssr0 on 7450
238 mtspr(chud_7400_msscr1, val);
239 per_proc->pf.pfMSSCR1 = val;
240 retval = KERN_SUCCESS;
241 }
242 else if(spr==chud_7450_ldstcr && target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450) {
243 mtspr(chud_7450_ldstcr, val);
244 per_proc->pf.pfLDSTCR = val;
245 retval = KERN_SUCCESS;
246 }
247 else if(spr==chud_7450_ictrl && target_cpu_subtype==CPU_SUBTYPE_POWERPC_7450) {
248 mtspr(chud_7450_ictrl, val);
249 per_proc->pf.pfICTRL = val;
250 retval = KERN_SUCCESS;
251 } else {
252 retval = KERN_INVALID_ARGUMENT;
253 }
254
255 if(didBind) {
256 chudxnu_unbind_thread(current_thread(), 0);
257 }
258
259 return retval;
260 }
261
262 __private_extern__
263 kern_return_t chudxnu_set_shadowed_spr64(int cpu, int spr, uint64_t val)
264 {
265 cpu_subtype_t target_cpu_subtype;
266 kern_return_t retval = KERN_FAILURE;
267 struct per_proc_info *per_proc;
268 boolean_t didBind = FALSE;
269
270 if(cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
271 return KERN_FAILURE;
272 }
273
274 if(cpu<0) { // cpu<0 means don't bind (current cpu)
275 cpu = chudxnu_cpu_number();
276 didBind = FALSE;
277 } else {
278 chudxnu_bind_thread(current_thread(), cpu, 0);
279 didBind = TRUE;
280 }
281
282 per_proc = PerProcTable[cpu].ppe_vaddr;
283 target_cpu_subtype = per_proc->cpu_subtype;
284
285 if(spr==chud_970_hid0) {
286 switch(target_cpu_subtype) {
287 case CPU_SUBTYPE_POWERPC_970:
288 mtspr64(chud_970_hid0, &val);
289 per_proc->pf.pfHID0 = val;
290 retval = KERN_SUCCESS;
291 break;
292 default:
293 retval = KERN_INVALID_ARGUMENT;
294 break;
295 }
296 }
297 else if(spr==chud_970_hid1) {
298 switch(target_cpu_subtype) {
299 case CPU_SUBTYPE_POWERPC_970:
300 mtspr64(chud_970_hid1, &val);
301 per_proc->pf.pfHID1 = val;
302 retval = KERN_SUCCESS;
303 break;
304 default:
305 retval = KERN_INVALID_ARGUMENT;
306 break;
307 }
308 }
309 else if(spr==chud_970_hid4) {
310 switch(target_cpu_subtype) {
311 case CPU_SUBTYPE_POWERPC_970:
312 mtspr64(chud_970_hid4, &val);
313 per_proc->pf.pfHID4 = val;
314 retval = KERN_SUCCESS;
315 break;
316 default:
317 retval = KERN_INVALID_ARGUMENT;
318 break;
319 }
320 }
321 else if(spr==chud_970_hid5) {
322 switch(target_cpu_subtype) {
323 case CPU_SUBTYPE_POWERPC_970:
324 mtspr64(chud_970_hid5, &val);
325 per_proc->pf.pfHID5 = val;
326 retval = KERN_SUCCESS;
327 break;
328 default:
329 retval = KERN_INVALID_ARGUMENT;
330 break;
331 }
332 } else {
333 retval = KERN_INVALID_ARGUMENT;
334 }
335
336 if(didBind) {
337 chudxnu_unbind_thread(current_thread(), 0);
338 }
339
340 return retval;
341 }
342
343 __private_extern__
344 uint32_t chudxnu_get_orig_cpu_l2cr(int cpu)
345 {
346 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
347 cpu = 0;
348 }
349 return PerProcTable[cpu].ppe_vaddr->pf.l2crOriginal;
350 }
351
352 __private_extern__
353 uint32_t chudxnu_get_orig_cpu_l3cr(int cpu)
354 {
355 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
356 cpu = 0;
357 }
358 return PerProcTable[cpu].ppe_vaddr->pf.l3crOriginal;
359 }
360
361 #pragma mark **** spr ****
362
363 __private_extern__
364 kern_return_t chudxnu_read_spr(int cpu, int spr, uint32_t *val_p)
365 {
366 kern_return_t retval = KERN_SUCCESS;
367 boolean_t oldlevel;
368 uint32_t val = 0xFFFFFFFF;
369
370 /* bind to requested CPU */
371 if(cpu>=0 && !(ml_at_interrupt_context() && cpu_number() == cpu)) { // cpu<0 means don't bind
372 if(chudxnu_bind_thread(current_thread(), cpu, 0)!=KERN_SUCCESS) {
373 return KERN_INVALID_ARGUMENT;
374 }
375 }
376
377 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
378
379 do {
380 /* PPC SPRs - 32-bit and 64-bit implementations */
381 if(spr==chud_ppc_srr0) { mfspr(val, chud_ppc_srr0); break; }
382 if(spr==chud_ppc_srr1) { mfspr(val, chud_ppc_srr1); break; }
383 if(spr==chud_ppc_dsisr) { mfspr(val, chud_ppc_dsisr); break; }
384 if(spr==chud_ppc_dar) { mfspr(val, chud_ppc_dar); break; }
385 if(spr==chud_ppc_dec) { mfspr(val, chud_ppc_dec); break; }
386 if(spr==chud_ppc_sdr1) { mfspr(val, chud_ppc_sdr1); break; }
387 if(spr==chud_ppc_sprg0) { mfspr(val, chud_ppc_sprg0); break; }
388 if(spr==chud_ppc_sprg1) { mfspr(val, chud_ppc_sprg1); break; }
389 if(spr==chud_ppc_sprg2) { mfspr(val, chud_ppc_sprg2); break; }
390 if(spr==chud_ppc_sprg3) { mfspr(val, chud_ppc_sprg3); break; }
391 if(spr==chud_ppc_ear) { mfspr(val, chud_ppc_ear); break; }
392 if(spr==chud_ppc_tbl) { mfspr(val, 268); break; } /* timebase consists of read registers and write registers */
393 if(spr==chud_ppc_tbu) { mfspr(val, 269); break; }
394 if(spr==chud_ppc_pvr) { mfspr(val, chud_ppc_pvr); break; }
395 if(spr==chud_ppc_ibat0u) { mfspr(val, chud_ppc_ibat0u); break; }
396 if(spr==chud_ppc_ibat0l) { mfspr(val, chud_ppc_ibat0l); break; }
397 if(spr==chud_ppc_ibat1u) { mfspr(val, chud_ppc_ibat1u); break; }
398 if(spr==chud_ppc_ibat1l) { mfspr(val, chud_ppc_ibat1l); break; }
399 if(spr==chud_ppc_ibat2u) { mfspr(val, chud_ppc_ibat2u); break; }
400 if(spr==chud_ppc_ibat2l) { mfspr(val, chud_ppc_ibat2l); break; }
401 if(spr==chud_ppc_ibat3u) { mfspr(val, chud_ppc_ibat3u); break; }
402 if(spr==chud_ppc_ibat3l) { mfspr(val, chud_ppc_ibat3l); break; }
403 if(spr==chud_ppc_dbat0u) { mfspr(val, chud_ppc_dbat0u); break; }
404 if(spr==chud_ppc_dbat0l) { mfspr(val, chud_ppc_dbat0l); break; }
405 if(spr==chud_ppc_dbat1u) { mfspr(val, chud_ppc_dbat1u); break; }
406 if(spr==chud_ppc_dbat1l) { mfspr(val, chud_ppc_dbat1l); break; }
407 if(spr==chud_ppc_dbat2u) { mfspr(val, chud_ppc_dbat2u); break; }
408 if(spr==chud_ppc_dbat2l) { mfspr(val, chud_ppc_dbat2l); break; }
409 if(spr==chud_ppc_dbat3u) { mfspr(val, chud_ppc_dbat3u); break; }
410 if(spr==chud_ppc_dbat3l) { mfspr(val, chud_ppc_dbat3l); break; }
411 if(spr==chud_ppc_dabr) { mfspr(val, chud_ppc_dabr); break; }
412 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
413 struct ppc_thread_state64 state;
414 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
415 kern_return_t kr;
416 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
417 if(KERN_SUCCESS==kr) {
418 val = state.srr1;
419 } else {
420 retval = KERN_FAILURE;
421 }
422 break;
423 }
424
425 /* PPC SPRs - 32-bit implementations */
426 if(spr==chud_ppc32_sr0) { mfsr(val, 0); break; }
427 if(spr==chud_ppc32_sr1) { mfsr(val, 1); break; }
428 if(spr==chud_ppc32_sr2) { mfsr(val, 2); break; }
429 if(spr==chud_ppc32_sr3) { mfsr(val, 3); break; }
430 if(spr==chud_ppc32_sr4) { mfsr(val, 4); break; }
431 if(spr==chud_ppc32_sr5) { mfsr(val, 5); break; }
432 if(spr==chud_ppc32_sr6) { mfsr(val, 6); break; }
433 if(spr==chud_ppc32_sr7) { mfsr(val, 7); break; }
434 if(spr==chud_ppc32_sr8) { mfsr(val, 8); break; }
435 if(spr==chud_ppc32_sr9) { mfsr(val, 9); break; }
436 if(spr==chud_ppc32_sr10) { mfsr(val, 10); break; }
437 if(spr==chud_ppc32_sr11) { mfsr(val, 11); break; }
438 if(spr==chud_ppc32_sr12) { mfsr(val, 12); break; }
439 if(spr==chud_ppc32_sr13) { mfsr(val, 13); break; }
440 if(spr==chud_ppc32_sr14) { mfsr(val, 14); break; }
441 if(spr==chud_ppc32_sr15) { mfsr(val, 15); break; }
442
443 /* PPC SPRs - 64-bit implementations */
444 if(spr==chud_ppc64_ctrl) { mfspr(val, chud_ppc64_ctrl); break; }
445
446 /* Implementation Specific SPRs */
447 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_750) {
448 if(spr==chud_750_mmcr0) { mfspr(val, chud_750_mmcr0); break; }
449 if(spr==chud_750_pmc1) { mfspr(val, chud_750_pmc1); break; }
450 if(spr==chud_750_pmc2) { mfspr(val, chud_750_pmc2); break; }
451 if(spr==chud_750_sia) { mfspr(val, chud_750_sia); break; }
452 if(spr==chud_750_mmcr1) { mfspr(val, chud_750_mmcr1); break; }
453 if(spr==chud_750_pmc3) { mfspr(val, chud_750_pmc3); break; }
454 if(spr==chud_750_pmc4) { mfspr(val, chud_750_pmc4); break; }
455 if(spr==chud_750_hid0) { mfspr(val, chud_750_hid0); break; }
456 if(spr==chud_750_hid1) { mfspr(val, chud_750_hid1); break; }
457 if(spr==chud_750_iabr) { mfspr(val, chud_750_iabr); break; }
458 if(spr==chud_750_ictc) { mfspr(val, chud_750_ictc); break; }
459 if(spr==chud_750_thrm1) { mfspr(val, chud_750_thrm1); break; }
460 if(spr==chud_750_thrm2) { mfspr(val, chud_750_thrm2); break; }
461 if(spr==chud_750_thrm3) { mfspr(val, chud_750_thrm3); break; }
462 if(spr==chud_750_l2cr) { mfspr(val, chud_750_l2cr); break; }
463
464 // 750FX only
465 if(spr==chud_750fx_ibat4u) { mfspr(val, chud_750fx_ibat4u); break; }
466 if(spr==chud_750fx_ibat4l) { mfspr(val, chud_750fx_ibat4l); break; }
467 if(spr==chud_750fx_ibat5u) { mfspr(val, chud_750fx_ibat5u); break; }
468 if(spr==chud_750fx_ibat5l) { mfspr(val, chud_750fx_ibat5l); break; }
469 if(spr==chud_750fx_ibat6u) { mfspr(val, chud_750fx_ibat6u); break; }
470 if(spr==chud_750fx_ibat6l) { mfspr(val, chud_750fx_ibat6l); break; }
471 if(spr==chud_750fx_ibat7u) { mfspr(val, chud_750fx_ibat7u); break; }
472 if(spr==chud_750fx_ibat7l) { mfspr(val, chud_750fx_ibat7l); break; }
473 if(spr==chud_750fx_dbat4u) { mfspr(val, chud_750fx_dbat4u); break; }
474 if(spr==chud_750fx_dbat4l) { mfspr(val, chud_750fx_dbat4l); break; }
475 if(spr==chud_750fx_dbat5u) { mfspr(val, chud_750fx_dbat5u); break; }
476 if(spr==chud_750fx_dbat5l) { mfspr(val, chud_750fx_dbat5l); break; }
477 if(spr==chud_750fx_dbat6u) { mfspr(val, chud_750fx_dbat6u); break; }
478 if(spr==chud_750fx_dbat6l) { mfspr(val, chud_750fx_dbat6l); break; }
479 if(spr==chud_750fx_dbat7u) { mfspr(val, chud_750fx_dbat7u); break; }
480 if(spr==chud_750fx_dbat7l) { mfspr(val, chud_750fx_dbat7l); break; }
481
482 // 750FX >= DDR2.x only
483 if(spr==chud_750fx_hid2) { mfspr(val, chud_750fx_hid2); break; }
484 }
485
486 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7400) {
487 if(spr==chud_7400_mmcr2) { mfspr(val, chud_7400_mmcr2); break; }
488 if(spr==chud_7400_bamr) { mfspr(val, chud_7400_bamr); break; }
489 if(spr==chud_7400_mmcr0) { mfspr(val, chud_7400_mmcr0); break; }
490 if(spr==chud_7400_pmc1) { mfspr(val, chud_7400_pmc1); break; }
491 if(spr==chud_7400_pmc2) { mfspr(val, chud_7400_pmc2); break; }
492 if(spr==chud_7400_siar) { mfspr(val, chud_7400_siar); break; }
493 if(spr==chud_7400_mmcr1) { mfspr(val, chud_7400_mmcr1); break; }
494 if(spr==chud_7400_pmc3) { mfspr(val, chud_7400_pmc3); break; }
495 if(spr==chud_7400_pmc4) { mfspr(val, chud_7400_pmc4); break; }
496 if(spr==chud_7400_hid0) { mfspr(val, chud_7400_hid0); break; }
497 if(spr==chud_7400_hid1) { mfspr(val, chud_7400_hid1); break; }
498 if(spr==chud_7400_iabr) { mfspr(val, chud_7400_iabr); break; }
499 if(spr==chud_7400_msscr0) { mfspr(val, chud_7400_msscr0); break; }
500 if(spr==chud_7400_msscr1) { mfspr(val, chud_7400_msscr1); break; } /* private */
501 if(spr==chud_7400_ictc) { mfspr(val, chud_7400_ictc); break; }
502 if(spr==chud_7400_thrm1) { mfspr(val, chud_7400_thrm1); break; }
503 if(spr==chud_7400_thrm2) { mfspr(val, chud_7400_thrm2); break; }
504 if(spr==chud_7400_thrm3) { mfspr(val, chud_7400_thrm3); break; }
505 if(spr==chud_7400_pir) { mfspr(val, chud_7400_pir); break; }
506 if(spr==chud_7400_l2cr) { mfspr(val, chud_7400_l2cr); break; }
507
508 // 7410 only
509 if(spr==chud_7410_l2pmcr) { mfspr(val, chud_7410_l2pmcr); break; }
510 }
511
512 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7450) {
513 if(spr==chud_7450_mmcr2) { mfspr(val, chud_7450_mmcr2); break; }
514 if(spr==chud_7450_pmc5) { mfspr(val, chud_7450_pmc5); break; }
515 if(spr==chud_7450_pmc6) { mfspr(val, chud_7450_pmc6); break; }
516 if(spr==chud_7450_bamr) { mfspr(val, chud_7450_bamr); break; }
517 if(spr==chud_7450_mmcr0) { mfspr(val, chud_7450_mmcr0); break; }
518 if(spr==chud_7450_pmc1) { mfspr(val, chud_7450_pmc1); break; }
519 if(spr==chud_7450_pmc2) { mfspr(val, chud_7450_pmc2); break; }
520 if(spr==chud_7450_siar) { mfspr(val, chud_7450_siar); break; }
521 if(spr==chud_7450_mmcr1) { mfspr(val, chud_7450_mmcr1); break; }
522 if(spr==chud_7450_pmc3) { mfspr(val, chud_7450_pmc3); break; }
523 if(spr==chud_7450_pmc4) { mfspr(val, chud_7450_pmc4); break; }
524 if(spr==chud_7450_tlbmiss) { mfspr(val, chud_7450_tlbmiss); break; }
525 if(spr==chud_7450_ptehi) { mfspr(val, chud_7450_ptehi); break; }
526 if(spr==chud_7450_ptelo) { mfspr(val, chud_7450_ptelo); break; }
527 if(spr==chud_7450_l3pm) { mfspr(val, chud_7450_l3pm); break; }
528 if(spr==chud_7450_hid0) { mfspr(val, chud_7450_hid0); break; }
529 if(spr==chud_7450_hid1) { mfspr(val, chud_7450_hid1); break; }
530 if(spr==chud_7450_iabr) { mfspr(val, chud_7450_iabr); break; }
531 if(spr==chud_7450_ldstdb) { mfspr(val, chud_7450_ldstdb); break; }
532 if(spr==chud_7450_msscr0) { mfspr(val, chud_7450_msscr0); break; }
533 if(spr==chud_7450_msssr0) { mfspr(val, chud_7450_msssr0); break; }
534 if(spr==chud_7450_ldstcr) { mfspr(val, chud_7450_ldstcr); break; }
535 if(spr==chud_7450_ictc) { mfspr(val, chud_7450_ictc); break; }
536 if(spr==chud_7450_ictrl) { mfspr(val, chud_7450_ictrl); break; }
537 if(spr==chud_7450_thrm1) { mfspr(val, chud_7450_thrm1); break; }
538 if(spr==chud_7450_thrm2) { mfspr(val, chud_7450_thrm2); break; }
539 if(spr==chud_7450_thrm3) { mfspr(val, chud_7450_thrm3); break; }
540 if(spr==chud_7450_pir) { mfspr(val, chud_7450_pir); break; }
541 if(spr==chud_7450_l2cr) { mfspr(val, chud_7450_l2cr); break; }
542 if(spr==chud_7450_l3cr) { mfspr(val, chud_7450_l3cr); break; }
543
544 // 7455/7457 only
545 if(spr==chud_7455_sprg4) { mfspr(val, chud_7455_sprg4); break; }
546 if(spr==chud_7455_sprg5) { mfspr(val, chud_7455_sprg5); break; }
547 if(spr==chud_7455_sprg6) { mfspr(val, chud_7455_sprg6); break; }
548 if(spr==chud_7455_sprg7) { mfspr(val, chud_7455_sprg7); break; }
549 if(spr==chud_7455_ibat4u) { mfspr(val, chud_7455_ibat4u); break; }
550 if(spr==chud_7455_ibat4l) { mfspr(val, chud_7455_ibat4l); break; }
551 if(spr==chud_7455_ibat5u) { mfspr(val, chud_7455_ibat5u); break; }
552 if(spr==chud_7455_ibat5l) { mfspr(val, chud_7455_ibat5l); break; }
553 if(spr==chud_7455_ibat6u) { mfspr(val, chud_7455_ibat6u); break; }
554 if(spr==chud_7455_ibat6l) { mfspr(val, chud_7455_ibat6l); break; }
555 if(spr==chud_7455_ibat7u) { mfspr(val, chud_7455_ibat7u); break; }
556 if(spr==chud_7455_ibat7l) { mfspr(val, chud_7455_ibat7l); break; }
557 if(spr==chud_7455_dbat4u) { mfspr(val, chud_7455_dbat4u); break; }
558 if(spr==chud_7455_dbat4l) { mfspr(val, chud_7455_dbat4l); break; }
559 if(spr==chud_7455_dbat5u) { mfspr(val, chud_7455_dbat5u); break; }
560 if(spr==chud_7455_dbat5l) { mfspr(val, chud_7455_dbat5l); break; }
561 if(spr==chud_7455_dbat6u) { mfspr(val, chud_7455_dbat6u); break; }
562 if(spr==chud_7455_dbat6l) { mfspr(val, chud_7455_dbat6l); break; }
563 if(spr==chud_7455_dbat7u) { mfspr(val, chud_7455_dbat7u); break; }
564 if(spr==chud_7455_dbat7l) { mfspr(val, chud_7455_dbat7l); break; }
565 }
566
567 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
568 if(spr==chud_970_pir) { mfspr(val, chud_970_pir); break; }
569 if(spr==chud_970_pmc1) { mfspr(val, chud_970_pmc1); break; }
570 if(spr==chud_970_pmc2) { mfspr(val, chud_970_pmc2); break; }
571 if(spr==chud_970_pmc3) { mfspr(val, chud_970_pmc3); break; }
572 if(spr==chud_970_pmc4) { mfspr(val, chud_970_pmc4); break; }
573 if(spr==chud_970_pmc5) { mfspr(val, chud_970_pmc5); break; }
574 if(spr==chud_970_pmc6) { mfspr(val, chud_970_pmc6); break; }
575 if(spr==chud_970_pmc7) { mfspr(val, chud_970_pmc7); break; }
576 if(spr==chud_970_pmc8) { mfspr(val, chud_970_pmc8); break; }
577 if(spr==chud_970_hdec) { mfspr(val, chud_970_hdec); break; }
578 }
579
580 /* we only get here if none of the above cases qualify */
581 retval = KERN_INVALID_ARGUMENT;
582 } while(0);
583
584 chudxnu_set_interrupts_enabled(oldlevel); /* enable interrupts */
585
586 if(cpu>=0) { // cpu<0 means don't bind
587 chudxnu_unbind_thread(current_thread(), 0);
588 }
589
590 *val_p = val;
591
592 return retval;
593 }
594
595 __private_extern__
596 kern_return_t chudxnu_read_spr64(int cpu, int spr, uint64_t *val_p)
597 {
598 kern_return_t retval = KERN_SUCCESS;
599 boolean_t oldlevel;
600
601 /* bind to requested CPU */
602 if(cpu>=0 && !(ml_at_interrupt_context() && cpu_number() == cpu)) { // cpu<0 means don't bind
603 if(chudxnu_bind_thread(current_thread(), cpu, 0)!=KERN_SUCCESS) {
604 return KERN_INVALID_ARGUMENT;
605 }
606 }
607
608 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
609
610 do {
611 /* PPC SPRs - 32-bit and 64-bit implementations */
612 if(spr==chud_ppc_srr0) { retval = mfspr64(val_p, chud_ppc_srr0); break; }
613 if(spr==chud_ppc_srr1) { retval = mfspr64(val_p, chud_ppc_srr1); break; }
614 if(spr==chud_ppc_dar) { retval = mfspr64(val_p, chud_ppc_dar); break; }
615 if(spr==chud_ppc_dsisr) { retval = mfspr64(val_p, chud_ppc_dsisr); break; }
616 if(spr==chud_ppc_sdr1) { retval = mfspr64(val_p, chud_ppc_sdr1); break; }
617 if(spr==chud_ppc_sprg0) { retval = mfspr64(val_p, chud_ppc_sprg0); break; }
618 if(spr==chud_ppc_sprg1) { retval = mfspr64(val_p, chud_ppc_sprg1); break; }
619 if(spr==chud_ppc_sprg2) { retval = mfspr64(val_p, chud_ppc_sprg2); break; }
620 if(spr==chud_ppc_sprg3) { retval = mfspr64(val_p, chud_ppc_sprg3); break; }
621 if(spr==chud_ppc_dabr) { retval = mfspr64(val_p, chud_ppc_dabr); break; }
622 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
623 struct ppc_thread_state64 state;
624 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
625 kern_return_t kr;
626 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
627 if(KERN_SUCCESS==kr) {
628 *val_p = state.srr1;
629 } else {
630 retval = KERN_FAILURE;
631 }
632 break;
633 }
634
635 /* PPC SPRs - 64-bit implementations */
636 if(spr==chud_ppc64_asr) { retval = mfspr64(val_p, chud_ppc64_asr); break; }
637 if(spr==chud_ppc64_accr) { retval = mfspr64(val_p, chud_ppc64_accr); break; }
638
639 /* Implementation Specific SPRs */
640 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
641 if(spr==chud_970_hid0) { retval = mfspr64(val_p, chud_970_hid0); break; }
642 if(spr==chud_970_hid1) { retval = mfspr64(val_p, chud_970_hid1); break; }
643 if(spr==chud_970_hid4) { retval = mfspr64(val_p, chud_970_hid4); break; }
644 if(spr==chud_970_hid5) { retval = mfspr64(val_p, chud_970_hid5); break; }
645 if(spr==chud_970_mmcr0) { retval = mfspr64(val_p, chud_970_mmcr0); break; }
646 if(spr==chud_970_mmcr1) { retval = mfspr64(val_p, chud_970_mmcr1); break; }
647 if(spr==chud_970_mmcra) { retval = mfspr64(val_p, chud_970_mmcra); break; }
648 if(spr==chud_970_siar) { retval = mfspr64(val_p, chud_970_siar); break; }
649 if(spr==chud_970_sdar) { retval = mfspr64(val_p, chud_970_sdar); break; }
650 if(spr==chud_970_imc) { retval = mfspr64(val_p, chud_970_imc); break; }
651 if(spr==chud_970_rmor) { retval = mfspr64(val_p, chud_970_rmor); break; }
652 if(spr==chud_970_hrmor) { retval = mfspr64(val_p, chud_970_hrmor); break; }
653 if(spr==chud_970_hior) { retval = mfspr64(val_p, chud_970_hior); break; }
654 if(spr==chud_970_lpidr) { retval = mfspr64(val_p, chud_970_lpidr); break; }
655 if(spr==chud_970_lpcr) { retval = mfspr64(val_p, chud_970_lpcr); break; }
656 if(spr==chud_970_dabrx) { retval = mfspr64(val_p, chud_970_dabrx); break; }
657 if(spr==chud_970_hsprg0) { retval = mfspr64(val_p, chud_970_hsprg0); break; }
658 if(spr==chud_970_hsprg1) { retval = mfspr64(val_p, chud_970_hsprg1); break; }
659 if(spr==chud_970_hsrr0) { retval = mfspr64(val_p, chud_970_hsrr0); break; }
660 if(spr==chud_970_hsrr1) { retval = mfspr64(val_p, chud_970_hsrr1); break; }
661 if(spr==chud_970_hdec) { retval = mfspr64(val_p, chud_970_hdec); break; }
662 if(spr==chud_970_trig0) { retval = mfspr64(val_p, chud_970_trig0); break; }
663 if(spr==chud_970_trig1) { retval = mfspr64(val_p, chud_970_trig1); break; }
664 if(spr==chud_970_trig2) { retval = mfspr64(val_p, chud_970_trig2); break; }
665 if(spr==chud_970_scomc) { retval = mfspr64(val_p, chud_970_scomc); break; }
666 if(spr==chud_970_scomd) { retval = mfspr64(val_p, chud_970_scomd); break; }
667 }
668
669 /* we only get here if none of the above cases qualify */
670 *val_p = 0xFFFFFFFFFFFFFFFFLL;
671 retval = KERN_INVALID_ARGUMENT;
672 } while(0);
673
674 chudxnu_set_interrupts_enabled(oldlevel); /* enable interrupts */
675
676 if(cpu>=0) { // cpu<0 means don't bind
677 chudxnu_unbind_thread(current_thread(), 0);
678 }
679
680 return retval;
681 }
682
683 __private_extern__
684 kern_return_t chudxnu_write_spr(int cpu, int spr, uint32_t val)
685 {
686 kern_return_t retval = KERN_SUCCESS;
687 boolean_t oldlevel;
688
689 /* bind to requested CPU */
690 if(cpu>=0 && !(ml_at_interrupt_context() && cpu_number() == cpu)) { // cpu<0 means don't bind
691 if(chudxnu_bind_thread(current_thread(), cpu, 0)!=KERN_SUCCESS) {
692 return KERN_INVALID_ARGUMENT;
693 }
694 }
695
696 oldlevel = chudxnu_set_interrupts_enabled(FALSE); /* disable interrupts */
697
698 do {
699 /* PPC SPRs - 32-bit and 64-bit implementations */
700 if(spr==chud_ppc_srr0) { mtspr(chud_ppc_srr0, val); break; }
701 if(spr==chud_ppc_srr1) { mtspr(chud_ppc_srr1, val); break; }
702 if(spr==chud_ppc_dsisr) { mtspr(chud_ppc_dsisr, val); break; }
703 if(spr==chud_ppc_dar) { mtspr(chud_ppc_dar, val); break; }
704 if(spr==chud_ppc_dec) { mtspr(chud_ppc_dec, val); break; }
705 if(spr==chud_ppc_sdr1) { mtspr(chud_ppc_sdr1, val); break; }
706 if(spr==chud_ppc_sprg0) { mtspr(chud_ppc_sprg0, val); break; }
707 if(spr==chud_ppc_sprg1) { mtspr(chud_ppc_sprg1, val); break; }
708 if(spr==chud_ppc_sprg2) { mtspr(chud_ppc_sprg2, val); break; }
709 if(spr==chud_ppc_sprg3) { mtspr(chud_ppc_sprg3, val); break; }
710 if(spr==chud_ppc_ear) { mtspr(chud_ppc_ear, val); break; }
711 if(spr==chud_ppc_tbl) { mtspr(284, val); break; } /* timebase consists of read registers and write registers */
712 if(spr==chud_ppc_tbu) { mtspr(285, val); break; }
713 if(spr==chud_ppc_pvr) { mtspr(chud_ppc_pvr, val); break; }
714 if(spr==chud_ppc_ibat0u) { mtspr(chud_ppc_ibat0u, val); break; }
715 if(spr==chud_ppc_ibat0l) { mtspr(chud_ppc_ibat0l, val); break; }
716 if(spr==chud_ppc_ibat1u) { mtspr(chud_ppc_ibat1u, val); break; }
717 if(spr==chud_ppc_ibat1l) { mtspr(chud_ppc_ibat1l, val); break; }
718 if(spr==chud_ppc_ibat2u) { mtspr(chud_ppc_ibat2u, val); break; }
719 if(spr==chud_ppc_ibat2l) { mtspr(chud_ppc_ibat2l, val); break; }
720 if(spr==chud_ppc_ibat3u) { mtspr(chud_ppc_ibat3u, val); break; }
721 if(spr==chud_ppc_ibat3l) { mtspr(chud_ppc_ibat3l, val); break; }
722 if(spr==chud_ppc_dbat0u) { mtspr(chud_ppc_dbat0u, val); break; }
723 if(spr==chud_ppc_dbat0l) { mtspr(chud_ppc_dbat0l, val); break; }
724 if(spr==chud_ppc_dbat1u) { mtspr(chud_ppc_dbat1u, val); break; }
725 if(spr==chud_ppc_dbat1l) { mtspr(chud_ppc_dbat1l, val); break; }
726 if(spr==chud_ppc_dbat2u) { mtspr(chud_ppc_dbat2u, val); break; }
727 if(spr==chud_ppc_dbat2l) { mtspr(chud_ppc_dbat2l, val); break; }
728 if(spr==chud_ppc_dbat3u) { mtspr(chud_ppc_dbat3u, val); break; }
729 if(spr==chud_ppc_dbat3l) { mtspr(chud_ppc_dbat3l, val); break; }
730 if(spr==chud_ppc_dabr) { mtspr(chud_ppc_dabr, val); break; }
731 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
732 struct ppc_thread_state64 state;
733 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
734 kern_return_t kr;
735 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
736 if(KERN_SUCCESS==kr) {
737 state.srr1 = val;
738 kr = chudxnu_thread_set_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, count, TRUE /* user only */);
739 if(KERN_SUCCESS!=kr) {
740 retval = KERN_FAILURE;
741 }
742 } else {
743 retval = KERN_FAILURE;
744 }
745 break;
746 }
747
748 /* PPC SPRs - 32-bit implementations */
749 if(spr==chud_ppc32_sr0) { mtsr(0, val); break; }
750 if(spr==chud_ppc32_sr1) { mtsr(1, val); break; }
751 if(spr==chud_ppc32_sr2) { mtsr(2, val); break; }
752 if(spr==chud_ppc32_sr3) { mtsr(3, val); break; }
753 if(spr==chud_ppc32_sr4) { mtsr(4, val); break; }
754 if(spr==chud_ppc32_sr5) { mtsr(5, val); break; }
755 if(spr==chud_ppc32_sr6) { mtsr(6, val); break; }
756 if(spr==chud_ppc32_sr7) { mtsr(7, val); break; }
757 if(spr==chud_ppc32_sr8) { mtsr(8, val); break; }
758 if(spr==chud_ppc32_sr9) { mtsr(9, val); break; }
759 if(spr==chud_ppc32_sr10) { mtsr(10, val); break; }
760 if(spr==chud_ppc32_sr11) { mtsr(11, val); break; }
761 if(spr==chud_ppc32_sr12) { mtsr(12, val); break; }
762 if(spr==chud_ppc32_sr13) { mtsr(13, val); break; }
763 if(spr==chud_ppc32_sr14) { mtsr(14, val); break; }
764 if(spr==chud_ppc32_sr15) { mtsr(15, val); break; }
765
766 /* Implementation Specific SPRs */
767 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_750) {
768 if(spr==chud_750_mmcr0) { mtspr(chud_750_mmcr0, val); break; }
769 if(spr==chud_750_pmc1) { mtspr(chud_750_pmc1, val); break; }
770 if(spr==chud_750_pmc2) { mtspr(chud_750_pmc2, val); break; }
771 if(spr==chud_750_sia) { mtspr(chud_750_sia, val); break; }
772 if(spr==chud_750_mmcr1) { mtspr(chud_750_mmcr1, val); break; }
773 if(spr==chud_750_pmc3) { mtspr(chud_750_pmc3, val); break; }
774 if(spr==chud_750_pmc4) { mtspr(chud_750_pmc4, val); break; }
775 if(spr==chud_750_iabr) { mtspr(chud_750_iabr, val); break; }
776 if(spr==chud_750_ictc) { mtspr(chud_750_ictc, val); break; }
777 if(spr==chud_750_thrm1) { mtspr(chud_750_thrm1, val); break; }
778 if(spr==chud_750_thrm2) { mtspr(chud_750_thrm2, val); break; }
779 if(spr==chud_750_thrm3) { mtspr(chud_750_thrm3, val); break; }
780 if(spr==chud_750_l2cr) {
781 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
782 break;
783 }
784 if(spr==chud_750_hid0) {
785 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
786 break;
787 }
788 if(spr==chud_750_hid1) {
789 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
790 break;
791 }
792
793 // 750FX only
794 if(spr==chud_750fx_ibat4u) { mtspr(chud_750fx_ibat4u, val); break; }
795 if(spr==chud_750fx_ibat4l) { mtspr(chud_750fx_ibat4l, val); break; }
796 if(spr==chud_750fx_ibat5u) { mtspr(chud_750fx_ibat5u, val); break; }
797 if(spr==chud_750fx_ibat5l) { mtspr(chud_750fx_ibat5l, val); break; }
798 if(spr==chud_750fx_ibat6u) { mtspr(chud_750fx_ibat6u, val); break; }
799 if(spr==chud_750fx_ibat6l) { mtspr(chud_750fx_ibat6l, val); break; }
800 if(spr==chud_750fx_ibat7u) { mtspr(chud_750fx_ibat7u, val); break; }
801 if(spr==chud_750fx_ibat7l) { mtspr(chud_750fx_ibat7l, val); break; }
802 if(spr==chud_750fx_dbat4u) { mtspr(chud_750fx_dbat4u, val); break; }
803 if(spr==chud_750fx_dbat4l) { mtspr(chud_750fx_dbat4l, val); break; }
804 if(spr==chud_750fx_dbat5u) { mtspr(chud_750fx_dbat5u, val); break; }
805 if(spr==chud_750fx_dbat5l) { mtspr(chud_750fx_dbat5l, val); break; }
806 if(spr==chud_750fx_dbat6u) { mtspr(chud_750fx_dbat6u, val); break; }
807 if(spr==chud_750fx_dbat6l) { mtspr(chud_750fx_dbat6l, val); break; }
808 if(spr==chud_750fx_dbat7u) { mtspr(chud_750fx_dbat7u, val); break; }
809 if(spr==chud_750fx_dbat7l) { mtspr(chud_750fx_dbat7l, val); break; }
810
811 // 750FX >= DDR2.x
812 if(spr==chud_750fx_hid2) { mtspr(chud_750fx_hid2, val); break; }
813 }
814
815 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7400) {
816 if(spr==chud_7400_mmcr2) { mtspr(chud_7400_mmcr2, val); break; }
817 if(spr==chud_7400_bamr) { mtspr(chud_7400_bamr, val); break; }
818 if(spr==chud_7400_mmcr0) { mtspr(chud_7400_mmcr0, val); break; }
819 if(spr==chud_7400_pmc1) { mtspr(chud_7400_pmc1, val); break; }
820 if(spr==chud_7400_pmc2) { mtspr(chud_7400_pmc2, val); break; }
821 if(spr==chud_7400_siar) { mtspr(chud_7400_siar, val); break; }
822 if(spr==chud_7400_mmcr1) { mtspr(chud_7400_mmcr1, val); break; }
823 if(spr==chud_7400_pmc3) { mtspr(chud_7400_pmc3, val); break; }
824 if(spr==chud_7400_pmc4) { mtspr(chud_7400_pmc4, val); break; }
825 if(spr==chud_7400_iabr) { mtspr(chud_7400_iabr, val); break; }
826 if(spr==chud_7400_ictc) { mtspr(chud_7400_ictc, val); break; }
827 if(spr==chud_7400_thrm1) { mtspr(chud_7400_thrm1, val); break; }
828 if(spr==chud_7400_thrm2) { mtspr(chud_7400_thrm2, val); break; }
829 if(spr==chud_7400_thrm3) { mtspr(chud_7400_thrm3, val); break; }
830 if(spr==chud_7400_pir) { mtspr(chud_7400_pir, val); break; }
831
832 if(spr==chud_7400_l2cr) {
833 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
834 break;
835 }
836 if(spr==chud_7400_hid0) {
837 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
838 break;
839 }
840 if(spr==chud_7400_hid1) {
841 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
842 break;
843 }
844 if(spr==chud_7400_msscr0) {
845 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
846 break;
847 }
848 if(spr==chud_7400_msscr1) { /* private */
849 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
850 break;
851 }
852
853 // 7410 only
854 if(spr==chud_7410_l2pmcr) { mtspr(chud_7410_l2pmcr, val); break; }
855 }
856
857 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_7450) {
858 if(spr==chud_7450_mmcr2) { mtspr(chud_7450_mmcr2, val); break; }
859 if(spr==chud_7450_pmc5) { mtspr(chud_7450_pmc5, val); break; }
860 if(spr==chud_7450_pmc6) { mtspr(chud_7450_pmc6, val); break; }
861 if(spr==chud_7450_bamr) { mtspr(chud_7450_bamr, val); break; }
862 if(spr==chud_7450_mmcr0) { mtspr(chud_7450_mmcr0, val); break; }
863 if(spr==chud_7450_pmc1) { mtspr(chud_7450_pmc1, val); break; }
864 if(spr==chud_7450_pmc2) { mtspr(chud_7450_pmc2, val); break; }
865 if(spr==chud_7450_siar) { mtspr(chud_7450_siar, val); break; }
866 if(spr==chud_7450_mmcr1) { mtspr(chud_7450_mmcr1, val); break; }
867 if(spr==chud_7450_pmc3) { mtspr(chud_7450_pmc3, val); break; }
868 if(spr==chud_7450_pmc4) { mtspr(chud_7450_pmc4, val); break; }
869 if(spr==chud_7450_tlbmiss) { mtspr(chud_7450_tlbmiss, val); break; }
870 if(spr==chud_7450_ptehi) { mtspr(chud_7450_ptehi, val); break; }
871 if(spr==chud_7450_ptelo) { mtspr(chud_7450_ptelo, val); break; }
872 if(spr==chud_7450_l3pm) { mtspr(chud_7450_l3pm, val); break; }
873 if(spr==chud_7450_iabr) { mtspr(chud_7450_iabr, val); break; }
874 if(spr==chud_7450_ldstdb) { mtspr(chud_7450_ldstdb, val); break; }
875 if(spr==chud_7450_ictc) { mtspr(chud_7450_ictc, val); break; }
876 if(spr==chud_7450_thrm1) { mtspr(chud_7450_thrm1, val); break; }
877 if(spr==chud_7450_thrm2) { mtspr(chud_7450_thrm2, val); break; }
878 if(spr==chud_7450_thrm3) { mtspr(chud_7450_thrm3, val); break; }
879 if(spr==chud_7450_pir) { mtspr(chud_7450_pir, val); break; }
880
881 if(spr==chud_7450_l2cr) {
882 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
883 break;
884 }
885
886 if(spr==chud_7450_l3cr) {
887 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
888 break;
889 }
890 if(spr==chud_7450_ldstcr) {
891 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
892 break;
893 }
894 if(spr==chud_7450_hid0) {
895 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
896 break;
897 }
898 if(spr==chud_7450_hid1) {
899 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
900 break;
901 }
902 if(spr==chud_7450_msscr0) {
903 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
904 break;
905 }
906 if(spr==chud_7450_msssr0) {
907 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
908 break;
909 }
910 if(spr==chud_7450_ictrl) {
911 retval = chudxnu_set_shadowed_spr(cpu, spr, val);
912 break;
913 }
914
915 // 7455/7457 only
916 if(spr==chud_7455_sprg4) { mtspr(chud_7455_sprg4, val); break; }
917 if(spr==chud_7455_sprg5) { mtspr(chud_7455_sprg5, val); break; }
918 if(spr==chud_7455_sprg6) { mtspr(chud_7455_sprg6, val); break; }
919 if(spr==chud_7455_sprg7) { mtspr(chud_7455_sprg7, val); break; }
920 if(spr==chud_7455_ibat4u) { mtspr(chud_7455_ibat4u, val); break; }
921 if(spr==chud_7455_ibat4l) { mtspr(chud_7455_ibat4l, val); break; }
922 if(spr==chud_7455_ibat5u) { mtspr(chud_7455_ibat5u, val); break; }
923 if(spr==chud_7455_ibat5l) { mtspr(chud_7455_ibat5l, val); break; }
924 if(spr==chud_7455_ibat6u) { mtspr(chud_7455_ibat6u, val); break; }
925 if(spr==chud_7455_ibat6l) { mtspr(chud_7455_ibat6l, val); break; }
926 if(spr==chud_7455_ibat7u) { mtspr(chud_7455_ibat7u, val); break; }
927 if(spr==chud_7455_ibat7l) { mtspr(chud_7455_ibat7l, val); break; }
928 if(spr==chud_7455_dbat4u) { mtspr(chud_7455_dbat4u, val); break; }
929 if(spr==chud_7455_dbat4l) { mtspr(chud_7455_dbat4l, val); break; }
930 if(spr==chud_7455_dbat5u) { mtspr(chud_7455_dbat5u, val); break; }
931 if(spr==chud_7455_dbat5l) { mtspr(chud_7455_dbat5l, val); break; }
932 if(spr==chud_7455_dbat6u) { mtspr(chud_7455_dbat6u, val); break; }
933 if(spr==chud_7455_dbat6l) { mtspr(chud_7455_dbat6l, val); break; }
934 if(spr==chud_7455_dbat7u) { mtspr(chud_7455_dbat7u, val); break; }
935 if(spr==chud_7455_dbat7l) { mtspr(chud_7455_dbat7l, val); break; }
936 }
937
938 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
939 if(spr==chud_970_pir) { mtspr(chud_970_pir, val); break; }
940 if(spr==chud_970_pmc1) { mtspr(chud_970_pmc1, val); break; }
941 if(spr==chud_970_pmc2) { mtspr(chud_970_pmc2, val); break; }
942 if(spr==chud_970_pmc3) { mtspr(chud_970_pmc3, val); break; }
943 if(spr==chud_970_pmc4) { mtspr(chud_970_pmc4, val); break; }
944 if(spr==chud_970_pmc5) { mtspr(chud_970_pmc5, val); break; }
945 if(spr==chud_970_pmc6) { mtspr(chud_970_pmc6, val); break; }
946 if(spr==chud_970_pmc7) { mtspr(chud_970_pmc7, val); break; }
947 if(spr==chud_970_pmc8) { mtspr(chud_970_pmc8, val); break; }
948 if(spr==chud_970_hdec) { mtspr(chud_970_hdec, val); break; }
949 }
950
951 /* we only get here if none of the above cases qualify */
952 retval = KERN_INVALID_ARGUMENT;
953 } while(0);
954
955 chudxnu_set_interrupts_enabled(oldlevel); /* re-enable interrupts */
956
957 if(cpu>=0) { // cpu<0 means don't bind
958 chudxnu_unbind_thread(current_thread(), 0);
959 }
960
961 return retval;
962 }
963
964 __private_extern__
965 kern_return_t chudxnu_write_spr64(int cpu, int spr, uint64_t val)
966 {
967 kern_return_t retval = KERN_SUCCESS;
968 boolean_t oldlevel;
969 uint64_t *val_p = &val;
970
971 /* bind to requested CPU */
972 if(cpu>=0 && !(ml_at_interrupt_context() && cpu_number() == cpu)) { // cpu<0 means don't bind
973 if(chudxnu_bind_thread(current_thread(), cpu, 0)!=KERN_SUCCESS) {
974 return KERN_INVALID_ARGUMENT;
975 }
976 }
977
978 oldlevel = ml_set_interrupts_enabled(FALSE); /* disable interrupts */
979
980 do {
981 /* PPC SPRs - 32-bit and 64-bit implementations */
982 if(spr==chud_ppc_srr0) { retval = mtspr64(chud_ppc_srr0, val_p); break; }
983 if(spr==chud_ppc_srr1) { retval = mtspr64(chud_ppc_srr1, val_p); break; }
984 if(spr==chud_ppc_dar) { retval = mtspr64(chud_ppc_dar, val_p); break; }
985 if(spr==chud_ppc_dsisr) { retval = mtspr64(chud_ppc_dsisr, val_p); break; }
986 if(spr==chud_ppc_sdr1) { retval = mtspr64(chud_ppc_sdr1, val_p); break; }
987 if(spr==chud_ppc_sprg0) { retval = mtspr64(chud_ppc_sprg0, val_p); break; }
988 if(spr==chud_ppc_sprg1) { retval = mtspr64(chud_ppc_sprg1, val_p); break; }
989 if(spr==chud_ppc_sprg2) { retval = mtspr64(chud_ppc_sprg2, val_p); break; }
990 if(spr==chud_ppc_sprg3) { retval = mtspr64(chud_ppc_sprg3, val_p); break; }
991 if(spr==chud_ppc_dabr) { retval = mtspr64(chud_ppc_dabr, val_p); break; }
992 if(spr==chud_ppc_msr) { /* this is the MSR for the calling process */
993 struct ppc_thread_state64 state;
994 mach_msg_type_number_t count = PPC_THREAD_STATE64_COUNT;
995 kern_return_t kr;
996 kr = chudxnu_thread_get_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, &count, TRUE /* user only */);
997 if(KERN_SUCCESS==kr) {
998 state.srr1 = val;
999 kr = chudxnu_thread_set_state(current_thread(), PPC_THREAD_STATE64, (thread_state_t)&state, count, TRUE /* user only */);
1000 if(KERN_SUCCESS!=kr) {
1001 retval = KERN_FAILURE;
1002 }
1003 } else {
1004 retval = KERN_FAILURE;
1005 }
1006 break;
1007 }
1008
1009 /* PPC SPRs - 64-bit implementations */
1010 if(spr==chud_ppc64_asr) { retval = mtspr64(chud_ppc64_asr, val_p); break; }
1011 if(spr==chud_ppc64_accr) { retval = mtspr64(chud_ppc64_accr, val_p); break; }
1012 if(spr==chud_ppc64_ctrl) { retval = mtspr64(chud_ppc64_ctrl, val_p); break; }
1013
1014 /* Implementation Specific SPRs */
1015 if(cpu_subtype()==CPU_SUBTYPE_POWERPC_970) {
1016 if(spr==chud_970_hid0) { retval = mtspr64(chud_970_hid0, val_p); break; }
1017 if(spr==chud_970_hid1) { retval = mtspr64(chud_970_hid1, val_p); break; }
1018 if(spr==chud_970_hid4) { retval = mtspr64(chud_970_hid4, val_p); break; }
1019 if(spr==chud_970_hid5) { retval = mtspr64(chud_970_hid5, val_p); break; }
1020 if(spr==chud_970_mmcr0) { retval = mtspr64(chud_970_mmcr0, val_p); break; }
1021 if(spr==chud_970_mmcr1) { retval = mtspr64(chud_970_mmcr1, val_p); break; }
1022 if(spr==chud_970_mmcra) { retval = mtspr64(chud_970_mmcra, val_p); break; }
1023 if(spr==chud_970_siar) { retval = mtspr64(chud_970_siar, val_p); break; }
1024 if(spr==chud_970_sdar) { retval = mtspr64(chud_970_sdar, val_p); break; }
1025 if(spr==chud_970_imc) { retval = mtspr64(chud_970_imc, val_p); break; }
1026
1027 if(spr==chud_970_rmor) { retval = mtspr64(chud_970_rmor, val_p); break; }
1028 if(spr==chud_970_hrmor) { retval = mtspr64(chud_970_hrmor, val_p); break; }
1029 if(spr==chud_970_hior) { retval = mtspr64(chud_970_hior, val_p); break; }
1030 if(spr==chud_970_lpidr) { retval = mtspr64(chud_970_lpidr, val_p); break; }
1031 if(spr==chud_970_lpcr) { retval = mtspr64(chud_970_lpcr, val_p); break; }
1032 if(spr==chud_970_dabrx) { retval = mtspr64(chud_970_dabrx, val_p); break; }
1033
1034 if(spr==chud_970_hsprg0) { retval = mtspr64(chud_970_hsprg0, val_p); break; }
1035 if(spr==chud_970_hsprg1) { retval = mtspr64(chud_970_hsprg1, val_p); break; }
1036 if(spr==chud_970_hsrr0) { retval = mtspr64(chud_970_hsrr0, val_p); break; }
1037 if(spr==chud_970_hsrr1) { retval = mtspr64(chud_970_hsrr1, val_p); break; }
1038 if(spr==chud_970_hdec) { retval = mtspr64(chud_970_hdec, val_p); break; }
1039 if(spr==chud_970_trig0) { retval = mtspr64(chud_970_trig0, val_p); break; }
1040 if(spr==chud_970_trig1) { retval = mtspr64(chud_970_trig1, val_p); break; }
1041 if(spr==chud_970_trig2) { retval = mtspr64(chud_970_trig2, val_p); break; }
1042 if(spr==chud_970_scomc) { retval = mtspr64(chud_970_scomc, val_p); break; }
1043 if(spr==chud_970_scomd) { retval = mtspr64(chud_970_scomd, val_p); break; }
1044
1045 if(spr==chud_970_hid0) {
1046 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1047 break;
1048 }
1049
1050 if(spr==chud_970_hid1) {
1051 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1052 break;
1053 }
1054
1055 if(spr==chud_970_hid4) {
1056 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1057 break;
1058 }
1059
1060 if(spr==chud_970_hid5) {
1061 retval = chudxnu_set_shadowed_spr64(cpu, spr, val);
1062 break;
1063 }
1064
1065 }
1066
1067 /* we only get here if none of the above cases qualify */
1068 retval = KERN_INVALID_ARGUMENT;
1069 } while(0);
1070
1071 chudxnu_set_interrupts_enabled(oldlevel); /* re-enable interrupts */
1072
1073 if(cpu>=0) { // cpu<0 means don't bind
1074 chudxnu_unbind_thread(current_thread(), 0);
1075 }
1076
1077 return retval;
1078 }
1079
1080 #pragma mark **** perfmon facility ****
1081
1082 __private_extern__
1083 kern_return_t chudxnu_perfmon_acquire_facility(task_t task)
1084 {
1085 return perfmon_acquire_facility(task);
1086 }
1087
1088 __private_extern__
1089 kern_return_t chudxnu_perfmon_release_facility(task_t task)
1090 {
1091 return perfmon_release_facility(task);
1092 }
1093
1094 #pragma mark **** rupt counters ****
1095
1096 __private_extern__
1097 kern_return_t chudxnu_get_cpu_interrupt_counters(int cpu, rupt_counters_t *rupts)
1098 {
1099 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
1100 return KERN_FAILURE;
1101 }
1102
1103 if(rupts) {
1104 boolean_t oldlevel = ml_set_interrupts_enabled(FALSE);
1105 struct per_proc_info *per_proc;
1106
1107 per_proc = PerProcTable[cpu].ppe_vaddr;
1108 rupts->hwResets = per_proc->hwCtr.hwResets;
1109 rupts->hwMachineChecks = per_proc->hwCtr.hwMachineChecks;
1110 rupts->hwDSIs = per_proc->hwCtr.hwDSIs;
1111 rupts->hwISIs = per_proc->hwCtr.hwISIs;
1112 rupts->hwExternals = per_proc->hwCtr.hwExternals;
1113 rupts->hwAlignments = per_proc->hwCtr.hwAlignments;
1114 rupts->hwPrograms = per_proc->hwCtr.hwPrograms;
1115 rupts->hwFloatPointUnavailable = per_proc->hwCtr.hwFloatPointUnavailable;
1116 rupts->hwDecrementers = per_proc->hwCtr.hwDecrementers;
1117 rupts->hwIOErrors = per_proc->hwCtr.hwIOErrors;
1118 rupts->hwSystemCalls = per_proc->hwCtr.hwSystemCalls;
1119 rupts->hwTraces = per_proc->hwCtr.hwTraces;
1120 rupts->hwFloatingPointAssists = per_proc->hwCtr.hwFloatingPointAssists;
1121 rupts->hwPerformanceMonitors = per_proc->hwCtr.hwPerformanceMonitors;
1122 rupts->hwAltivecs = per_proc->hwCtr.hwAltivecs;
1123 rupts->hwInstBreakpoints = per_proc->hwCtr.hwInstBreakpoints;
1124 rupts->hwSystemManagements = per_proc->hwCtr.hwSystemManagements;
1125 rupts->hwAltivecAssists = per_proc->hwCtr.hwAltivecAssists;
1126 rupts->hwThermal = per_proc->hwCtr.hwThermal;
1127 rupts->hwSoftPatches = per_proc->hwCtr.hwSoftPatches;
1128 rupts->hwMaintenances = per_proc->hwCtr.hwMaintenances;
1129 rupts->hwInstrumentations = per_proc->hwCtr.hwInstrumentations;
1130
1131 ml_set_interrupts_enabled(oldlevel);
1132 return KERN_SUCCESS;
1133 } else {
1134 return KERN_FAILURE;
1135 }
1136 }
1137
1138 __private_extern__
1139 kern_return_t chudxnu_clear_cpu_interrupt_counters(int cpu)
1140 {
1141 if(cpu<0 || cpu>=chudxnu_phys_cpu_count()) { // check sanity of cpu argument
1142 return KERN_FAILURE;
1143 }
1144
1145 bzero((char *)&(PerProcTable[cpu].ppe_vaddr->hwCtr), sizeof(struct hwCtrs));
1146 return KERN_SUCCESS;
1147 }
1148
1149 #pragma mark **** alignment exceptions ****
1150
1151 __private_extern__
1152 kern_return_t chudxnu_passup_alignment_exceptions(boolean_t enable)
1153 {
1154 if(enable) {
1155 dgWork.dgFlags |= enaNotifyEM;
1156 } else {
1157 dgWork.dgFlags &= ~enaNotifyEM;
1158 }
1159 return KERN_SUCCESS;
1160 }
1161
1162 #pragma mark **** scom ****
1163 kern_return_t chudxnu_scom_read(uint32_t reg, uint64_t *data)
1164 {
1165 ml_scom_read(reg, data);
1166 return KERN_SUCCESS;
1167 }
1168
1169 kern_return_t chudxnu_scom_write(uint32_t reg, uint64_t data)
1170 {
1171 ml_scom_write(reg, data);
1172 return KERN_SUCCESS;
1173 }
1174
1175 #pragma mark *** deprecated ***
1176
1177 //DEPRECATED
1178 __private_extern__ kern_return_t
1179 chudxnu_get_cpu_rupt_counters(int cpu, rupt_counters_t *rupts) {
1180 return chudxnu_get_cpu_interrupt_counters(cpu, rupts);
1181 }
1182
1183 //DEPRECATED
1184 __private_extern__ kern_return_t
1185 chudxnu_clear_cpu_rupt_counters(int cpu) {
1186 return chudxnu_clear_cpu_interrupt_counters(cpu);
1187 }
1188
1189 //DEPRECATED
1190 __private_extern__
1191 void chudxnu_flush_caches(void)
1192 {
1193 cacheInit();
1194 }
1195
1196 //DEPRECATED
1197 __private_extern__
1198 void chudxnu_enable_caches(boolean_t enable)
1199 {
1200 if(!enable) {
1201 cacheInit();
1202 cacheDisable();
1203 } else {
1204 cacheInit();
1205 }
1206 }
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