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[apple/xnu.git] / osfmk / mach / i386 / _structs.h
1 /*
2 * Copyright (c) 2004-2006 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31
32 #ifndef _MACH_I386__STRUCTS_H_
33 #define _MACH_I386__STRUCTS_H_
34
35 #include <sys/cdefs.h> /* __DARWIN_UNIX03 */
36 #include <machine/types.h> /* __uint8_t */
37
38 /*
39 * i386 is the structure that is exported to user threads for
40 * use in status/mutate calls. This structure should never change.
41 *
42 */
43
44 #if __DARWIN_UNIX03
45 #define _STRUCT_X86_THREAD_STATE32 struct __darwin_i386_thread_state
46 _STRUCT_X86_THREAD_STATE32
47 {
48 unsigned int __eax;
49 unsigned int __ebx;
50 unsigned int __ecx;
51 unsigned int __edx;
52 unsigned int __edi;
53 unsigned int __esi;
54 unsigned int __ebp;
55 unsigned int __esp;
56 unsigned int __ss;
57 unsigned int __eflags;
58 unsigned int __eip;
59 unsigned int __cs;
60 unsigned int __ds;
61 unsigned int __es;
62 unsigned int __fs;
63 unsigned int __gs;
64 };
65 #else /* !__DARWIN_UNIX03 */
66 #define _STRUCT_X86_THREAD_STATE32 struct i386_thread_state
67 _STRUCT_X86_THREAD_STATE32
68 {
69 unsigned int eax;
70 unsigned int ebx;
71 unsigned int ecx;
72 unsigned int edx;
73 unsigned int edi;
74 unsigned int esi;
75 unsigned int ebp;
76 unsigned int esp;
77 unsigned int ss;
78 unsigned int eflags;
79 unsigned int eip;
80 unsigned int cs;
81 unsigned int ds;
82 unsigned int es;
83 unsigned int fs;
84 unsigned int gs;
85 };
86 #endif /* !__DARWIN_UNIX03 */
87
88 /* This structure should be double-word aligned for performance */
89
90 #if __DARWIN_UNIX03
91 #define _STRUCT_FP_CONTROL struct __darwin_fp_control
92 _STRUCT_FP_CONTROL
93 {
94 unsigned short __invalid :1,
95 __denorm :1,
96 __zdiv :1,
97 __ovrfl :1,
98 __undfl :1,
99 __precis :1,
100 :2,
101 __pc :2,
102 #if !defined(_POSIX_C_SOURCE) || defined(_DARWIN_C_SOURCE)
103 #define FP_PREC_24B 0
104 #define FP_PREC_53B 2
105 #define FP_PREC_64B 3
106 #endif /* !_POSIX_C_SOURCE || _DARWIN_C_SOURCE */
107 __rc :2,
108 #if !defined(_POSIX_C_SOURCE) || defined(_DARWIN_C_SOURCE)
109 #define FP_RND_NEAR 0
110 #define FP_RND_DOWN 1
111 #define FP_RND_UP 2
112 #define FP_CHOP 3
113 #endif /* !_POSIX_C_SOURCE || _DARWIN_C_SOURCE */
114 /*inf*/ :1,
115 :3;
116 };
117 typedef _STRUCT_FP_CONTROL __darwin_fp_control_t;
118 #else /* !__DARWIN_UNIX03 */
119 #define _STRUCT_FP_CONTROL struct fp_control
120 _STRUCT_FP_CONTROL
121 {
122 unsigned short invalid :1,
123 denorm :1,
124 zdiv :1,
125 ovrfl :1,
126 undfl :1,
127 precis :1,
128 :2,
129 pc :2,
130 #define FP_PREC_24B 0
131 #define FP_PREC_53B 2
132 #define FP_PREC_64B 3
133 rc :2,
134 #define FP_RND_NEAR 0
135 #define FP_RND_DOWN 1
136 #define FP_RND_UP 2
137 #define FP_CHOP 3
138 /*inf*/ :1,
139 :3;
140 };
141 typedef _STRUCT_FP_CONTROL fp_control_t;
142 #endif /* !__DARWIN_UNIX03 */
143
144 /*
145 * Status word.
146 */
147
148 #if __DARWIN_UNIX03
149 #define _STRUCT_FP_STATUS struct __darwin_fp_status
150 _STRUCT_FP_STATUS
151 {
152 unsigned short __invalid :1,
153 __denorm :1,
154 __zdiv :1,
155 __ovrfl :1,
156 __undfl :1,
157 __precis :1,
158 __stkflt :1,
159 __errsumm :1,
160 __c0 :1,
161 __c1 :1,
162 __c2 :1,
163 __tos :3,
164 __c3 :1,
165 __busy :1;
166 };
167 typedef _STRUCT_FP_STATUS __darwin_fp_status_t;
168 #else /* !__DARWIN_UNIX03 */
169 #define _STRUCT_FP_STATUS struct fp_status
170 _STRUCT_FP_STATUS
171 {
172 unsigned short invalid :1,
173 denorm :1,
174 zdiv :1,
175 ovrfl :1,
176 undfl :1,
177 precis :1,
178 stkflt :1,
179 errsumm :1,
180 c0 :1,
181 c1 :1,
182 c2 :1,
183 tos :3,
184 c3 :1,
185 busy :1;
186 };
187 typedef _STRUCT_FP_STATUS fp_status_t;
188 #endif /* !__DARWIN_UNIX03 */
189
190 /* defn of 80bit x87 FPU or MMX register */
191
192 #if __DARWIN_UNIX03
193 #define _STRUCT_MMST_REG struct __darwin_mmst_reg
194 _STRUCT_MMST_REG
195 {
196 char __mmst_reg[10];
197 char __mmst_rsrv[6];
198 };
199 #else /* !__DARWIN_UNIX03 */
200 #define _STRUCT_MMST_REG struct mmst_reg
201 _STRUCT_MMST_REG
202 {
203 char mmst_reg[10];
204 char mmst_rsrv[6];
205 };
206 #endif /* !__DARWIN_UNIX03 */
207
208
209 /* defn of 128 bit XMM regs */
210
211 #if __DARWIN_UNIX03
212 #define _STRUCT_XMM_REG struct __darwin_xmm_reg
213 _STRUCT_XMM_REG
214 {
215 char __xmm_reg[16];
216 };
217 #else /* !__DARWIN_UNIX03 */
218 #define _STRUCT_XMM_REG struct xmm_reg
219 _STRUCT_XMM_REG
220 {
221 char xmm_reg[16];
222 };
223 #endif /* !__DARWIN_UNIX03 */
224
225 #if !defined(RC_HIDE_XNU_J137)
226 /* defn of 256 bit YMM regs */
227
228 #if __DARWIN_UNIX03
229 #define _STRUCT_YMM_REG struct __darwin_ymm_reg
230 _STRUCT_YMM_REG
231 {
232 char __ymm_reg[32];
233 };
234 #else /* !__DARWIN_UNIX03 */
235 #define _STRUCT_YMM_REG struct ymm_reg
236 _STRUCT_YMM_REG
237 {
238 char ymm_reg[32];
239 };
240 #endif /* !__DARWIN_UNIX03 */
241
242 /* defn of 512 bit ZMM regs */
243
244 #if __DARWIN_UNIX03
245 #define _STRUCT_ZMM_REG struct __darwin_zmm_reg
246 _STRUCT_ZMM_REG
247 {
248 char __zmm_reg[64];
249 };
250 #else /* !__DARWIN_UNIX03 */
251 #define _STRUCT_ZMM_REG struct zmm_reg
252 _STRUCT_ZMM_REG
253 {
254 char zmm_reg[64];
255 };
256 #endif /* !__DARWIN_UNIX03 */
257
258 #if __DARWIN_UNIX03
259 #define _STRUCT_OPMASK_REG struct __darwin_opmask_reg
260 _STRUCT_OPMASK_REG
261 {
262 char __opmask_reg[8];
263 };
264 #else /* !__DARWIN_UNIX03 */
265 #define _STRUCT_OPMASK_REG struct opmask_reg
266 _STRUCT_OPMASK_REG
267 {
268 char opmask_reg[8];
269 };
270 #endif /* !__DARWIN_UNIX03 */
271 #endif /* not RC_HIDE_XNU_J137 */
272
273 /*
274 * Floating point state.
275 */
276
277 #if !defined(_POSIX_C_SOURCE) || defined(_DARWIN_C_SOURCE)
278 #define FP_STATE_BYTES 512 /* number of chars worth of data from fpu_fcw */
279 #endif /* !_POSIX_C_SOURCE || _DARWIN_C_SOURCE */
280
281 #if __DARWIN_UNIX03
282 #define _STRUCT_X86_FLOAT_STATE32 struct __darwin_i386_float_state
283 _STRUCT_X86_FLOAT_STATE32
284 {
285 int __fpu_reserved[2];
286 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
287 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
288 __uint8_t __fpu_ftw; /* x87 FPU tag word */
289 __uint8_t __fpu_rsrv1; /* reserved */
290 __uint16_t __fpu_fop; /* x87 FPU Opcode */
291 __uint32_t __fpu_ip; /* x87 FPU Instruction Pointer offset */
292 __uint16_t __fpu_cs; /* x87 FPU Instruction Pointer Selector */
293 __uint16_t __fpu_rsrv2; /* reserved */
294 __uint32_t __fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
295 __uint16_t __fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
296 __uint16_t __fpu_rsrv3; /* reserved */
297 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
298 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
299 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
300 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
301 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
302 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
303 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
304 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
305 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
306 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
307 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
308 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
309 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
310 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
311 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
312 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
313 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
314 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
315 char __fpu_rsrv4[14*16]; /* reserved */
316 int __fpu_reserved1;
317 };
318
319 #define _STRUCT_X86_AVX_STATE32 struct __darwin_i386_avx_state
320 _STRUCT_X86_AVX_STATE32
321 {
322 int __fpu_reserved[2];
323 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
324 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
325 __uint8_t __fpu_ftw; /* x87 FPU tag word */
326 __uint8_t __fpu_rsrv1; /* reserved */
327 __uint16_t __fpu_fop; /* x87 FPU Opcode */
328 __uint32_t __fpu_ip; /* x87 FPU Instruction Pointer offset */
329 __uint16_t __fpu_cs; /* x87 FPU Instruction Pointer Selector */
330 __uint16_t __fpu_rsrv2; /* reserved */
331 __uint32_t __fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
332 __uint16_t __fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
333 __uint16_t __fpu_rsrv3; /* reserved */
334 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
335 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
336 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
337 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
338 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
339 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
340 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
341 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
342 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
343 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
344 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
345 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
346 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
347 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
348 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
349 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
350 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
351 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
352 char __fpu_rsrv4[14*16]; /* reserved */
353 int __fpu_reserved1;
354 char __avx_reserved1[64];
355 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
356 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
357 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
358 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
359 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
360 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
361 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
362 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
363 };
364
365 #if !defined(RC_HIDE_XNU_J137)
366 #define _STRUCT_X86_AVX512_STATE32 struct __darwin_i386_avx512_state
367 _STRUCT_X86_AVX512_STATE32
368 {
369 int __fpu_reserved[2];
370 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
371 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
372 __uint8_t __fpu_ftw; /* x87 FPU tag word */
373 __uint8_t __fpu_rsrv1; /* reserved */
374 __uint16_t __fpu_fop; /* x87 FPU Opcode */
375 __uint32_t __fpu_ip; /* x87 FPU Instruction Pointer offset */
376 __uint16_t __fpu_cs; /* x87 FPU Instruction Pointer Selector */
377 __uint16_t __fpu_rsrv2; /* reserved */
378 __uint32_t __fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
379 __uint16_t __fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
380 __uint16_t __fpu_rsrv3; /* reserved */
381 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
382 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
383 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
384 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
385 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
386 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
387 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
388 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
389 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
390 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
391 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
392 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
393 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
394 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
395 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
396 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
397 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
398 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
399 char __fpu_rsrv4[14*16]; /* reserved */
400 int __fpu_reserved1;
401 char __avx_reserved1[64];
402 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
403 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
404 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
405 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
406 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
407 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
408 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
409 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
410 _STRUCT_OPMASK_REG __fpu_k0; /* K0 */
411 _STRUCT_OPMASK_REG __fpu_k1; /* K1 */
412 _STRUCT_OPMASK_REG __fpu_k2; /* K2 */
413 _STRUCT_OPMASK_REG __fpu_k3; /* K3 */
414 _STRUCT_OPMASK_REG __fpu_k4; /* K4 */
415 _STRUCT_OPMASK_REG __fpu_k5; /* K5 */
416 _STRUCT_OPMASK_REG __fpu_k6; /* K6 */
417 _STRUCT_OPMASK_REG __fpu_k7; /* K7 */
418 _STRUCT_YMM_REG __fpu_zmmh0; /* ZMMH 0 */
419 _STRUCT_YMM_REG __fpu_zmmh1; /* ZMMH 1 */
420 _STRUCT_YMM_REG __fpu_zmmh2; /* ZMMH 2 */
421 _STRUCT_YMM_REG __fpu_zmmh3; /* ZMMH 3 */
422 _STRUCT_YMM_REG __fpu_zmmh4; /* ZMMH 4 */
423 _STRUCT_YMM_REG __fpu_zmmh5; /* ZMMH 5 */
424 _STRUCT_YMM_REG __fpu_zmmh6; /* ZMMH 6 */
425 _STRUCT_YMM_REG __fpu_zmmh7; /* ZMMH 7 */
426 };
427 #endif /* not RC_HIDE_XNU_J137 */
428
429 #else /* !__DARWIN_UNIX03 */
430 #define _STRUCT_X86_FLOAT_STATE32 struct i386_float_state
431 _STRUCT_X86_FLOAT_STATE32
432 {
433 int fpu_reserved[2];
434 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
435 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
436 __uint8_t fpu_ftw; /* x87 FPU tag word */
437 __uint8_t fpu_rsrv1; /* reserved */
438 __uint16_t fpu_fop; /* x87 FPU Opcode */
439 __uint32_t fpu_ip; /* x87 FPU Instruction Pointer offset */
440 __uint16_t fpu_cs; /* x87 FPU Instruction Pointer Selector */
441 __uint16_t fpu_rsrv2; /* reserved */
442 __uint32_t fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
443 __uint16_t fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
444 __uint16_t fpu_rsrv3; /* reserved */
445 __uint32_t fpu_mxcsr; /* MXCSR Register state */
446 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
447 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
448 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
449 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
450 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
451 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
452 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
453 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
454 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
455 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
456 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
457 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
458 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
459 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
460 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
461 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
462 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
463 char fpu_rsrv4[14*16]; /* reserved */
464 int fpu_reserved1;
465 };
466
467 #define _STRUCT_X86_AVX_STATE32 struct i386_avx_state
468 _STRUCT_X86_AVX_STATE32
469 {
470 int fpu_reserved[2];
471 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
472 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
473 __uint8_t fpu_ftw; /* x87 FPU tag word */
474 __uint8_t fpu_rsrv1; /* reserved */
475 __uint16_t fpu_fop; /* x87 FPU Opcode */
476 __uint32_t fpu_ip; /* x87 FPU Instruction Pointer offset */
477 __uint16_t fpu_cs; /* x87 FPU Instruction Pointer Selector */
478 __uint16_t fpu_rsrv2; /* reserved */
479 __uint32_t fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
480 __uint16_t fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
481 __uint16_t fpu_rsrv3; /* reserved */
482 __uint32_t fpu_mxcsr; /* MXCSR Register state */
483 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
484 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
485 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
486 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
487 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
488 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
489 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
490 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
491 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
492 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
493 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
494 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
495 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
496 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
497 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
498 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
499 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
500 char fpu_rsrv4[14*16]; /* reserved */
501 int fpu_reserved1;
502 char avx_reserved1[64];
503 _STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
504 _STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
505 _STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
506 _STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
507 _STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
508 _STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
509 _STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
510 _STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
511 };
512
513 #if !defined(RC_HIDE_XNU_J137)
514 #define _STRUCT_X86_AVX512_STATE32 struct i386_avx512_state
515 _STRUCT_X86_AVX512_STATE32
516 {
517 int fpu_reserved[2];
518 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
519 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
520 __uint8_t fpu_ftw; /* x87 FPU tag word */
521 __uint8_t fpu_rsrv1; /* reserved */
522 __uint16_t fpu_fop; /* x87 FPU Opcode */
523 __uint32_t fpu_ip; /* x87 FPU Instruction Pointer offset */
524 __uint16_t fpu_cs; /* x87 FPU Instruction Pointer Selector */
525 __uint16_t fpu_rsrv2; /* reserved */
526 __uint32_t fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
527 __uint16_t fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
528 __uint16_t fpu_rsrv3; /* reserved */
529 __uint32_t fpu_mxcsr; /* MXCSR Register state */
530 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
531 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
532 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
533 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
534 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
535 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
536 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
537 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
538 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
539 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
540 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
541 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
542 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
543 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
544 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
545 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
546 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
547 char fpu_rsrv4[14*16]; /* reserved */
548 int fpu_reserved1;
549 char avx_reserved1[64];
550 _STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
551 _STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
552 _STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
553 _STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
554 _STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
555 _STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
556 _STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
557 _STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
558 _STRUCT_OPMASK_REG fpu_k0; /* K0 */
559 _STRUCT_OPMASK_REG fpu_k1; /* K1 */
560 _STRUCT_OPMASK_REG fpu_k2; /* K2 */
561 _STRUCT_OPMASK_REG fpu_k3; /* K3 */
562 _STRUCT_OPMASK_REG fpu_k4; /* K4 */
563 _STRUCT_OPMASK_REG fpu_k5; /* K5 */
564 _STRUCT_OPMASK_REG fpu_k6; /* K6 */
565 _STRUCT_OPMASK_REG fpu_k7; /* K7 */
566 _STRUCT_YMM_REG fpu_zmmh0; /* ZMMH 0 */
567 _STRUCT_YMM_REG fpu_zmmh1; /* ZMMH 1 */
568 _STRUCT_YMM_REG fpu_zmmh2; /* ZMMH 2 */
569 _STRUCT_YMM_REG fpu_zmmh3; /* ZMMH 3 */
570 _STRUCT_YMM_REG fpu_zmmh4; /* ZMMH 4 */
571 _STRUCT_YMM_REG fpu_zmmh5; /* ZMMH 5 */
572 _STRUCT_YMM_REG fpu_zmmh6; /* ZMMH 6 */
573 _STRUCT_YMM_REG fpu_zmmh7; /* ZMMH 7 */
574 };
575 #endif /* not RC_HIDE_XNU_J137 */
576
577 #endif /* !__DARWIN_UNIX03 */
578
579 #if __DARWIN_UNIX03
580 #define _STRUCT_X86_EXCEPTION_STATE32 struct __darwin_i386_exception_state
581 _STRUCT_X86_EXCEPTION_STATE32
582 {
583 __uint16_t __trapno;
584 __uint16_t __cpu;
585 __uint32_t __err;
586 __uint32_t __faultvaddr;
587 };
588 #else /* !__DARWIN_UNIX03 */
589 #define _STRUCT_X86_EXCEPTION_STATE32 struct i386_exception_state
590 _STRUCT_X86_EXCEPTION_STATE32
591 {
592 __uint16_t trapno;
593 __uint16_t cpu;
594 __uint32_t err;
595 __uint32_t faultvaddr;
596 };
597 #endif /* !__DARWIN_UNIX03 */
598
599 #if __DARWIN_UNIX03
600 #define _STRUCT_X86_DEBUG_STATE32 struct __darwin_x86_debug_state32
601 _STRUCT_X86_DEBUG_STATE32
602 {
603 unsigned int __dr0;
604 unsigned int __dr1;
605 unsigned int __dr2;
606 unsigned int __dr3;
607 unsigned int __dr4;
608 unsigned int __dr5;
609 unsigned int __dr6;
610 unsigned int __dr7;
611 };
612 #else /* !__DARWIN_UNIX03 */
613 #define _STRUCT_X86_DEBUG_STATE32 struct x86_debug_state32
614 _STRUCT_X86_DEBUG_STATE32
615 {
616 unsigned int dr0;
617 unsigned int dr1;
618 unsigned int dr2;
619 unsigned int dr3;
620 unsigned int dr4;
621 unsigned int dr5;
622 unsigned int dr6;
623 unsigned int dr7;
624 };
625 #endif /* !__DARWIN_UNIX03 */
626
627 #define _STRUCT_X86_PAGEIN_STATE struct __x86_pagein_state
628 _STRUCT_X86_PAGEIN_STATE
629 {
630 int __pagein_error;
631 };
632
633 /*
634 * 64 bit versions of the above
635 */
636
637 #if __DARWIN_UNIX03
638 #define _STRUCT_X86_THREAD_STATE64 struct __darwin_x86_thread_state64
639 _STRUCT_X86_THREAD_STATE64
640 {
641 __uint64_t __rax;
642 __uint64_t __rbx;
643 __uint64_t __rcx;
644 __uint64_t __rdx;
645 __uint64_t __rdi;
646 __uint64_t __rsi;
647 __uint64_t __rbp;
648 __uint64_t __rsp;
649 __uint64_t __r8;
650 __uint64_t __r9;
651 __uint64_t __r10;
652 __uint64_t __r11;
653 __uint64_t __r12;
654 __uint64_t __r13;
655 __uint64_t __r14;
656 __uint64_t __r15;
657 __uint64_t __rip;
658 __uint64_t __rflags;
659 __uint64_t __cs;
660 __uint64_t __fs;
661 __uint64_t __gs;
662 };
663 #else /* !__DARWIN_UNIX03 */
664 #define _STRUCT_X86_THREAD_STATE64 struct x86_thread_state64
665 _STRUCT_X86_THREAD_STATE64
666 {
667 __uint64_t rax;
668 __uint64_t rbx;
669 __uint64_t rcx;
670 __uint64_t rdx;
671 __uint64_t rdi;
672 __uint64_t rsi;
673 __uint64_t rbp;
674 __uint64_t rsp;
675 __uint64_t r8;
676 __uint64_t r9;
677 __uint64_t r10;
678 __uint64_t r11;
679 __uint64_t r12;
680 __uint64_t r13;
681 __uint64_t r14;
682 __uint64_t r15;
683 __uint64_t rip;
684 __uint64_t rflags;
685 __uint64_t cs;
686 __uint64_t fs;
687 __uint64_t gs;
688 };
689 #endif /* !__DARWIN_UNIX03 */
690
691 /*
692 * 64 bit versions of the above (complete)
693 */
694
695 #if __DARWIN_UNIX03
696 #define _STRUCT_X86_THREAD_FULL_STATE64 struct __darwin_x86_thread_full_state64
697 _STRUCT_X86_THREAD_FULL_STATE64
698 {
699 _STRUCT_X86_THREAD_STATE64 __ss64;
700 __uint64_t __ds;
701 __uint64_t __es;
702 __uint64_t __ss;
703 __uint64_t __gsbase;
704 };
705 #else /* !__DARWIN_UNIX03 */
706 #define _STRUCT_X86_THREAD_FULL_STATE64 struct x86_thread_full_state64
707 _STRUCT_X86_THREAD_FULL_STATE64
708 {
709 _STRUCT_X86_THREAD_STATE64 ss64;
710 __uint64_t ds;
711 __uint64_t es;
712 __uint64_t ss;
713 __uint64_t gsbase;
714 };
715 #endif /* !__DARWIN_UNIX03 */
716
717
718 #if __DARWIN_UNIX03
719 #define _STRUCT_X86_FLOAT_STATE64 struct __darwin_x86_float_state64
720 _STRUCT_X86_FLOAT_STATE64
721 {
722 int __fpu_reserved[2];
723 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
724 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
725 __uint8_t __fpu_ftw; /* x87 FPU tag word */
726 __uint8_t __fpu_rsrv1; /* reserved */
727 __uint16_t __fpu_fop; /* x87 FPU Opcode */
728
729 /* x87 FPU Instruction Pointer */
730 __uint32_t __fpu_ip; /* offset */
731 __uint16_t __fpu_cs; /* Selector */
732
733 __uint16_t __fpu_rsrv2; /* reserved */
734
735 /* x87 FPU Instruction Operand(Data) Pointer */
736 __uint32_t __fpu_dp; /* offset */
737 __uint16_t __fpu_ds; /* Selector */
738
739 __uint16_t __fpu_rsrv3; /* reserved */
740 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
741 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
742 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
743 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
744 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
745 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
746 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
747 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
748 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
749 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
750 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
751 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
752 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
753 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
754 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
755 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
756 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
757 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
758 _STRUCT_XMM_REG __fpu_xmm8; /* XMM 8 */
759 _STRUCT_XMM_REG __fpu_xmm9; /* XMM 9 */
760 _STRUCT_XMM_REG __fpu_xmm10; /* XMM 10 */
761 _STRUCT_XMM_REG __fpu_xmm11; /* XMM 11 */
762 _STRUCT_XMM_REG __fpu_xmm12; /* XMM 12 */
763 _STRUCT_XMM_REG __fpu_xmm13; /* XMM 13 */
764 _STRUCT_XMM_REG __fpu_xmm14; /* XMM 14 */
765 _STRUCT_XMM_REG __fpu_xmm15; /* XMM 15 */
766 char __fpu_rsrv4[6*16]; /* reserved */
767 int __fpu_reserved1;
768 };
769
770 #define _STRUCT_X86_AVX_STATE64 struct __darwin_x86_avx_state64
771 _STRUCT_X86_AVX_STATE64
772 {
773 int __fpu_reserved[2];
774 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
775 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
776 __uint8_t __fpu_ftw; /* x87 FPU tag word */
777 __uint8_t __fpu_rsrv1; /* reserved */
778 __uint16_t __fpu_fop; /* x87 FPU Opcode */
779
780 /* x87 FPU Instruction Pointer */
781 __uint32_t __fpu_ip; /* offset */
782 __uint16_t __fpu_cs; /* Selector */
783
784 __uint16_t __fpu_rsrv2; /* reserved */
785
786 /* x87 FPU Instruction Operand(Data) Pointer */
787 __uint32_t __fpu_dp; /* offset */
788 __uint16_t __fpu_ds; /* Selector */
789
790 __uint16_t __fpu_rsrv3; /* reserved */
791 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
792 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
793 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
794 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
795 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
796 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
797 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
798 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
799 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
800 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
801 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
802 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
803 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
804 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
805 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
806 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
807 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
808 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
809 _STRUCT_XMM_REG __fpu_xmm8; /* XMM 8 */
810 _STRUCT_XMM_REG __fpu_xmm9; /* XMM 9 */
811 _STRUCT_XMM_REG __fpu_xmm10; /* XMM 10 */
812 _STRUCT_XMM_REG __fpu_xmm11; /* XMM 11 */
813 _STRUCT_XMM_REG __fpu_xmm12; /* XMM 12 */
814 _STRUCT_XMM_REG __fpu_xmm13; /* XMM 13 */
815 _STRUCT_XMM_REG __fpu_xmm14; /* XMM 14 */
816 _STRUCT_XMM_REG __fpu_xmm15; /* XMM 15 */
817 char __fpu_rsrv4[6*16]; /* reserved */
818 int __fpu_reserved1;
819 char __avx_reserved1[64];
820 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
821 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
822 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
823 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
824 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
825 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
826 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
827 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
828 _STRUCT_XMM_REG __fpu_ymmh8; /* YMMH 8 */
829 _STRUCT_XMM_REG __fpu_ymmh9; /* YMMH 9 */
830 _STRUCT_XMM_REG __fpu_ymmh10; /* YMMH 10 */
831 _STRUCT_XMM_REG __fpu_ymmh11; /* YMMH 11 */
832 _STRUCT_XMM_REG __fpu_ymmh12; /* YMMH 12 */
833 _STRUCT_XMM_REG __fpu_ymmh13; /* YMMH 13 */
834 _STRUCT_XMM_REG __fpu_ymmh14; /* YMMH 14 */
835 _STRUCT_XMM_REG __fpu_ymmh15; /* YMMH 15 */
836 };
837
838 #if !defined(RC_HIDE_XNU_J137)
839 #define _STRUCT_X86_AVX512_STATE64 struct __darwin_x86_avx512_state64
840 _STRUCT_X86_AVX512_STATE64
841 {
842 int __fpu_reserved[2];
843 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
844 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
845 __uint8_t __fpu_ftw; /* x87 FPU tag word */
846 __uint8_t __fpu_rsrv1; /* reserved */
847 __uint16_t __fpu_fop; /* x87 FPU Opcode */
848
849 /* x87 FPU Instruction Pointer */
850 __uint32_t __fpu_ip; /* offset */
851 __uint16_t __fpu_cs; /* Selector */
852
853 __uint16_t __fpu_rsrv2; /* reserved */
854
855 /* x87 FPU Instruction Operand(Data) Pointer */
856 __uint32_t __fpu_dp; /* offset */
857 __uint16_t __fpu_ds; /* Selector */
858
859 __uint16_t __fpu_rsrv3; /* reserved */
860 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
861 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
862 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
863 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
864 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
865 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
866 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
867 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
868 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
869 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
870 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
871 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
872 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
873 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
874 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
875 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
876 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
877 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
878 _STRUCT_XMM_REG __fpu_xmm8; /* XMM 8 */
879 _STRUCT_XMM_REG __fpu_xmm9; /* XMM 9 */
880 _STRUCT_XMM_REG __fpu_xmm10; /* XMM 10 */
881 _STRUCT_XMM_REG __fpu_xmm11; /* XMM 11 */
882 _STRUCT_XMM_REG __fpu_xmm12; /* XMM 12 */
883 _STRUCT_XMM_REG __fpu_xmm13; /* XMM 13 */
884 _STRUCT_XMM_REG __fpu_xmm14; /* XMM 14 */
885 _STRUCT_XMM_REG __fpu_xmm15; /* XMM 15 */
886 char __fpu_rsrv4[6*16]; /* reserved */
887 int __fpu_reserved1;
888 char __avx_reserved1[64];
889 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
890 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
891 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
892 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
893 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
894 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
895 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
896 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
897 _STRUCT_XMM_REG __fpu_ymmh8; /* YMMH 8 */
898 _STRUCT_XMM_REG __fpu_ymmh9; /* YMMH 9 */
899 _STRUCT_XMM_REG __fpu_ymmh10; /* YMMH 10 */
900 _STRUCT_XMM_REG __fpu_ymmh11; /* YMMH 11 */
901 _STRUCT_XMM_REG __fpu_ymmh12; /* YMMH 12 */
902 _STRUCT_XMM_REG __fpu_ymmh13; /* YMMH 13 */
903 _STRUCT_XMM_REG __fpu_ymmh14; /* YMMH 14 */
904 _STRUCT_XMM_REG __fpu_ymmh15; /* YMMH 15 */
905 _STRUCT_OPMASK_REG __fpu_k0; /* K0 */
906 _STRUCT_OPMASK_REG __fpu_k1; /* K1 */
907 _STRUCT_OPMASK_REG __fpu_k2; /* K2 */
908 _STRUCT_OPMASK_REG __fpu_k3; /* K3 */
909 _STRUCT_OPMASK_REG __fpu_k4; /* K4 */
910 _STRUCT_OPMASK_REG __fpu_k5; /* K5 */
911 _STRUCT_OPMASK_REG __fpu_k6; /* K6 */
912 _STRUCT_OPMASK_REG __fpu_k7; /* K7 */
913 _STRUCT_YMM_REG __fpu_zmmh0; /* ZMMH 0 */
914 _STRUCT_YMM_REG __fpu_zmmh1; /* ZMMH 1 */
915 _STRUCT_YMM_REG __fpu_zmmh2; /* ZMMH 2 */
916 _STRUCT_YMM_REG __fpu_zmmh3; /* ZMMH 3 */
917 _STRUCT_YMM_REG __fpu_zmmh4; /* ZMMH 4 */
918 _STRUCT_YMM_REG __fpu_zmmh5; /* ZMMH 5 */
919 _STRUCT_YMM_REG __fpu_zmmh6; /* ZMMH 6 */
920 _STRUCT_YMM_REG __fpu_zmmh7; /* ZMMH 7 */
921 _STRUCT_YMM_REG __fpu_zmmh8; /* ZMMH 8 */
922 _STRUCT_YMM_REG __fpu_zmmh9; /* ZMMH 9 */
923 _STRUCT_YMM_REG __fpu_zmmh10; /* ZMMH 10 */
924 _STRUCT_YMM_REG __fpu_zmmh11; /* ZMMH 11 */
925 _STRUCT_YMM_REG __fpu_zmmh12; /* ZMMH 12 */
926 _STRUCT_YMM_REG __fpu_zmmh13; /* ZMMH 13 */
927 _STRUCT_YMM_REG __fpu_zmmh14; /* ZMMH 14 */
928 _STRUCT_YMM_REG __fpu_zmmh15; /* ZMMH 15 */
929 _STRUCT_ZMM_REG __fpu_zmm16; /* ZMM 16 */
930 _STRUCT_ZMM_REG __fpu_zmm17; /* ZMM 17 */
931 _STRUCT_ZMM_REG __fpu_zmm18; /* ZMM 18 */
932 _STRUCT_ZMM_REG __fpu_zmm19; /* ZMM 19 */
933 _STRUCT_ZMM_REG __fpu_zmm20; /* ZMM 20 */
934 _STRUCT_ZMM_REG __fpu_zmm21; /* ZMM 21 */
935 _STRUCT_ZMM_REG __fpu_zmm22; /* ZMM 22 */
936 _STRUCT_ZMM_REG __fpu_zmm23; /* ZMM 23 */
937 _STRUCT_ZMM_REG __fpu_zmm24; /* ZMM 24 */
938 _STRUCT_ZMM_REG __fpu_zmm25; /* ZMM 25 */
939 _STRUCT_ZMM_REG __fpu_zmm26; /* ZMM 26 */
940 _STRUCT_ZMM_REG __fpu_zmm27; /* ZMM 27 */
941 _STRUCT_ZMM_REG __fpu_zmm28; /* ZMM 28 */
942 _STRUCT_ZMM_REG __fpu_zmm29; /* ZMM 29 */
943 _STRUCT_ZMM_REG __fpu_zmm30; /* ZMM 30 */
944 _STRUCT_ZMM_REG __fpu_zmm31; /* ZMM 31 */
945 };
946 #endif /* not RC_HIDE_XNU_J137 */
947
948 #else /* !__DARWIN_UNIX03 */
949 #define _STRUCT_X86_FLOAT_STATE64 struct x86_float_state64
950 _STRUCT_X86_FLOAT_STATE64
951 {
952 int fpu_reserved[2];
953 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
954 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
955 __uint8_t fpu_ftw; /* x87 FPU tag word */
956 __uint8_t fpu_rsrv1; /* reserved */
957 __uint16_t fpu_fop; /* x87 FPU Opcode */
958
959 /* x87 FPU Instruction Pointer */
960 __uint32_t fpu_ip; /* offset */
961 __uint16_t fpu_cs; /* Selector */
962
963 __uint16_t fpu_rsrv2; /* reserved */
964
965 /* x87 FPU Instruction Operand(Data) Pointer */
966 __uint32_t fpu_dp; /* offset */
967 __uint16_t fpu_ds; /* Selector */
968
969 __uint16_t fpu_rsrv3; /* reserved */
970 __uint32_t fpu_mxcsr; /* MXCSR Register state */
971 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
972 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
973 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
974 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
975 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
976 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
977 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
978 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
979 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
980 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
981 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
982 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
983 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
984 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
985 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
986 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
987 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
988 _STRUCT_XMM_REG fpu_xmm8; /* XMM 8 */
989 _STRUCT_XMM_REG fpu_xmm9; /* XMM 9 */
990 _STRUCT_XMM_REG fpu_xmm10; /* XMM 10 */
991 _STRUCT_XMM_REG fpu_xmm11; /* XMM 11 */
992 _STRUCT_XMM_REG fpu_xmm12; /* XMM 12 */
993 _STRUCT_XMM_REG fpu_xmm13; /* XMM 13 */
994 _STRUCT_XMM_REG fpu_xmm14; /* XMM 14 */
995 _STRUCT_XMM_REG fpu_xmm15; /* XMM 15 */
996 char fpu_rsrv4[6*16]; /* reserved */
997 int fpu_reserved1;
998 };
999
1000 #define _STRUCT_X86_AVX_STATE64 struct x86_avx_state64
1001 _STRUCT_X86_AVX_STATE64
1002 {
1003 int fpu_reserved[2];
1004 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
1005 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
1006 __uint8_t fpu_ftw; /* x87 FPU tag word */
1007 __uint8_t fpu_rsrv1; /* reserved */
1008 __uint16_t fpu_fop; /* x87 FPU Opcode */
1009
1010 /* x87 FPU Instruction Pointer */
1011 __uint32_t fpu_ip; /* offset */
1012 __uint16_t fpu_cs; /* Selector */
1013
1014 __uint16_t fpu_rsrv2; /* reserved */
1015
1016 /* x87 FPU Instruction Operand(Data) Pointer */
1017 __uint32_t fpu_dp; /* offset */
1018 __uint16_t fpu_ds; /* Selector */
1019
1020 __uint16_t fpu_rsrv3; /* reserved */
1021 __uint32_t fpu_mxcsr; /* MXCSR Register state */
1022 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
1023 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
1024 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
1025 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
1026 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
1027 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
1028 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
1029 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
1030 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
1031 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
1032 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
1033 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
1034 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
1035 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
1036 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
1037 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
1038 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
1039 _STRUCT_XMM_REG fpu_xmm8; /* XMM 8 */
1040 _STRUCT_XMM_REG fpu_xmm9; /* XMM 9 */
1041 _STRUCT_XMM_REG fpu_xmm10; /* XMM 10 */
1042 _STRUCT_XMM_REG fpu_xmm11; /* XMM 11 */
1043 _STRUCT_XMM_REG fpu_xmm12; /* XMM 12 */
1044 _STRUCT_XMM_REG fpu_xmm13; /* XMM 13 */
1045 _STRUCT_XMM_REG fpu_xmm14; /* XMM 14 */
1046 _STRUCT_XMM_REG fpu_xmm15; /* XMM 15 */
1047 char fpu_rsrv4[6*16]; /* reserved */
1048 int fpu_reserved1;
1049 char avx_reserved1[64];
1050 _STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
1051 _STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
1052 _STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
1053 _STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
1054 _STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
1055 _STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
1056 _STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
1057 _STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
1058 _STRUCT_XMM_REG fpu_ymmh8; /* YMMH 8 */
1059 _STRUCT_XMM_REG fpu_ymmh9; /* YMMH 9 */
1060 _STRUCT_XMM_REG fpu_ymmh10; /* YMMH 10 */
1061 _STRUCT_XMM_REG fpu_ymmh11; /* YMMH 11 */
1062 _STRUCT_XMM_REG fpu_ymmh12; /* YMMH 12 */
1063 _STRUCT_XMM_REG fpu_ymmh13; /* YMMH 13 */
1064 _STRUCT_XMM_REG fpu_ymmh14; /* YMMH 14 */
1065 _STRUCT_XMM_REG fpu_ymmh15; /* YMMH 15 */
1066 };
1067
1068 #if !defined(RC_HIDE_XNU_J137)
1069 #define _STRUCT_X86_AVX512_STATE64 struct x86_avx512_state64
1070 _STRUCT_X86_AVX512_STATE64
1071 {
1072 int fpu_reserved[2];
1073 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
1074 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
1075 __uint8_t fpu_ftw; /* x87 FPU tag word */
1076 __uint8_t fpu_rsrv1; /* reserved */
1077 __uint16_t fpu_fop; /* x87 FPU Opcode */
1078
1079 /* x87 FPU Instruction Pointer */
1080 __uint32_t fpu_ip; /* offset */
1081 __uint16_t fpu_cs; /* Selector */
1082
1083 __uint16_t fpu_rsrv2; /* reserved */
1084
1085 /* x87 FPU Instruction Operand(Data) Pointer */
1086 __uint32_t fpu_dp; /* offset */
1087 __uint16_t fpu_ds; /* Selector */
1088
1089 __uint16_t fpu_rsrv3; /* reserved */
1090 __uint32_t fpu_mxcsr; /* MXCSR Register state */
1091 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
1092 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
1093 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
1094 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
1095 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
1096 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
1097 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
1098 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
1099 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
1100 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
1101 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
1102 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
1103 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
1104 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
1105 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
1106 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
1107 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
1108 _STRUCT_XMM_REG fpu_xmm8; /* XMM 8 */
1109 _STRUCT_XMM_REG fpu_xmm9; /* XMM 9 */
1110 _STRUCT_XMM_REG fpu_xmm10; /* XMM 10 */
1111 _STRUCT_XMM_REG fpu_xmm11; /* XMM 11 */
1112 _STRUCT_XMM_REG fpu_xmm12; /* XMM 12 */
1113 _STRUCT_XMM_REG fpu_xmm13; /* XMM 13 */
1114 _STRUCT_XMM_REG fpu_xmm14; /* XMM 14 */
1115 _STRUCT_XMM_REG fpu_xmm15; /* XMM 15 */
1116 char fpu_rsrv4[6*16]; /* reserved */
1117 int fpu_reserved1;
1118 char avx_reserved1[64];
1119 _STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
1120 _STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
1121 _STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
1122 _STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
1123 _STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
1124 _STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
1125 _STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
1126 _STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
1127 _STRUCT_XMM_REG fpu_ymmh8; /* YMMH 8 */
1128 _STRUCT_XMM_REG fpu_ymmh9; /* YMMH 9 */
1129 _STRUCT_XMM_REG fpu_ymmh10; /* YMMH 10 */
1130 _STRUCT_XMM_REG fpu_ymmh11; /* YMMH 11 */
1131 _STRUCT_XMM_REG fpu_ymmh12; /* YMMH 12 */
1132 _STRUCT_XMM_REG fpu_ymmh13; /* YMMH 13 */
1133 _STRUCT_XMM_REG fpu_ymmh14; /* YMMH 14 */
1134 _STRUCT_XMM_REG fpu_ymmh15; /* YMMH 15 */
1135 _STRUCT_OPMASK_REG fpu_k0; /* K0 */
1136 _STRUCT_OPMASK_REG fpu_k1; /* K1 */
1137 _STRUCT_OPMASK_REG fpu_k2; /* K2 */
1138 _STRUCT_OPMASK_REG fpu_k3; /* K3 */
1139 _STRUCT_OPMASK_REG fpu_k4; /* K4 */
1140 _STRUCT_OPMASK_REG fpu_k5; /* K5 */
1141 _STRUCT_OPMASK_REG fpu_k6; /* K6 */
1142 _STRUCT_OPMASK_REG fpu_k7; /* K7 */
1143 _STRUCT_YMM_REG fpu_zmmh0; /* ZMMH 0 */
1144 _STRUCT_YMM_REG fpu_zmmh1; /* ZMMH 1 */
1145 _STRUCT_YMM_REG fpu_zmmh2; /* ZMMH 2 */
1146 _STRUCT_YMM_REG fpu_zmmh3; /* ZMMH 3 */
1147 _STRUCT_YMM_REG fpu_zmmh4; /* ZMMH 4 */
1148 _STRUCT_YMM_REG fpu_zmmh5; /* ZMMH 5 */
1149 _STRUCT_YMM_REG fpu_zmmh6; /* ZMMH 6 */
1150 _STRUCT_YMM_REG fpu_zmmh7; /* ZMMH 7 */
1151 _STRUCT_YMM_REG fpu_zmmh8; /* ZMMH 8 */
1152 _STRUCT_YMM_REG fpu_zmmh9; /* ZMMH 9 */
1153 _STRUCT_YMM_REG fpu_zmmh10; /* ZMMH 10 */
1154 _STRUCT_YMM_REG fpu_zmmh11; /* ZMMH 11 */
1155 _STRUCT_YMM_REG fpu_zmmh12; /* ZMMH 12 */
1156 _STRUCT_YMM_REG fpu_zmmh13; /* ZMMH 13 */
1157 _STRUCT_YMM_REG fpu_zmmh14; /* ZMMH 14 */
1158 _STRUCT_YMM_REG fpu_zmmh15; /* ZMMH 15 */
1159 _STRUCT_ZMM_REG fpu_zmm16; /* ZMM 16 */
1160 _STRUCT_ZMM_REG fpu_zmm17; /* ZMM 17 */
1161 _STRUCT_ZMM_REG fpu_zmm18; /* ZMM 18 */
1162 _STRUCT_ZMM_REG fpu_zmm19; /* ZMM 19 */
1163 _STRUCT_ZMM_REG fpu_zmm20; /* ZMM 20 */
1164 _STRUCT_ZMM_REG fpu_zmm21; /* ZMM 21 */
1165 _STRUCT_ZMM_REG fpu_zmm22; /* ZMM 22 */
1166 _STRUCT_ZMM_REG fpu_zmm23; /* ZMM 23 */
1167 _STRUCT_ZMM_REG fpu_zmm24; /* ZMM 24 */
1168 _STRUCT_ZMM_REG fpu_zmm25; /* ZMM 25 */
1169 _STRUCT_ZMM_REG fpu_zmm26; /* ZMM 26 */
1170 _STRUCT_ZMM_REG fpu_zmm27; /* ZMM 27 */
1171 _STRUCT_ZMM_REG fpu_zmm28; /* ZMM 28 */
1172 _STRUCT_ZMM_REG fpu_zmm29; /* ZMM 29 */
1173 _STRUCT_ZMM_REG fpu_zmm30; /* ZMM 30 */
1174 _STRUCT_ZMM_REG fpu_zmm31; /* ZMM 31 */
1175 };
1176 #endif /* not RC_HIDE_XNU_J137 */
1177
1178 #endif /* !__DARWIN_UNIX03 */
1179
1180 #if __DARWIN_UNIX03
1181 #define _STRUCT_X86_EXCEPTION_STATE64 struct __darwin_x86_exception_state64
1182 _STRUCT_X86_EXCEPTION_STATE64
1183 {
1184 __uint16_t __trapno;
1185 __uint16_t __cpu;
1186 __uint32_t __err;
1187 __uint64_t __faultvaddr;
1188 };
1189 #else /* !__DARWIN_UNIX03 */
1190 #define _STRUCT_X86_EXCEPTION_STATE64 struct x86_exception_state64
1191 _STRUCT_X86_EXCEPTION_STATE64
1192 {
1193 __uint16_t trapno;
1194 __uint16_t cpu;
1195 __uint32_t err;
1196 __uint64_t faultvaddr;
1197 };
1198 #endif /* !__DARWIN_UNIX03 */
1199
1200 #if __DARWIN_UNIX03
1201 #define _STRUCT_X86_DEBUG_STATE64 struct __darwin_x86_debug_state64
1202 _STRUCT_X86_DEBUG_STATE64
1203 {
1204 __uint64_t __dr0;
1205 __uint64_t __dr1;
1206 __uint64_t __dr2;
1207 __uint64_t __dr3;
1208 __uint64_t __dr4;
1209 __uint64_t __dr5;
1210 __uint64_t __dr6;
1211 __uint64_t __dr7;
1212 };
1213 #else /* !__DARWIN_UNIX03 */
1214 #define _STRUCT_X86_DEBUG_STATE64 struct x86_debug_state64
1215 _STRUCT_X86_DEBUG_STATE64
1216 {
1217 __uint64_t dr0;
1218 __uint64_t dr1;
1219 __uint64_t dr2;
1220 __uint64_t dr3;
1221 __uint64_t dr4;
1222 __uint64_t dr5;
1223 __uint64_t dr6;
1224 __uint64_t dr7;
1225 };
1226 #endif /* !__DARWIN_UNIX03 */
1227
1228 #if __DARWIN_UNIX03
1229 #define _STRUCT_X86_CPMU_STATE64 struct __darwin_x86_cpmu_state64
1230 _STRUCT_X86_CPMU_STATE64
1231 {
1232 __uint64_t __ctrs[16];
1233 };
1234 #else /* __DARWIN_UNIX03 */
1235 #define _STRUCT_X86_CPMU_STATE64 struct x86_cpmu_state64
1236 _STRUCT_X86_CPMU_STATE64
1237 {
1238 __uint64_t ctrs[16];
1239 };
1240 #endif /* !__DARWIN_UNIX03 */
1241
1242 #endif /* _MACH_I386__STRUCTS_H_ */
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